EVAL-ADV7533-SAZ

Data Sheet MIPI/DSI Receiver with HDMI Transmitter ADV7533 FEATURES APPLICATIONS General Low power MIPI/DSI receiver Low power HDMI/DVI transmitter ideal for portable applications CEC controller and expanded message buffer (3 messages) reduces system overhead Incorporates HDMI v.1.3 (x.v.Color™) technology Compatible with DVI v.1.0 Optional embedded HDCP keys to support HDCP 1.3 1.8 V, 1.2 V (optional), and 3.3 V supplies for ultralow operating power Audio inputs accept logic levels from 1.8 V to 3.3 V MIPI/DSI receiver 2-, 3-, or 4-lane DSI receiver Supports up to 800 Mbps per lane Compatible with DPHY V.0.90 and DSI V.1.02 Supports inputs of 16-bit RGB 4:4:4 24-bit RGB 4:4:4 30-bit RGB 4:4:4 HDMI (TMDS) video out 80 MHz operation supports all video and graphics resolutions from 480i to 1080p at 30 Hz Programmable 2-way color space converter Output supports 36-, 30-, or 24-bit RGB 4:4:4 36-, 30-, or 24-bit YCbCr 4:4:4 Automatic input video format timing detection (CEA-861E) Digital audio Supports standard S/PDIF for stereo LPCM or compressed audio up to 192 kHz 2-channel uncompressed LPCM I2S audio up to 192 kHz Special features for easy system design On-chip MPU with I2C master to perform EDID reading and HDCP operations; reports HDMI events through interrupts and registers 5 V tolerant I2C and HPD I/Os, no extra device needed No audio master clock needed for supporting S/PDIF and I2S Mobile systems Cellular handsets Digital video cameras Digital still cameras Personal media players Gaming GENERAL DESCRIPTION The ADV7533 is a multifunction video interface chip. The ADV7533 provides a mobile industry processor interface/ display serial interface (MIPI®/DSI) input port, a high definition multimedia interface (HDMI®) data output in a 49-ball wafer level chip scale package (WLCSP). The display serial interface (DSI) input provides up to four lanes of MIPI/DSI data, each running up to 800 Mbps. The DSI Rx implements DSI video mode operation only. The HDMI Tx supports video resolutions using pixel clocks of up to 80 MHz. With the optional inclusion of embedded HDCP keys, the ADV7533 allows the secure transmission of protected content, as specified by the HDCP 1.3 protocol. The ADV7533 supports x.v.Color™ (gamut metadata) for a wider color gamut. The ADV7533 supports both S/PDIF and 2-channel I2S audio. Its high fidelity 2-channel I2S can transmit stereo up to a 192 kHz sampling rate. The S/PDIF can carry stereo LPCM audio or compressed audio, including Dolby® Digital and DTS®. The ADV7533 helps to reduce system design complexity and cost by incorporating such features as an I2C master for EDID reading and 5 V tolerance on the I2C and Hot Plug™ detect pins. Fabricated in an advanced CMOS process, the ADV7533 is available in a space saving, 49-ball, WLCSP surface mount package. This package is RoHS compliant and specified to operate from −10°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. ADV7533 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................8 Applications ....................................................................................... 1 Explanation of Test Levels ............................................................8 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................9 Revision History ............................................................................... 2 Applications Information .............................................................. 11 Functional Block Diagram .............................................................. 3 Design Resources ....................................................................... 11 Specifications..................................................................................... 4 Outline Dimensions ....................................................................... 12 MIPI/DSI Specifications .............................................................. 6 Ordering Guide .......................................................................... 12 Absolute Maximum Ratings ............................................................ 8 REVISION HISTORY 8/12—Rev. 0 to Rev. A Changed Storage Temperature from −65°C to +150°C to −40°C to +85°C ............................................................................................. 8 7/11—Revision 0: Initial Version Rev. A | Page 2 of 12 Data Sheet ADV7533 R_EXT BAND GAP CTRL SDA SCL I2C SLAVE ADV7533 LRCLK SPDIF/I2S DDC_SDA I 2C MASTER DDC_SCL CEC_CLK CEC 2 4 CH DPHY DSI DECODE PATTERN GENERATOR SYNC ADJUST AND GENERATION COLOR SPACE CONVERTER UP/ DOWN DITHER 2 HDCP ENCRYPTION 2 HDMI TMDS Tx 2 2 2 HDMI_Tx0 HDMI_Tx1 HDMI_Tx2 HDMI_TxC HDCP KEYS N/V MEMORY V3P3 GND PVDD POWER Figure 1. Rev. A | Page 3 of 12 09821-001 2 V1P2 DRx3 DRxC HDCP AND EDID MICROCONTROLLER CEC CONTROLLER BUFFER 2 DVDD DRx2 AUDIO DATA CAPTURE 2 A2VDD DRx1 AVDD DRx0 SCLK/MCLK HPD INT PD FUNCTIONAL BLOCK DIAGRAM ADV7533 Data Sheet SPECIFICATIONS Table 1. Electrical Specifications Parameter DIGITAL INPUTS Data Inputs—Audio, CEC_CLK Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Capacitance I2C Lines (SDA, SCL) Input Voltage, High (VIH) Input Voltage, Low (VIL) I2C Lines (DDCSDA, DDCSCL) Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Voltage, High (VIH) Input Voltage, Low (VIL) CEC Input Voltage, High (VIH) Input Voltage, Low (VIL) Output Voltage, High (VOH) Output Voltage, Low (VOL) HPD Input Voltage, High (VIH) Input Voltage, Low (VIL) DIGITAL OUTPUTS—INT Output Voltage, Low (VOL) THERMAL CHARACTERISTICS Thermal Resistance θJC Junction-to-Case θJA Junction-to-Ambient Ambient Temperature DC SPECIFICATIONS Input Leakage Current, IIL POWER SUPPLY 1.8 V Supply Voltage (DVDD, AVDD, A2VDD, PVDD) V1P2 = (1.2 V) V1P2 = (1.8 V) Supply Voltage Noise Limit DVDD —Digital I/O Pad Logic AVDD—HDMI Analog Core V1P2—HDMI/DSI Digital Core 1.2 V 1.8 V A2VDD—MIPI DPHY PVDD—HDMI PLL 3.3 V Supply Voltage (V3P3) 3.3 V Supply Voltage Noise Limit Power-Down Current Operating Current DVDD Conditions Default values Programmable optional values Load = 5 pF Refer to Figure 2 I/O pads (30 bits at 720p) Rev. A | Page 4 of 12 Temp Test Level 1 Full Full 25°C VI VI VIII 1.4 −0.3 Full Full VI VI Full Full Full Full Min ADV7533BCBZ Typ Max Unit 3.5 +0.7 1.5 V V pF 1.3 −0.3 5.5 +0.6 V V VI VI IV IV 1.3 −0.3 3.5 −0.5 5.5 +0.6 5.5 +1.2 V V V V Full Full Full Full VI VI VI VI 2.0 2.5 −0.3 0.6 3.63 +0.6 V V V V Full Full VI VI 1.3 −0.3 5.5 +0.6 V V Full VI 0.4 V Full Full Full V V V −10 +85 °C/W °C/W °C 25°C VI −1 +1 μA Full IV 1.71 1.8 1.9 V Full Full IV IV 1.14 1.71 1.2 1.8 1.26 1.9 V V Full Full IV IV 64 64 mV rms mV rms Full Full Full Full Full Full 25°C IV Iv IV IV IV IV VI 43 64 64 15 mV rms mV rms mV rms mV rms V mV rms μA Full IV 6 mA 1.0 3.15 20 43 +25 3.30 3.45 64 Data Sheet Parameter AVDD V1P2 (1.2 V) A2VDD PVDD V3P3—HDMI/HDCP Memory Transmitter Total Power ADV7533 Conditions HDMI analog core (24 bits at 720p) HDMI/DSI digital core (DSI 30 bits/HDMI 24 bits at 720p) MIPI DPHY (30 bits/three lanes/720p) HDMI PLL (24 bits at 720p) HDMI HDCP memory 720p, 30-bit DSI in; 720p, 36-bit HDMI out; typical random pattern with CSC enabled, HDCP enabled, audio enabled ADV7533BCBZ Typ Max Unit 11 mA Temp Full Test Level 1 IV Full IV 39 mA Full IV 12 mA Full Full IV IV 11 0.3 mA mA Full Full IV VI 120 25°C 25°C 25°C IV IV VII 20 48 800 1000 Min V1P2 = 1.2 V V1P2 = 1.8 V AC SPECIFICATIONS TMDS Output Clock Frequency TMDS Output Clock Duty Cycle TMDS Differential Swing Differential Output Timing Low-to-High Transition Time High-to-Low Transition Time AUDIO AC TIMING 2 SCLK Duty Cycle When N = Even Number When N = Odd Number I2S, S/PDIF Setup, tASU I2S, S/PDIF Hold Time, tAHLD LRCLK Setup Time, tASU LRCLK Hold Time, tAHLD 25°C 25°C VII VII 75 75 175 175 Full Full Full Full Full Full IV IV IV IV IV IV 40 49 2 2 2 2 50 50 60 51 % % ns ns ns ns CEC CEC_CLK Frequency 3 CEC_CLK Accuracy CEC_CLK Duty Cycle Full Full Full VIII VIII VIII 3 −2 40 12 100 +2 60 MHz % % I2C INTERFACE SCL Clock Frequency SDA Setup Time, tDSU SDA Hold Time, tDHO Setup for Start, tSTASU Hold Time for Start, tSTAH Setup for Stop, tSTOSU Bus Free Between Stop and Start, tBUF SCL High, tHIGH SCL Low, tLOW Full Full Full Full Full Full Full Full Full VIII VIII VIII VIII VIII VIII VIII VIII VIII 400 4 kHz ns ns μs μs μs μs μs μs 1 See the Explanation of Test Levels section. 12 MHz crystal for default register settings. Only applies to S/PDIF if external MCLK is used. 4 2 I C data rates of 100 KHz and 400 KHz are supported. 2 3 Rev. A | Page 5 of 12 100 100 0.6 0.6 0.6 1.3 0.6 1.3 154 204 mW mW 112 52 1200 MHz % mV ps ps ADV7533 Data Sheet The power supply noise sensitivity of the ADV7533 is frequency dependent. Therefore, the maximum noise limit for the PVDD is specified in mV rms vs. frequency (see Figure 2). 70 NOISE LIMIT (mV rms) 60 50 40 30 20 0 1 10 100 1k 10k FREQUENCY (Hz) 09821-102 10 Figure 2. PVDD Maximum Noise Limit MIPI/DSI SPECIFICATIONS Unless noted, timing and levels comply with MIPI DPHY standards. Table 2. DSI High Speed (HS) Specifications Parameters DC SPECIFICATIONS DSI Input Common Mode Voltage DSI Input High Threshold DSI Input Low Threshold DSI Single-Ended Input High Voltage DSI Single-Ended Input Low Voltage DSI Single-Ended Threshold for Termination Enable Differential Input Impedance AC SPECIFICATIONS Single Channel Data Rate Data to Clock Setup Time Data to Clock Hold Time DSI Clock Duty Cycle Common-Mode Interference Beyond 450 MHz Common-Mode Interference 50 MHz to 450 MHz Common-Mode Termination Symbol Temp Test Level VCMRX VIDTH VIDTL VIHHS VILHS VTERM-EN ZID 25°C 25°C 25°C 25°C 25°C 25°C 25°C VII VII VII VII VII VII VII 25°C 25°C 25°C 25°C 25°C 25°C 25°C IV VII VII VII VII VII VII tSETUP tHOLD ∆VCMRX(HF) ∆VCMRX(LF) CCM Rev. A | Page 6 of 12 ADV7533 Min Typ 70 Max Unit 330 70 mV mV mV mV mV mV Ω −70 460 −40 80 200 0.15 0.15 45 −50 100 450 125 800 50 55 100 +50 60 Mbps UIINST UIINST % mV mV pF Data Sheet ADV7533 REFERENCE TIME tSETUP tHOLD 0.5UI INST+ tSKEW CLKp CLKn 09821-002 1UIINST tCLKp Figure 3. DSI Data to Clock Timing Definitions Table 3. DSI Low Power Specifications Parameter DC SPECIFICATIONS Logic 1 Input Voltage Logic 0 Input Voltage, Not in ULP State Input Hysteresis AC SPECIFICATIONS Input Pulse Rejection Minimum Pulse Width Response Peak Interference Amplitude Interference Frequency Symbol Temp Test Level Min VIH VIL VHYST 25°C 25°C 25°C VII VII VII 880 ESPIKE TMIN-RX VINT fINT 25°C 25°C 25°C 25°C VII VII VII VII Conditions Temp Test Level VPIN ILEAK VGNDSH VPIN(absmax) TVPIN(absmax) 25°C 25°C 25°C 25°C 25°C VII VII VII VII VII Typ Max Unit 550 mV mV mV 25 300 20 200 450 V × ps ns mV MHz Table 4. DSI Pin Specifications Parameter DC SPECIFICATIONS Pin Signal Voltage Range Pin Leakage Current Ground Shift Transient Pin Voltage Level Maximum Transient Time Above VPIN (Max) or Below VPIN (Min) Rev. A | Page 7 of 12 ADV7533 Min Typ −50 −10 −50 −0.15 Max Unit +1350 +10 +50 +1.45 20 mV μA mV V ns ADV7533 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Digital Inputs—I2C (DDCSDA, DDCSCL, SDA, SCL) and HPD Digital Inputs—MIPI/DSI Digital Inputs—Video/Audio Inputs, CEC_IO, CEC_CLK Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating 5.5 V to −0.3 V 1.8 V 3.63 V to −0.3 V 20 mA −10°C to +85°C −40°C to +85°C 150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION EXPLANATION OF TEST LEVELS I II III IV V VI VII VIII 100% production tested. 100% production tested at 25°C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C; guaranteed by design and characterization testing. Limits defined by HDMI specification; guaranteed by design and characterization testing. Parameter is guaranteed by design. Rev. A | Page 8 of 12 Data Sheet ADV7533 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 1 2 3 4 5 6 7 Tx2+ Tx2– Tx1+ Tx1– Tx0+ Tx0– TxC+ V3P3 GND GND AVDD GND GND TxC– PD HPD REXT PVDD GND A B C SPDIF/I2S SCLK/MCLK D DDCSCL DDCSDA LRCLK V1P2 INT CEC CECCLK GND DVDD V1P2 DVDD SDA SCL GND GND DRxC– DRx0– DRx1– DRx2– DRx3– GND DVDD DRxC+ DRx0+ DRx1+ DRx2+ DRx3+ A2VDD E F G 09821-003 ADV7533 TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. F6, G6 F5, G5 F4, G4 F3, G3 F2, G2 C3 Mnemonic DRx3−/DRx3+ DRx2−/DRx2+ DRx1−/DRx1+ DRx0−/DRx0+ DRxC−/DRxC+ PD Type1 I I I I I I C5 R_EXT I C4 HPD I C1 SPDIF/I2S I C2 SCLK/MCLK I D3 LRCLK I B7, A7 A2, A1 TxC−/TxC+ Tx2−/Tx2+ O O A4, A3 Tx1−/Tx1+ O A6, A5 Tx0−/Tx0+ O D5 INT O B4 D4, E3 AVDD V1P2 P P Description MIPI/DSI Differential Pair for Lane 3. Unused channel should be connected to ground. MIPI/DSI Differential Pair for Lane 2. Unused channel should be connected to ground. MIPI/DSI Differential Pair for Lane 1. MIPI/DSI Differential Pair for Lane 0. MIPI/DSI Differential Clock. Power-Down. Programmable polarity is determined at power-up. The I2C address and the PD polarity are set by the PD pin state when the supplies are applied to the ADV7533. Internally pulled up for 1; if 0 desired, pull down to ground with a 2 kΩ resistor. Supports typical CMOS logic levels from 1.8 V up to 3.3 V. Sets internal reference currents. Place a 1 KΩ resistor (1% tolerance) between this pin and ground. Hot Plug Detect Signal. Indicates to the interface whether the receiver is connected. 1.8 V to 5.0 V CMOS logic level. S/PDIF or I2S Audio Data Input. Represents the S/PDIF block or the two channels of audio available through I2S. Supports typical CMOS logic levels from1.8 V to 3.3 V. Audio Clock. Supports typical CMOS logic levels from1.8 V to 3.3 V. Unused input should be connected to ground. Audio Left/Right Clock Input. Supports typical CMOS logic levels from1.8 V to 3.3 V. Unused input should be connected to ground. Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic level. Differential Output Channel 2. Differential output of the red data at 10× the pixel clock rate; TMDS logic level. Differential Output Channel 1. Differential output of the green data at 10× the pixel clock rate; TMDS logic level. Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock rate; TMDS logic level. Interrupt. CMOS logic level. A 2 kΩ pull-up resistor to interrupt the microcontroller I/O supply is recommended. This is a low active signal. 1.8 V Power Supply for TMDS Outputs. Should be filtered and as quiet as possible. Digital Logic Supply (1.2 V or 1.8 V). Set to 1.2 V for lowest power consumption. Should be filtered and as quiet as possible. Rev. A | Page 9 of 12 ADV7533 Data Sheet Pin No. G7 E2, E4, G1 Mnemonic A2VDD DVDD Type1 P P C6 PVDD P B1 B2, B3, B5, B6, C7, E1, E7, F1, F7 E5 V3P3 GND P P SDA C E6 SCL C D2 DDCSDA C D1 DDCSCL C D6 D7 CEC CEC_CLK I/O I 1 Description 1.8 V Power Supply for MIPI/DPHY Input. Should be filtered and as quiet as possible. 1.8 V Power Supply for Digital and I/O Power Supply. Supply power to the digital logic and I/Os. Should be filtered and as quiet as possible. 1.8 V Power Supply for the PLL. Should be filtered and as quiet as possible. This supply is the most noise sensitive. 3.3 V programming pin for HDCP nonvolatile memory. Ground for all domains. Serial Port Data I/O. Serves as the serial port data I/O slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data Clock. Serves as the serial port data clock slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data I/O to Receiver. Serves as the master to the DDC bus. 5 V CMOS logic level. Serial Port Data Clock to Receiver. Serves as the master clock for the DDC bus. 5 V CMOS logic level. CEC I/O. If unused, pin should be connected to ground. CEC External Clock. Can be from 3 MHz to 100 MHz. Settings default to 12 MHz. If unused, pin should be connected to ground. I = input, O = output, P = power supply, C = control. Rev. A | Page 10 of 12 Data Sheet ADV7533 APPLICATIONS INFORMATION DESIGN RESOURCES Other references include the following: Analog Devices, Inc., offers the following design resources: EIA/CEA-861E, which describes audio and video infoframes as well as the E-EDID structure for HDMI. It is available from the Consumer Electronics Association (CEA). x x x x x Evaluation kits Reference design schematics Hardware and software guides Software driver reference code HDMI compliance pretest services The HDMI v.1.3, the defining document for HDMI Version 1.3, and the HDMI Compliance Test Specification Version 1.3 are available from HDMI Licensing, LLC. Other support documentation is available under the nondisclosure agreement (NDA) from ATV_VideoTx_Apps@analog.com. Rev. A | Page 11 of 12 ADV7533 Data Sheet OUTLINE DIMENSIONS 3.500 3.460 SQ 3.420 7 6 5 4 3 2 1 A BALL A1 IDENTIFIER B 3.000 REF SQ C D E F G 0.50 REF TOP VIEW (BALL SIDE DOWN) SEATING PLANE END VIEW (BALL SIDE UP) 0.390 0.360 0.330 COPLANARITY 0.05 0.360 0.320 0.280 0.270 0.240 0.210 08-17-2010-B 0.660 0.600 0.540 BOTTOM VIEW Figure 5. 49-Ball Wafer Level Chip Scale Package [WLCSP] 7 mm × 7 mm Body (CB-49-1) Dimensions shown in millimeters ORDERING GUIDE Model1 ADV7533BCBZ-RL EVAL-ADV7533-SAZ 1 Temperature Range −10°C to +85°C Package Description 49-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Package Option CB-49-1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09821-0-8/12(A) Rev. A | Page 12 of 12