LT1683
Slew Rate Controlled
Ultralow Noise Push-Pull DC/DC Controller
DESCRIPTION
FEATURES
Greatly Reduced Conducted and Radiated EMI
n Low Switching Harmonic Content
n Independent Control of Output Switch Voltage and
Current Slew Rates
n Greatly Reduced Need for External Filters
n Dual N-Channel MOSFET Drivers
n 20kHz to 250kHz Oscillator Frequency
n Easily Synchronized to External Clock
n Regulates Positive and Negative Voltages
n Easier Layout Than with Conventional Switchers
The LT ®1683 is a switching regulator controller designed to
lower conducted and radiated electromagnetic interference
(EMI). Ultralow noise and EMI are achieved by controlling
the voltage and current slew rates of external N-channel
MOSFET switches. Current and voltage slew rates can
be independently set to optimize harmonic content of
the switching waveforms vs efficiency. The LT1683 can
reduce high frequency harmonic power by as much as
40dB with only minor losses in efficiency.
The LT1683 utilizes a dual output (push-pull) current
mode architecture optimized for low noise topologies.
The IC includes gate drivers and all necessary oscillator,
control and protection circuitry. Unique error amp circuitry
can regulate both positive and negative voltages. The oscillator may be synchronized to an external clock for more
accurate placement of switching harmonics.
n
APPLICATIONS
Power Supplies for Noise Sensitive Communication
Equipment
n EMI Compliant Offline Power Supplies
n Precision Instrumentation Systems
n Isolated Supplies for Industrial Automation
n Medical Instruments
n Data Acquisition Systems
n
Protection features include gate drive lockout for low VIN,
opposite gate lockout, soft-start, output current limit,
short-circuit current limiting, gate drive overvoltage clamp
and input supply undervoltage lockout.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
DirectSense is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
Ultralow Noise 48V to 5V DC/DC Converter
48V
510Ω
0.5W
51k
39µF
63V
MIDCOM 31244
FZT853
10µF
20V
1N4148
23.2k
14
5
976Ω
6
1.2nF
7
16.9k
8
25k
3.3k
16
25k
3.3k
15
1.5k
12
CAP A
V5
GATE A
SYNC
CT
CAP B
LT1683
RT
GATE B
RVSL
CS
RCSL
PGND
VC
SS
13
GND
11
FB
NFB
10
22µH
150µF
OS-CON
17
3
VIN GCL
SHDN
0.22µF 22nF
MBRS340
8.2V
68µF
20V
11V
OPTIONAL
MBR0530
2N3904
2
5pF
22µH
A 5V/2A
2×100µF
POSCAP
5V Output Noise
(Bandwidth = 100MHz)
10pF
200V
MBRS340
1
18
B
200µVP-P
30pF
19
4 Si9422
A
200µV/DIV
10pF
200V
5pF
B
20mV/DIV
Si9422
0.1Ω
20
7.50k
9
5µs/DIV
1683 TA01a
30pF
2.49k
10nF
1683 TA01
1683fd
1
LT1683
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Supply Voltage (VIN)..................................................20V
Gate Drive Current...................................... Internal Limit
V5 Current................................................... Internal Limit
SHDN Pin Voltage......................................................20V
Feedback Pin Voltage (Trans. 10ms) ....................... ±10V
Feedback Pin Current .............................................10mA
Negative Feedback Pin Voltage (Trans. 10ms) .......... ±10V
CS Pin............................................................................5V
GCL Pin........................................................................16V
SS Pin............................................................................3V
Operating Junction Temperature Range
(Note 3)...................................................– 40°C to 125°C
Storage Temperature Range....................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
GATE A
1
20 PGND
CAP A
2
19 GATE B
GCL
3
18 CAP B
CS
4
17 VIN
V5
5
16 RVSL
SYNC
6
15 RCSL
CT
7
14 SHDN
RT
8
13 SS
FB
9
12 VC
NFB 10
11 GND
G PACKAGE
20-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 110°C/ W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT1683EG#PBF
LT1683EG#TRPBF
1683
20-Lead Plastic SSOP
– 40°C to 125°C
LT1683IG#PBF
LT1683IG#TRPBF
1683
20-Lead Plastic SSOP
– 40°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT1683EG
LT1683EG#TR
1683
20-Lead Plastic SSOP
– 40°C to 125°C
LT1683IG
LT1683IG#TR
1683
20-Lead Plastic SSOP
– 40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF , RVSL, RCSL = 16.9k, RT = 16.9k and
other pins open unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.235
V
Error Amplifiers
VREF
Reference Voltage
Measured at Feedback Pin
l
1.250
1.265
250
1000
nA
0.012
0.03
%/V
– 2.500
– 2.45
V
0.009
0.03
%/V
1500
2200
2500
µmho
µmho
IFB
Feedback Input Current
VFB = VREF
l
FBREG
Reference Voltage Line Regulation
2.7V ≤ VIN ≤ 20V
l
VNFR
Negative Feedback Reference Voltage
Measured at Negative Feedback Pin
with Feedback Pin Open
l
INFR
Negative Feedback Input Current
VNFB = VNFR
NFBREG
Negative Feedback Reference Voltage Line Regulation
2.7V ≤ VIN ≤ 20V
gm
Error Amplifier Transconductance
∆IC = ±50µA
– 2.56
– 37
l
l
1100
700
– 25
µA
1683fd
2
LT1683
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF , RVSL, RCSL = 16.9k, RT = 16.9k and
other pins open unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IESK
Error Amp Sink Current
VFB = VREF + 150mV, VC = 0.9V
l
120
200
350
µA
IESRC
Error Amp Source Current
VFB = VREF – 150mV, VC = 0.9V
l
120
200
350
µA
VCLH
Error Amp Clamp Voltage
High Clamp, VFB = 1V
1.27
V
VCLL
Error Amp Clamp Voltage
Low Clamp, VFB = 1.5V
0.12
V
AV
Error Amplifier Voltage Gain
250
V/V
FBOV
FB Overvoltage Shutdown
Outputs Drivers Disabled
1.47
V
ISS
Soft-Start Charge Current
VSS = 1V
9.0
180
12
µA
Oscillator and Sync
fMAX
Max Switch Frequency
fSYNC
Synchronization Frequency Range
VSYNC
SYNC Pin Input Threshold
RSYNC
SYNC Pin Input Resistance
250
Oscillator Frequency = 250kHz
kHz
290
l
0.7
kHz
1.4
2.0
40
kΩ
45
46
%
10
7.6
10.4
7.9
10.7
8.1
0.2
0.35
Gate Drives (Specifications Apply to Either A or B Unless Otherwise Noted)
DCMAX
Maximum Switch Duty Cycle
RVSL = RCSL = 4.85k,
Osc Frequency = 25kHz
VGON
Gate On Voltage
VIN = 12, GCL = 12
VIN = 12, GCL = 8
VGOFF
Gate Off Voltage
VIN = 12V
IGSO
Max Gate Source Current
VIN = 12V
0.3
IGSK
Max Gate Sink Current
VIN = 12V
0.3
VINUVLO
Gate Drive Undervoltage Lockout (Note 5)
VGCL = 6.5V, Gates Enabled
l
V
V
V
A
A
7.3
7.5
V
103
120
mV
230
300
mV
Current Sense
tIBL
Switch Current Limit Blanking Time
VSENSE
Sense Voltage Shutdown Voltage
VSENSEF
Sense Voltage Fault Threshold
100
VC Pulled Low
l
86
l
ns
Slew Control (for the Following Slew Tests See Test Circuit in Figure 1b)
VSLEWR
Output Voltage Slew Rising Edge
RVSL = RCSL = 17k
26
V/µs
VSLEWF
Output Voltage Slew Falling Edge
RVSL = RCSL = 17k
19
V/µs
VISLEWR
Output Current Slew Rising Edge (CS Pin Voltage)
RVSL = RCSL = 17k
0.21
V/µs
VISLEWF
Output Current Slew Falling Edge (CS Pin Voltage)
RVSL = RCSL = 17k
0.21
V/µs
Supply and Protection
VINMIN
Minimum Input Voltage (Note 4)
VGCL = VIN
l
2.55
3.6
V
IVIN
Supply Current (Note 2)
RVSL = RCSL = 17k , VIN = 12
RVSL = RCSL = 17k , VIN = 20
l
l
25
35
45
55
mA
mA
VSHDN
Shutdown Turn-On Threshold
l
1.31
1.39
1.48
V
∆VSHDN
Shutdown Turn-On Voltage Hysteresis
l
50
110
180
mV
ISHDN
Shutdown Input Current Hysteresis
l
10
24
35
µA
V5
5V Reference Voltage
6.5V ≤ VIN ≤ 20V, IV5 = 5mA
6.5V ≤ VIN ≤ 20V, IV5 = – 5mA
4.85
4.80
5
5
5.20
5.15
V
V
IV5SC
5V Reference Short-Circuit Current
VIN = 6.5V Source
VIN = 6.5V Sink
10
–10
mA
mA
1683fd
3
LT1683
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Supply current specification includes loads on each gate as in
Figure 1a. Actual supply currents vary with operating frequency, operating
voltages, V5 load, slew rates and type of external FET.
Note 3: The LT1683E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 125°C operating range
are assured by design, characterization and correlation with statistical
process controls. The LT1683I is guaranteed and tested over the – 40° to
125° operating temperature range.
Note 4: Output gate drivers will be enabled at this voltage. The GCL voltage
will also determine drivers’ activity.
Note 5: Gate drivers are ensured to be on when VIN is greater than the
maximum value.
TYPICAL PERFORMANCE CHARACTERISTICS
Negative Feedback Voltage and
Input Current vs Temperature
2.480
3.2
1.258
700
2.485
3.0
1.256
650
1.254
600
2.490
2.8
1.252
550
2.495
2.6
1.250
500
2.500
2.4
1.248
450
2.505
2.2
1.246
400
1.244
350
2.510
2.0
1.242
300
2.515
1.8
1.240
–50 –25
0
NEGATIVE FEEDBACK VOLTAGE (V)
750
2.520
–50 –25
250
25 50 75 100 125 150
TEMPERATURE (°C)
0
1.6
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G01
1683 G02
Error Amp Output Current vs
Feedback Pin Voltage from Nominal
Error Amp Transconductance
vs Temperature
2000
500
1.65
1900
400
1.60
1800
300
1700
200
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G03
CURRENT (µA)
1.70
TRANSCONDUCTANCE (µmho)
FEEDBACK VOLTAGE (V)
Feedback Overvoltage Shutdown
vs Temperature
NFB INPUT CURRENT (µA)
1.260
FB INPUT CURRENT (nA)
FEEDBACK VOLTAGE (V)
Feedback Voltage and Input
Current vs Temperature
1600
1500
1400
100
25°C
125°C
0
–100
–200
1300
1200
–300
1100
–400
1000
–50 –25
– 40°C
0
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G04
–500
–400 –300 –200 –100 0 100 200 300 400
FEEDBACK PIN VOLTAGE FROM NOMINAL (mV)
1683 G05
1683fd
4
LT1683
TYPICAL PERFORMANCE CHARACTERISTICS
VC Pin Threshold and Clamp
Voltage vs Temperature
1.50
240
220
1.0
200
0.8
0.6
0.4
FAULT
180
160
140
120
0.2
80
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25
22
23
20
VIN CURRENT (mA)
17
WITH NO EXTERNAL MOSFETs
VIN = 20 RCSL, RVSL = 17k
16
VIN = 12 RCSL, RVSL = 17k
14
0.6
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
GATE DRIVE A/B PIN VOLTAGE (V)
90
80
70
60
20
30
DUTY CYCLE (%)
40
50
1683 G12
0
20
40
60
80
CS PIN VOLTAGE (mV)
100
Gate Drive A/B Low Voltage
vs Temperature
10.7
6.5
0.50
10.6
6.4
0.45
GCL = 12V
10.5
6.3
10.4
6.2
10.3
6.1
VIN = 12V
NO LOAD
10.2
6.0
10.1
5.9
10.0
5.8
GCL = 6V
9.90
5.7
9.80
5.6
9.70
–50 –25
0
120
1683 G11
Gate Drive A/B High Voltage
vs Temperature
VC PIN = 0.9V
TA = 25°C
10
0.8
1683 G10
110
0
1.0
0.2
10
–50 –25
Slope Compensation
100
1.2
0.4
12
25 50 75 100 125 150
TEMPERATURE (°C)
TA = 25°C
1.4
VIN = 12 RCSL, RVSL = 5.7k
18
1683 G09
PERCENT OF MAX CS VOLTAGE
CS Pin to VC Pin Transfer Function
1.6
5.5
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G13
GATE DRIVE A/B PIN VOLTAGE (V)
SHDN PIN CURRENT (µA)
24
0
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G08
VIN Current vs Temperature
27
19
0
1683 G07
SHDN Pin Hysteresis Current vs
Temperature
21
OFF
1.25
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G06
15
–50 –25
1.35
VC PIN VOLTAGE (V)
0
ON
1.40
1.30
TRIP
100
0
–50 –25
1.45
SHDN PIN VOLTAGE (V)
1.2
CS PIN VOLTAGE (mV)
VC PIN VOLTAGE (V)
1.4
50
SHDN Pin On and Off Thresholds
vs Temperature
CS Pin Trip and CS Fault Voltage
vs Temperature
0.40
VIN = 12V
NO LOAD
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G14
1683fd
5
LT1683
TYPICAL PERFORMANCE CHARACTERISTICS
Gate Drive Undervoltage Lockout
Voltage vs Temperature
Soft-Start Current vs Temperature
7.3
GCL = 6V
9.3
7.0
6.9
6.8
6.7
6.6
5.06
8.9
8.7
8.5
8.3
8.1
6.5
7.9
6.4
7.7
6.3
–50 –25
SS VOLTAGE = 0.9V
9.1
SS PIN CURRENT (µA)
VIN PIN VOLTAGE (V)
7.1
5.08
0
25 50 75 100 125 150
TEMPERATURE (°C)
V5 PIN VOLTAGE (V)
7.2
V5 Voltage vs Load Current
9.5
7.5
–50 –25
T = 125°C
5.04
5.02
T = 25°C
5.00
T = –40°C
4.98
0
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G15
4.96
–15
–10
–5
0
5
LOAD CURRENT (mA)
1683 G16
10
15
1683 G17
PIN FUNCTIONS
Part Supply
V5 (Pin 5): This pin provides a 5V output that can sink or
source 10mA for use by external components. V5 source
current comes from VIN . Sink current goes to GND. VIN
must be greater than 6.5V in order for this voltage to be
in regulation. If this pin is used, a small capacitor ( VGCL + 0.8V. If this
pin is tied to VIN, then undervoltage lockout is disabled.
CT (Pin 7): The oscillator capacitor pin is used in conjunction with RT to set the oscillator frequency. For RT = 16.9k:
Slew Control
COSC(nf) = 129/fOSC(kHz)
RT (Pin 8): The oscillator resistor pin is used to set the
charge and discharge currents of the oscillator capacitor.
The nominal value is 16.9k. It is possible to adjust this resistance ±25% to set oscillator frequency more accurately.
Gate Drive
GATE A, GATE B (Pins 1, 19): These pins connect to the
gates of the external N-channel MOSFETs. GATE A and
GATE B turn on with alternate clock cycles. These drivers
are capable of sinking and sourcing at least 300mA.
The GCL pin sets the upper voltage of the gate drive. The
gate pins will not be activated until VIN reaches a minimum
voltage as defined by the GCL pin (gate undervoltage
lockout).
The gate drive outputs have current limit protection to
safe guard against accidental shorts.
If the gate drive voltage is greater than about 1V the
opposite gate drive is inhibited thus preventing cross
conduction.
GCL (Pin 3): This pin sets the maximum gate voltage to
the GATE A and GATE B pins to the MOSFET gate drives.
This pin should be either tied to a Zener, a voltage source
or VIN.
If the pin is tied to a Zener or a voltage source, the
maximum gate drive voltage will be approximately
VGCL – 0.2V. If it is tied to VIN, the maximum gate voltage
is approximately VIN – 1.6.
Approximately 50µA of current can be sourced from this
pin if VGCL < VIN – 0.8V.
This pin also controls undervoltage lockout of the gate
drives. If the pin is tied to a Zener or voltage source, the
There is an internal 19V Zener tied from this pin to ground
to provide a fail-safe for maximum gate voltage.
CAP A, CAP B (Pins 2, 18): These pins are the feedback
nodes for the external voltage slewing capacitors. Normally
a small 1pf to 5pf capacitor is connected from this pin to
the drain of its respective MOSFET.
The voltage slew rate is inversely proportional to this
capacitance and proportional to the current that the part
will sink and source on this pin. That current is inversely
proportional to RVSL.
RCSL (Pin 15): A resistor to ground sets the current slew
rate for the external drive MOSFETs during switching. The
minimum resistor value is 3.3k and the maximum value
is 68k. The time to slew between on and off states of
the MOSFET current will determine how the di/dt related
harmonics are reduced. This time is proportional to RCSL
and RS (the current sense resistor) and maximum current. Longer times produce a greater reduction of higher
frequency harmonics.
RVSL (Pin 16): A resistor to ground sets the voltage slew
rate for the drains of the external drive MOSFETs. The
minimum resistor value is 3.3k and the maximum value
is 68k. The time to slew between on and off states on the
MOSFET drain voltage will determine how harmonics are
reduced from this source. This time is proportional to RVSL,
CVA/B and the input voltage. Longer times produce more
rolloff of harmonics. CVA/B is the equivalent capacitance
from CAP A or B to the drain of the MOSFET.
Switch Mode Control
CS (Pin 4): This is the input to the current sense amplifier.
It is used for both current mode control and current slewing
of the external MOSFETs. Current sense is accomplished
via a sense resistor (RS) connected from the sources of
the external MOSFETs to ground. CS is connected to the
top of RS. Current sense is referenced to the GND pin.
1683fd
7
LT1683
PIN FUNCTIONS
The switch maximum operating current will be equal to
0.1V/RS. At CS = 0.1V, the gate drivers will be immediately
turned off (no slew control).
If CS = 0.22V in addition to the drivers being turned off, VC
and SS will be discharged to ground (short-circuit protection). This will hasten turn off on subsequent cycles.
FB (Pin 9): The feedback pin is used for positive voltage
sensing. It is the inverting input to the error amplifier. The
noninverting input of this amplifier connects internally to
a 1.25V reference.
If the voltage on this pin exceeds the reference by 220mV,
then the output drivers will immediately turn off the external MOSFETs (no slew control). This provides for output
overvoltage protection
When this input is below 0.9V then the current sense
blanking will be disabled. This will assist start up.
NFB (Pin 10): The negative feedback pin is used for sensing a negative output voltage. The pin is connected to the
inverting input of the negative feedback amplifier through
a 100k source resistor. The negative feedback amplifier
provides a gain of –0.5 to the FB pin. The nominal regulation point would be –2.5V on NFB. This pin should be left
open if not used.
VC (Pin 12): The compensation pin is used for frequency
compensation and current limiting. It is the output of the
error amplifier and the input of the current comparator.
Loop frequency compensation can be performed with an
RC network connected from the VC pin to ground. The
voltage on VC is proportional to the switch peak current.
The normal range of voltage on this pin is 0.25V to 1.27V.
However, during slope compensation the upper clamp
voltage is allowed to increase with the compensation.
During a short-circuit fault the VC pin will be discharged
to ground.
SS (Pin 13): The SS pin allows for ramping of the switch
current threshold at startup. Normally a capacitor is placed
on this pin to ground. An internal 9µA current source will
charge this capacitor up. The voltage on the VC pin cannot
exceed the voltage on SS. Thus peak current will ramp
up as the SS pin ramps up. During a short circuit fault
the SS pin will be discharged to ground thus reinitializing
soft-start.
When SS is below the VC clamp voltage the VC pin will
closely track the SS pin.
This pin can be left open if not used.
If NFB is being used then overvoltage protection will occur
at 0.44V below the NFB regulation point.
At NFB < –1.8 current sense blanking will be disabled.
TEST CIRCUITS
20mA
5pF
0.9A
5pF
IN5819
CAP A/CAP B
IN5819
CAP A/CAP B
ZVN3306A
GATE A/GATE B
+
–
2
10
GATE A/GATE B
Si4450DY
CS
+
–
10
0.1
1683 F01a
Figure 1a. Typical Test Circuitry
1683 F01b
Figure 1b. Test Circuit for Slew
1683fd
8
LT1683
BLOCK DIAGRAM
VIN
CIN
RCSL
SHDN
VIN
V5
RVSL
RCSL
RVSL
TO
DRIVERS
REGULATOR
+
NEGATIVE
FEEDBACK
AMP
VREG
–
NFB
100k
GCL
50k
CAP A
GATE A
–
FB
+
ERROR
AMP
SLEW
CONTROL
+
CAP B
1.25V
CVC
CSS
GATE B
VC
–
SS
CVB
MB
CS
+
COMP
S
CT
MA
PGND
SENSE
AMP
+
RT
CVA
RSENSE
–
Q
FF
RT
R
OSCILLATOR
CT
T
Q
FF
QB
SYNC
SUB
GND
1683 BD
1683fd
9
LT1683
OPERATION
In noise sensitive applications switching regulators tend
to be ruled out as a power supply option due to their propensity for generating unwanted noise. When switching
supplies are required due to efficiency or input/output
constraints, great pains must be taken to work around
the noise generated by a typical supply. These steps may
include pre and post regulator filtering, precise synchronization of the power supply oscillator to an external clock,
synchronizing the rest of the circuit to the power supply
oscillator or halting power supply switching during noise
sensitive operations. The LT1683 greatly simplifies the task
of eliminating supply noise by enabling the design of an
inherently low noise switching regulator power supply.
The LT1683 is a fixed frequency, current mode switching
regulator with unique circuitry to control the voltage and
current slew rates of the output switches. Current mode
control provides excellent AC and DC line regulation and
simplifies loop compensation.
Slew control capability provides much greater control over
the power supply components that can create conducted
and radiated electromagnetic interference. Compliance
with EMI standards will be an easier task and will require
fewer external filtering components.
The LT1683 uses two external N-channel MOSFETs as the
power switches. This allows the user to tailor the drive
conditions to a wide range of voltages and currents.
CURRENT MODE CONTROL
Referring to the Block Diagram. A switching cycle begins
with an oscillator discharge pulse, which resets the RS
flip-flop, turning on one of the external MOSFET drivers.
The switch current is sensed across the external sense
resistor and the resulting voltage is amplified and compared to the output of the error amplifier (VC pin). The
driver is turned off once the output of the current sense
amplifier exceeds the voltage on the VC pin. In this way
pulse by pulse current limit is achieved. The toggle flip-flop
ensures that the two MOSFETs are enabled on alternate
clock cycles. Internal slope compensation is provided to
ensure stability under high duty cycle conditions.
Output regulation is obtained using the error amp to
set the switch current trip point. The error amp is a
transconductance amplifier that integrates the difference
between the feedback output voltage and an internal 1.25V
reference. The output of the error amp adjusts the switch
current trip point to provide the required load current
at the desired regulated output voltage. This method of
controlling current rather than voltage provides faster
input transient response, cycle-by-cycle current limiting
for better output switch protection and greater ease in
compensating the feedback loop. The VC pin is used for
loop compensation and current limit adjustment. During
normal operation the VC voltage will be between 0.25V
and 1.27V. An external clamp on VC or SS may be used
for lowering the current limit.
The negative voltage feedback amplifier allows for direct
regulation of negative output voltages. The voltage on the
NFB pin gets amplified by a gain of – 0.5 and driven on to
the FB input, i.e., the NFB pin regulates to –2.5V while the
amplifier output internally drives the FB pin to 1.25V as in
normal operation. The negative feedback amplifier input
impedance is 100k (typ) referred to ground.
Soft-Start
Control of the switch current during start-up can be
obtained by using the SS pin. An external capacitor from
SS to ground is charged by an internal 9µA current source.
The voltage on VC cannot exceed the voltage on SS. Thus
as the SS pin ramps up the VC voltage will be allowed to
ramp up. This will then provide for a smooth increase in
switch maximum current. SS will be discharged as a result
of the CS voltage exceeding the short-circuit threshold of
approximately 0.22V.
Slew Control
Control of output voltage and current slew rates is achieved
via two feedback loops. One loop controls the MOSFET drain
dV/dt and the other loop controls the MOSFET dI/dt.
The voltage slew rate uses an external capacitor between
CAP A or CAP B and the respective MOSFET drain. These
integrating caps close the voltage feedback loop. The
external resistor, RVSL, sets the current for the integrator.
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LT1683
OPERATION
The voltage slew rate is thus inversely proportional to both
the value of capacitor and RVSL.
The current slew feedback loop consists of the voltage
across the external sense resistor, which is internally amplified and differentiated. The derivative is limited to a value set
by RCSL. The current slew rate is thus inversely proportional
to both the value of sense resistor and RCSL.
The two control loops are combined internally so that a
smooth transition from current slew control to voltage
slew control is obtained. When turning on, the driver current will slew before voltage. When turning off, voltage
will slew before current. In general it is desirable to have
RVSL and RCSL of similar value.
Internal Regulator
Most of the control circuitry operates from an internal
2.4V low dropout regulator that is powered from VIN. The
internal low dropout design allows VIN to vary from 2.7V
to 20V with stable operation of the controller. When SHDN
< 1.3V the internal regulator is completely disabled.
5V Regulator
A 5V regulator is provided for powering external circuitry.
This regulator draws current from VIN and requires VIN
to be greater than 6.5V to be in regulation. It can sink or
source 10mA. The output is current limited to prevent
against destruction from accidental short circuits.
Safety and Protection Features
There are several safety and protection features on the
chip. The first is overcurrent limit. Normally the gate
drivers will go low when the output of the internal sense
amplifier exceeds the voltage on the VC pin. The VC pin is
clamped such that maximum output current is attained
when the CS pin voltage is 0.1V. At that level the outputs
will be immediately turned off (no slew). The effect of
this control is that the output voltage will foldback with
overcurrent.
In addition, if the CS voltage exceeds 0.22V, the VC and
SS pins will be discharged to ground also, resetting the
soft-start function. Thus if a short is present this will allow
for faster MOSFET turnoff and less MOSFET stress.
If the voltage on the FB pin exceeds regulation by approximately 0.22V, the outputs will immediately go low.
The implication is that there is an overvoltage fault.
The voltage on GCL determines two features. The first
is the maximum gate drive voltage. This will protect the
MOSFET gate from overvoltage.
With GCL tied to a Zener or an external voltage source
then the maximum gate driver voltage is approximately
VGCL – 0.2V. If GCL is tied to VIN , then the maximum
gate voltage is determined by VIN and is approximately
VIN – 1.6V. There is an internal 19V Zener on the GCL
pin that prevents the gate driver pin from exceeding approximately 19V.
In addition, the GCL voltage determines undervoltage
lockout of the gate drives. This feature disables the gate
drivers if VIN is too low to provide adequate voltage to
turn on the MOSFETs. This is helpful during start-up to
ensure the MOSFETs have sufficient gate drive to saturate.
If GCL is tied to a voltage source or Zener less than 6.8V,
the gate drivers will not turn on until VIN exceeds GCL
voltage by 0.8V. For VGCL above 6.5V, the gate drives are
ensured to be off for VIN < 7.3V and they will be turned
on by VGCL + 0.8V.
If GCL is tied to VIN, the gate drivers are always enabled
(undervoltage lockout is disabled).
When driving a push-pull transformer, it is important to
make sure that both drivers are not on at the same time.
Even though runaway cannot occur under such cross
conduction with this chip because current slew is regulated, increased current would be possible. This chip has
opposite gate lockout whereby when one MOSFET is on
the other MOSFET cannot be turned on until the gate of
the first drops below 1V. This ensures that cross conduction will not occur.
The gate drives have current limits for the drive currents.
If the sink or source current is greater than 300mA then
the current will be limited.
The V5 regulator also has internal current limiting that will
only guarantee ±10mA output current.
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LT1683
OPERATION
There is also an on-chip thermal shutdown circuit that will
turn off the outputs in the event the chip temperature rises
to dangerous levels. Thermal shutdown has hysteresis that
will cause a low frequency ( VREG + 0.22V
(Output Overvoltage)
Immediately Goes Low
Overridden
None
GCL Clamp
Set Max Gate Voltage to Prevent
FET Gate Breakdown
Limits Max Voltage
None
None
Gate Drive
Undervoltage Lockout
Disable Gate Drives When VIN
Is Too Low. Set Via GCL Pin
Immediately Goes Low
Overridden
None
Thermal Shutdown
Turn Off Drivers If Chip
Temperature Is Too Hot
Immediately Goes Low
Overridden
None
Opposite Gate Lockout
Prevents Opposite Driver from
Turning on Until Driver Is Off
(Cross Conduction in Transformer)
Inhibits Turn On of
Opposite Driver
None
None
VIN Undervoltage Lockout
Disable Part When VIN ≅ 2.55V
Immediately Goes Low
Overridden
None
Gate Drive Source and Sink Current Limit Limit Gate Drive Current
Limit Drive Current
None
None
V5 Source/Sink Current Limit
Limit Current from V5
None
None
None
Shutdown
Disable Part When SHDN
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