LT3071
5A, Low Noise,
Programmable Output, 85mV
Dropout Linear Regulator
with Analog Margining
FEATURES
Output Current: 5A
Dropout Voltage: 85mV Typical
n Digitally Programmable V
OUT : 0.8V to 1.8V
n Analog Output Margining: ±10% Range
n Low Output Noise: 25µV
RMS (10Hz to 100kHz)
n Parallel Multiple Devices for 10A or More
n Precision Current Limit: ±20%
n Output Current Monitor: I
MON = IOUT/2500
n ±1% Accuracy Over Line, Load and Temperature
n Stable with Low ESR Ceramic Output Capacitors
(15µF Minimum)
n High Frequency PSRR: 30dB at 1MHz
n Enable Function Turns Output On/Off
n VIOC Pin Controls Buck Converter to Maintain Low
Power Dissipation and Optimize Efficiency
n PWRGD/UVLO/Thermal Shutdown Flag
n Current Limit with Foldback Protection
n Thermal Shutdown
n 28-Lead (4mm × 5mm × 0.75mm) QFN Package
n
n
APPLICATIONS
FPGA and DSP Supplies
ASIC and Microprocessor Supplies
n Servers and Storage Devices
n Post Buck Regulation and Supply Isolation
n
DESCRIPTION
The LT®3071 is a low voltage, UltraFast™ transient response linear regulator. The device supplies up to 5A of
output current with a typical dropout voltage of 85mV.
A 0.01µF reference bypass capacitor decreases output
voltage noise to 25µVRMS. The LT3071’s high bandwidth
permits the use of low ESR ceramic capacitors, saving
bulk capacitance and cost. The LT3071’s features make
it ideal for high performance FPGAs, microprocessors or
sensitive communication supply applications.
Output voltage is digitally selectable in 50mV increments
over a 0.8V to 1.8V range. An analog margining function
allows the user to adjust system output voltage over a
continuous ±10% range. The IC incorporates a unique
tracking function to control a buck regulator powering
the LT3071’s input. This tracking function drives the buck
regulator to maintain the LT3071’s input voltage to VOUT
+ 300mV, minimizing power dissipation.
Internal protection includes UVLO, reverse-current protection, precision current limiting with power foldback and
thermal shutdown. The LT3071 regulator is available in a
thermally enhanced 28-lead, 4mm × 5mm QFN package.
All registered trademarks and trademarks are the property of their respective owners. Patents
pending.
n
TYPICAL APPLICATION
Dropout Voltage
0.9V, 5A Regulator
VIN
1.2V
50k
PWRGD
2.2µF
BIAS
IN
330µF
PWRGD
EN
VO0
SENSE
LT3071
OUT
VO1
VO2
NC
1nF
MARGA
VIOC
2.2µF*
4.7µF*
*X5R OR X7R CAPACITORS
IMON
REF/BYP
GND
0.01µF
VOUT
0.9V
10µF* 5A
VMON
2V AT 5A
FULL SCALE
1k
3071 TA01a
DROPOUT VOLTAGE (mV)
VBIAS
2.2V TO 3.6V
150
VIN = VOUT(NOMINAL)
120
90
VOUT = 1.8V
VBIAS = 3.3V
60
VOUT = 0.8V
VBIAS = 2.5V
30
0
0
1
3
4
2
OUTPUT CURRENT (A)
5
3071 TA01b
Rev. D
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1
LT3071
VO0
VO1
VO2
GND
BIAS
TOP VIEW
EN
28 27 26 25 24 23
VIOC 1
22 MARGA
PWRGD 2
21 IMON
REF/BYP 3
20 GND
GND 4
19 SENSE
29
GND
IN 5
18 OUT
IN 6
17 OUT
IN 7
16 OUT
IN 8
15 OUT
GND
GND
GND
9 10 11 12 13 14
GND
IN, OUT...................................................... –0.3V to 3.3V
BIAS.............................................................. –0.3V to 4V
VO2, VO1, VO0 Inputs..................................... –0.3V to 4V
MARGA Input................................................ –0.3V to 4V
EN Input........................................................ –0.3V to 4V
SENSE Input.................................................. –0.3V to 4V
VIOC, PWRGD, IMON Outputs........................ –0.3V to 4V
REF/BYP Output............................................ –0.3V to 4V
Output Short-Circuit Duration........................... Indefinite
Operating Junction Temperature (Note 2)
LT3071E/LT3071I............................... –40°C to 125°C
LT3071MP.......................................... –55°C to 125°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
GND
(Note 1)
GND
ABSOLUTE MAXIMUM RATINGS
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 30°C/W TO 35°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3071EUFD#PBF
LT3071EUFD#TRPBF
3071
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3071IUFD#PBF
LT3071IUFD#TRPBF
3071
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3071MPUFD#PBF
LT3071MPUFD#TRPBF
3071
28-Lead (4mm × 5mm) Plastic QFN
–55°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3071EUFD
LT3071EUFD#TR
3071
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3071IUFD
LT3071IUFD#TR
3071
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3071MPUFD
LT3071MPUFD#TR
3071
28-Lead (4mm × 5mm) Plastic QFN
–55°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
IN Pin Voltage Range
VIN ≥ VOUT + 150mV, IOUT= 5A
BIAS Pin Voltage Range (Note 3)
Regulated Output Voltage
VOUT = 0.8V, 10mA ≤ IOUT ≤ 5A, 1.05V ≤ VIN ≤ 1.25V
VOUT = 0.9V, 10mA ≤ IOUT ≤ 5A, 1.15V ≤ VIN ≤ 1.35V
VOUT = 1V, 10mA ≤ IOUT ≤ 5A, 1.25V ≤ VIN ≤ 1.45V
VOUT = 1.1V, 10mA ≤ IOUT ≤ 5A, 1.35V ≤ VIN ≤ 1.55V
VOUT = 1.2V, 10mA ≤ IOUT ≤ 5A, 1.45V ≤ VIN ≤ 1.65V, VBIAS = 3.3V
VOUT = 1.5V, 10mA ≤ IOUT ≤ 5A, 1.75V ≤ VIN ≤ 1.95V, VBIAS = 3.3V
VOUT = 1.8V, 10mA ≤ IOUT ≤ 5A, 2.05V ≤ VIN ≤ 2.25V, VBIAS = 3.3V
TYP
MAX
UNITS
l
0.95
3.0
V
l
2.2
3.6
V
l
l
l
l
l
l
l
0.792
0.891
0.990
1.089
1.188
1.485
1.782
0.808
0.909
1.010
1.111
1.212
1.515
1.818
V
V
V
V
V
V
V
0.800
0.900
1.000
1.100
1.200
1.500
1.800
Rev. D
2
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LT3071
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
Regulated Output Voltage Margining
(Note 3)
MARGA = 1.2V
MARGA = 0V
l
l
MIN
TYP
MAX
UNITS
9.5
–10.5
10
–10
10.5
–9.5
%
%
Line Regulation to VIN
VOUT = 0.8V, ∆VIN = 1.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA
VOUT = 1.8V, ∆VIN = 2.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA
l
l
1.0
1.0
mV
mV
Line Regulation to VBIAS
VOUT = 0.8V, ∆VBIAS = 2.2V to 3.6V, VIN = 1.1V, IOUT = 10mA
VOUT = 1.8V, ∆VBIAS = 3.25V to 3.6V, VIN = 2.1V, IOUT = 10mA
l
l
2.0
1.0
mV
mV
Load Regulation,
∆IOUT = 10mA to 5A
VBIAS = 2.5V, VIN = 1.05V, VOUT = 0.8V
–1.5
–3.0
–5.5
mV
mV
–2
–4.0
–7.5
mV
mV
–2
–4.0
–7.5
mV
mV
–2.5
–5.0
–9.0
mV
mV
–3
–7.0
–13
mV
mV
20
35
mV
50
65
85
mV
mV
85
120
150
mV
mV
l
VBIAS = 2.5V, VIN = 1.25V, VOUT = 1.0V
l
VBIAS = 3.3V, VIN = 1.45V, VOUT = 1.2V
l
VBIAS = 3.3V, VIN = 1.75V, VOUT = 1.5V
l
VBIAS = 3.3V, VIN = 2.05V, VOUT = 1.8V
l
Dropout Voltage,
VIN = VOUT(NOMINAL) (Note 6)
IOUT = 1A, VOUT = 1V
l
IOUT = 2.5A, VOUT = 1V
l
IOUT = 5A, VOUT = 1V
l
SENSE Pin Current
VIN = 1.1V, VSENSE = 0.8V
VBIAS = 3.3V, VIN = 2.1V, VSENSE = 1.8V
l
l
35
200
50
300
65
400
µA
µA
Ground Pin Current,
VIN = 1.3V, VOUT = 1V
IOUT = 10mA
IOUT = 5A
l
l
0.65
0.9
1.1
1.35
1.8
2.3
mA
mA
BIAS Pin Current in Nap Mode
EN = Low
l
120
300
420
µA
BIAS Pin Current,
VIN = 1.3V, VOUT = 1V
IOUT = 10mA
IOUT = 100mA
IOUT = 500mA
IOUT = 1A
IOUT = 2.5A
IOUT = 5A
l
l
l
l
l
l
0.75
1.25
2.0
2.6
3.5
4.5
1.08
1.8
3.0
3.8
5.2
6.9
1.5
2.4
4.0
5.0
7.0
10.0
mA
mA
mA
mA
mA
mA
Current Limit (Note 5)
VIN – VOUT < 0.3V, VBIAS = 3.3V
VIN – VOUT = 1.0V, VBIAS = 3.3V
VIN – VOUT = 1.7V, VBIAS = 3.3V
l
l
l
5.1
3.2
1.2
6.4
4.5
2.5
7.7
5.8
4.3
A
A
A
IMON Full-Scale Output Current (Note 3) IOUT = 5A, VIN – VOUT = 0.3V, VOUT = 0.8V, 1.8V
l
1.6
2.0
2.4
mA
IMON/IOUT Scale (Note 3)
1A ≤ IOUT ≤ 5A, VIN – VOUT = 0.3V, VOUT = 0.8V, 1.8V
l
340
400
460
µA/A
Reverse Output Current (Note 8)
VIN = 0V, VOUT = 1.8V
l
300
450
µA
PWRGD VOUT Threshold
Percentage of VOUT(NOMINAL), VOUT Rising
Percentage of VOUT(NOMINAL), VOUT Falling
l
l
87
82
90
85
93
88
%
%
PWRGD VOL
IPWRGD = 200µA (Fault Condition)
l
50
150
mV
VBIAS Undervoltage Lockout
VBIAS Rising
VBIAS Falling
l
l
1.1
0.9
1.55
1.4
2.1
1.7
V
V
l
250
300
350
mV
160
170
235
255
310
340
µA
µA
0.25
V
VIN-VOUT Servo Voltage by VIOC
VIOC Output Current
VIN = VOUT(NOMINAL) + 150mV, Sourcing Out of the Pin
VIN = VOUT(NOMINAL) + 450mV, Sinking Into the Pin
l
l
VIL Input Threshold (Logic-0 State),
VO2, VO1, VO0
Input Falling
l
Rev. D
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3
LT3071
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
VIZ Input Range (Logic-Z State),
VO2, VO1, VO0
VIH Input Threshold (Logic-1 State),
VO2, VO1, VO0
Input Rising
l
0.75
l
VBIAS – 0.25
Input Hysteresis (Both Thresholds),
VO2, VO1, VO0
TYP
MAX
VBIAS – 0.9
UNITS
V
V
60
mV
Input Current High,
VO2, VO1, VO0
VIH = VBIAS = 2.5V, Current Flows Into Pin
l
25
40
µA
Input Current Low,
VO2, VO1, VO0
VIL = 0V, VBIAS = 2.5V, Current Flows Out of Pin
l
25
40
µA
EN Pin Threshold
VOUT = Off to On, VBIAS = 2.5V
VOUT = On to Off, VBIAS = 2.5V
VOUT = Off to On, VBIAS = 2.2V to 3.6V
VOUT = On to Off, VBIAS = 2.2V to 3.6V
l
l
0.9
l
l 0.36 • VBIAS
1.4
V
V
V
V
EN Pin Logic High Current
VEN = VBIAS = 2.5V
l
EN Pin Logic Low Current
VEN = 0V
l
VBIAS Ripple Rejection
VBIAS = VOUT + 1.5VAVG, VRIPPLE =0.5VP-P , fRIPPLE = 120Hz,
VIN – VOUT = 300mV, IOUT = 2.5A
75
dB
VIN Ripple Rejection
(Notes 3, 4, 5)
VBIAS = 2.5V, VRIPPLE = 50mVP-P , fRIPPLE = 120Hz,
VIN – VOUT = 300mV, IOUT = 2.5A
66
dB
Reference Voltage Noise
(REF/BYP Pin)
CREF/BYP = 10nF, BW = 10Hz to 100kHz
10
µVRMS
Output Voltage Noise
VOUT = 1V, IOUT = 5A, CREF/BYP = 10nF, COUT = 15µF,
BW = 10Hz to 100kHz
25
µVRMS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3071 regulators are tested and specified under pulse load
conditions such that TJ ≅ TA. The LT3071E is 100% tested at TA = 25°C.
Performance at –40°C and 125°C is assured by design, characterization
and correlation with statistical process controls. The LT3071I is
guaranteed over the –40°C to 125°C operating junction temperature range.
The LT3071MP is 100% tested and guaranteed over the –55°C to 125°C
operating junction temperature range.
Note 3: To maintain proper performance and regulation, the BIAS supply
voltage must be higher than the IN supply voltage. For a given VOUT , the
BIAS voltage must satisfy the following conditions: 2.2V ≤ VBIAS ≤ 3.6V
and VBIAS ≥ (1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the minimum BIAS
voltage is limited to 2.2V.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification does not apply
for all possible combinations of input voltage and output current. When
operating at maximum output current, limit the input voltage range to
VIN < VOUT + 500mV.
2.5
0.56 • VBIAS
4.0
6.5
µA
0.1
µA
Note 5: The LT3071 incorporates safe operating area protection circuitry.
Current limit decreases as the VIN-VOUT voltage increases. Current limit
foldback starts at VIN – VOUT > 500mV. See the Typical Performance
Characteristics for a graph of Current Limit vs VIN – VOUT voltage. The
current limit foldback feature is independent of the thermal shutdown
circuity.
Note 6: Dropout voltage, VDO, is the minimum input to output voltage
differential at a specified output current. In dropout, the output voltage
equals VIN – VDO.
Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 300mV and a
current source load. VIOC is a buffered output determined by the value of
VOUT as programmed by the VO2-VO0 pins. VIOC’s output is independent
of the margining function.
Note 8: Reverse output current is tested with the IN pins grounded and the
OUT + SENSE pins forced to the rated output voltage. This is measured as
current into the OUT + SENSE pins.
Note 9: Frequency Compensation: The LT3071 must be frequency
compensated at its OUT pins with a minimum COUT of 15µF configured
as a cluster of (15×) 1µF ceramic capacitors or as a graduated cluster
of 10µF/4.7µF/2.2µF ceramic capacitors of the same case size. Linear
Technology only recommends X5R or X7R dielectric capacitors.
Rev. D
4
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LT3071
TYPICAL PERFORMANCE CHARACTERISTICS
Dropout Voltage vs IOUT
Dropout Voltage vs Temperature
VIN = VOUT(NOMINAL)
TJ = 25°C
25
120
90
VOUT = 1.8V
VBIAS = 3.3V
60
VOUT = 0.8V
VBIAS = 2.5V
30
0
VIN = VOUT(NOMINAL)
IOUT = 1A
1
3
4
2
OUTPUT CURRENT (A)
90
20
15
10
VOUT = 1.8V, VBIAS = 3.3V
VOUT = 0.8V, VBIAS = 2.5V
VOUT = 1.2V, VBIAS = 3.3V
5
0
30
VOUT = 1.8V, VBIAS = 3.3V
VOUT = 0.8V, VBIAS = 2.5V
VOUT = 1.2V, VBIAS = 3.3V
30
20
0.806
160
140
120
100
80
60
40
0
OUT = 1.8V
OUT = 1.5V
OUT = 0.8V
2.2
2.4
2.6 2.8 3.0
3.2
BIAS VOLTAGE (V)
3.4
1.212
ILOAD = 10mA
0.802
0.800
0.798
0.796
0.794
0.792
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3.6
3071 G06
Output Voltage (1.5V)
vs Temperature
1.515
ILOAD = 10mA
OUTPUT VOLTAGE (V)
1.000
0.998
0.996
0.994
ILOAD = 10mA
1.510
OUTPUT VOLTAGE (V)
1.208
1.006
1.002
ILOAD = 10mA
0.804
Output Voltage (1.2V)
vs Temperature
1.004
VOUT = 1.8V, VBIAS = 3.3V
VOUT = 0.8V, VBIAS = 2.5V
VOUT = 1.2V, VBIAS = 3.3V
3071 G05
Output Voltage (1V)
vs Temperature
OUTPUT VOLTAGE (V)
40
0.808
3071 G04
1.008
50
Output Voltage (0.8V)
vs Temperature
Dropout Voltage vs VBIAS
20
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1.010
60
3071 G03
OUTPUT VOLTAGE (V)
60
70
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
IOUT = 5A
180 TJ = 25°C
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
200
VIN = VOUT(NOMINAL)
IOUT = 5A
90
80
3071 G02
Dropout Voltage vs Temperature
120
VIN = VOUT(NOMINAL)
IOUT = 2.5A
10
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
5
3071 G01
150
Dropout Voltage vs Temperature
100
DROPOUT VOLTAGE (mV)
30
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
150
1.204
1.200
1.196
1.505
1.500
1.495
1.192
1.490
1.188
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1.485
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0.992
0.990
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G07
3071 G08
3071 G09
Rev. D
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5
LT3071
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage (1.8V)
vs Temperature
3.0
ILOAD = 10mA
1.814
GND PIN CURRENT (mA)
1.802
1.798
1.794
1.790
2.0
1.5
1.0
VOUT = 1.8V, VBIAS = 3.3V
VOUT = 1.2V, VBIAS = 3.3V
VOUT = 0.8V, VBIAS = 2.5V
0.5
1.786
0
1.782
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0
1
3071 G10
10
VBIAS = 2.5V
350 VEN = 0V
BIAS Pin Undervoltage Lockout
Threshold
300
250
200
150
100
50
2.5
VIN = VOUT + 300mV
TJ = 25°C
9
BIAS PIN CURRENT (mA)
BIAS PIN CURRENT (µA)
3071 G12
BIAS Pin Current vs IOUT
400
8
7
VOUT = 1.8V
VBIAS = 3.3V
6
5
4
VOUT = 0.8V
VBIAS = 2.5V
3
2
2.0
VBIAS RISING
1.5
1.0
VBIAS FALLING
0.5
1
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0
0
1
3
4
2
OUTPUT CURRENT (A)
1.00
PWRGD TRESHOLD VOLTAGE (V)
VBIAS = 3.3V
VOUT = 0.8V TO 1.8V
V – VOUT = 300mV
2.0 T IN= –55°C
TO 125°C
J
1.5
1.0
0.5
1
2
3
4
OUTPUT CURRENT (A)
3071 G15
PWRGD Threshold Voltage
IMON vs IOUT
2.5
0
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
5
3071 G14
3071 G13
IMON (mA)
598
3071 G11
BIAS Pin Current in Nap Mode
0
600
594
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
5
2
3
4
OUTPUT CURRENT (A)
602
596
5
6
PWRGD VOL vs Temperature
100
VBIAS = 2.5V
VOUT = 1V
PWRGD VOL VOLTAGE (mV)
OUTPUT VOLTAGE (V)
1.806
CREF/BYP = 0.01µF
604
REF/BYP VOLTAGE (mV)
2.5
1.810
606
VIN = VOUT + 300mV
TJ = 25°C
UVLO THRESHOLD VOLTAGE (V)
1.818
REF/BYP Pin Voltage
vs Temperature
GND Pin Current vs IOUT
0.95
VOUT RISING
0.90
0.85
VOUT FALLING
0.80
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G17
3071 G16
VBIAS = 2.5V
IPWRGD = 200µA
80
60
40
20
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G18
Rev. D
6
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LT3071
TYPICAL PERFORMANCE CHARACTERISTICS
4.0
VBIAS = 2.5V
1.4
1.2
1.0
0.8
EN PIN RISING
EN PIN FALLING
0.6
0.4
0.2
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
Logic Input Threshold Voltages
Logic Hi-Z to High State Transitions
2.8
INPUT RISING
LOGIC Hi-Z TO HIGH
2.7
INPUT FALLING
LOGIC HIGH TO Hi-Z
2.6
6.0
3
3.5
BIAS VOLTAGE (V)
0.6
0.5
5.5
0.4
3071 G21
Logic Pin Input Current,
High State
40
VEN = VBIAS = 2.5V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
35
30
25
20
15
10
5
SENSE Pin Current
SENSE Pin Current
SENSE PIN CURRENT (µA)
VBIAS = 2.5V
35 VLOGIC = 0V
CURRENT FLOWS OUT OF THE PIN
30
25
20
15
10
VLOGIC = VBIAS = 2.5V
CURRENT FLOWS INTO THE PIN
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G24
65
40
INPUT FALLING
LOGIC Hi-Z TO LOW
TYP DISABLE
MIN DISABLE
5.0
Logic Pin Input Current,
Low State
INPUT RISING
LOGIC LOW TO Hi-Z
0.3
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
4
3071 G20
1.0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G23
2.5
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G22
LOGIC PIN INPUT CURRENT (µA)
2.5
SEE APPLICATIONS INFORMATION
FOR MORE DETAILS
0.7
EN Pin Logic High Current
EN PIN LOGIC HIGH CURRENT (µA)
LOGIC INPUT THRESHOLD VOLTAGE (V)
2.9
VBIAS = 3.3V
LOGIC Hi-Z TO HIGH THRESHOLD IS
RELATIVE TO VBIAS VOLTAGE
SEE APPLICATIONS INFORMATION
FOR MORE DETAILS
2
VBIAS
MAX ENABLE
TYP ENABLE
3071 G19
3.0
TYPICAL
HYSTERESIS
= 150mV
LOGIC PIN INPUT CURRENT (µA)
1.6
0.8
TJ = –55˚C TO 125°C
400
VBIAS = 2.5V
60 VOUT = 0.8V
CURRENT FLOWS INTO SENSE
55
SENSE PIN CURRENT (µA)
ENABLE PIN THRESHOLD (V)
1.8
ENABLE/DISABLE THRESHOLD (V)
2.0
Logic Input Threshold Voltages
Logic Low to Hi-Z State Transitions
EN Pin Threshold and Hysteresis
vs VBIAS
LOGIC INPUT THRESHOLD VOLTAGE (V)
EN Pin Thresholds
50
45
40
35
VBIAS = 3.3V
375 VOUT = 1.8V
CURRENT FLOWS INTO SENSE
350
325
300
275
250
5
30
225
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
25
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
200
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G26
3071 G25
3071 G27
Rev. D
For more information www.analog.com
7
LT3071
TYPICAL PERFORMANCE CHARACTERISTICS
Current Limit vs Temperature
Current Limit vs VIN – VOUT
8
7.00
6.75
CURRENT LIMIT (A)
CURRENT LIMIT (A)
VBIAS = 3.3V
TJ = 25°C
7
6.50
6.25
6.00
5.75
5.50
5.25
6
5
4
3
2
VOUT = 1.8V, VBIAS = 3.3V
VOUT = 1.2V, VBIAS = 3.3V
VOUT = 0.8V, VBIAS = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
1
5.00
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0
0
70
70
50
40
0
COUT = 117µF
COUT = 16.9µF
VOUT = 1V
VIN = 1.3V + 50mVP-P RIPPLE
VBIAS = 2.5V
IOUT = 1A
10
100
1k
10k 100k
FREQUENCY (Hz)
110
100
90
1M
100
60
90
80
50
40
COUT = 117µF
COUT = 16.9µF
30
20
0
10M
60
10
120
110
100
90
40
30
70
100
1k
10k 100k
FREQUENCY (Hz)
IN Pin Ripple Rejection
vs VIN – VOUT, 1V/5A
50mVP-P RIPPLE ON VIN
COUT = 16.9μF
VBIAS = 2.5V
TA = 25°C
RIPPLE AT f = 10kHz
50
1M
0
10M
RIPPLE AT f = 100kHz
RIPPLE AT f = 1MHz
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)
3071 G33
IN Pin Ripple Rejection
vs VIN – VOUT, 1V/1A
120
50mVP-P RIPPLE ON VIN
COUT = 16.9μF
VBIAS = 2.5V
RIPPLE AT f = 10kHz
TA = 25°C
110
100
90
80
RIPPLE AT f = 100kHz
50
70
60
50
40
IN Pin Ripple Rejection
vs VIN – VOUT, 1V/5A
50mVP-P RIPPLE ON VIN
COUT = 117μF
VBIAS = 2.5V
TA = 25°C
RIPPLE AT f = 10kHz
RIPPLE AT f = 1MHz
RIPPLE AT f = 100kHz
30
RIPPLE AT f = 1MHz
20
20
20
10
10
10
0
0
3071 G34
10M
10
60
30
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)
1M
60
20
40
RIPPLE AT f = 1MHz
1k
10k 100k
FREQUENCY (Hz)
30
80
RIPPLE AT f = 100kHz
100
3071 G32
50mVP-P RIPPLE ON VIN
COUT = 16.9μF
VBIAS = 2.5V
TA = 25°C
RIPPLE AT f = 10kHz
50
10
70
40
VOUT = 1V
VIN = 1.3V + 50mVP-P RIPPLE
VBIAS = 2.5V
IOUT = 5A
IN Pin Ripple Rejection
vs VIN – VOUT, 1V/2.5A
70
VBIAS = 2.5V + 500mVP-P
VBIAS = 2.7V + 500mVP-P
VBIAS = 3.3V + 500mVP-P
10
110
10
PSRR (dB)
PSRR (dB)
80
30
20
120
3071 G31
120
50
40
3071 G30
PSRR (dB)
IN PIN RIPPLE REJECTION (dB)
IN PIN RIPPLE REJECTION (dB)
80
10
60
IN Pin Ripple Rejection
80
20
70
3071 G29
IN Pin Ripple Rejection
30
80
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
IN-TO-OUT VOLTAGE DIFFERENTIAL (V)
3071 G28
60
VIN = 1.3V
VOUT = 1V
IOUT = 5A
COUT = 10µF + 4.7µF + 2.2µF
90
BIAS PIN RIPPLE REJECTION (dB)
VIN = VOUT(NOMINAL) + 300mV
7.25
BIAS Pin Ripple Rejection
100
PSRR (dB)
7.50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)
3071 G35
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)
3071 G36
Rev. D
8
For more information www.analog.com
LT3071
TYPICAL PERFORMANCE CHARACTERISTICS
120
100
90
80
110
100
90
70
60
50
RIPPLE AT f = 1MHz
40
RIPPLE AT f = 100kHz
60
RIPPLE AT f = 1MHz
50
40
30
20
20
10
10
0
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)
3071 G37
3.8
RIPPLE AT f = 10kHz
70
30
4.0
50mVP-P RIPPLE ON VIN
COUT = 117μF
VBIAS = 2.5V
TA = 25°C
80
RIPPLE AT f = 10kHz
PSRR (dB)
PSRR (dB)
120
50mVP-P RIPPLE ON VIN
COUT = 117μF
VBIAS = 2.5V
TA = 25°C
110
Minimum BIAS Voltage
vs Temperature
IN Pin Ripple Rejection
vs VIN – VOUT, 1V/1A
MINIMUM BIAS VOLTAGE (V)
IN Pin Ripple Rejection
vs VIN – VOUT, 1V/2.5A
RIPPLE AT f = 100kHz
IOUT = 5A
3.6
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)
3071 G38
3071 G39
Minimum BIAS Voltage vs IOUT
VIN = VOUT(NOMINAL) + 300mV
∆VOUT = –1%, TJ = 25°C
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 0.8V TO 1V
3.2
3.0
3.2
MINIMUM BIAS VOLTAGE (V)
3.4
MINIMUM BIAS VOLTAGE (V)
Minimum BIAS Voltage vs VOUT
3.4
2.8
2.6
2.4
IOUT = 5A
TJ = 25°C
3.0
2.8
2.6
2.4
2.2
0
1
2
4
3
OUTPUT CURRENT (A)
1.8
0.7
5
0.9
1.5
1.1
1.3
OUTPUT VOLTAGE (V)
1.7
–4
–6
–8
Bias Voltage Line Regulation
3071 G41
Bias Voltage Line Regulation
Input Voltage Line Regulation
400
400
300
200
100
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G43
300
VBIAS = 3.25V TO 3.6V
300 VIN = 2.1V
VOUT = 1.8V
200 IOUT = 10mA
INPUT VOLTAGE LINE REGULATION (µV)
BIAS VOLTAGE LINE REGULATION (µV)
500
VOUT = 0.8V
VOUT = 1.2V
VOUT = 1.8V
3071 G42
800
VBIAS = 2.2V TO 3.6V
700 VIN = 1.1V
VOUT = 0.8V
600 IOUT = 10mA
VIN = VOUT(NOMINAL) + 300mV
VBIAS = 3.3V
∆IOUT = 100mA TO 5A
–10
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1.9
3071 G40
BIAS VOLTAGE LINE REGULATION (µV)
–2
2.0
2.2
2.0
Load Regulation
0
LOAD REGULATION (mV)
3.6
100
0
–100
–200
–300
–400
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G44
250
VBIAS = 3.3V
VIN = 1.05V TO 2.7V
VOUT = 0.8V
IOUT = 10mA
200
150
100
50
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G45
Rev. D
For more information www.analog.com
9
LT3071
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage Start-Up Time
vs CREF/BYP
20
VBIAS = 3.3V
VIN = 2.05V TO 2.7V
VOUT = 1.8V
IOUT = 10mA
250
OUTPUT VOLTAGE START-UP TIME (ms)
INPUT VOLTAGE LINE REGULATION (µV)
300
200
150
100
50
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
VBIAS = 2.5V TO 3.3V
IOUT = 10mA
COUT = 10µF + 4.7µF + 2.2µF
TJ = 25°C
SEE APPLICATIONS
INFORMATION FOR
START-UP DETAILS
18
16
14
12
10
8
6
4
2
0
0.1
0.3
0.4
0.2
REF/BYP CAPACITANCE (µF)
0
80
70
OUTPUT NOISE (µVRMS)
NOISE SPECTRAL DENSITY (µV/√Hz)
VBIAS = 2.5V
VOUT = 1V
IOUT = 5A
COUT = 16.9µF
CREF/BYP = 0.01µF
0.01
0.001
100
1k
10k
FREQUENCY (Hz)
250
200
150
100
50
0
0.5
100k
VOUT
100µV/DIV
40
30
20
0
0.01
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.8V
0.1
1
OUTPUT CURRENT (A)
VOUT = 1V
IOUT = 5A
COUT = 16.9µF
10
3071 G51
VIOC Amplifier IN-to-OUT
Servo Voltage
VBIAS
200mV/DIV
VIN = 1.3V
VBIAS = 2.5V
VOUT = 1V
IOUT = 5A
COUT = 16.9µF
20µs/DIV
3071 G53
VIOC IN-TO-OUT SERVO VOLTAGE (mV)
VOUT
10mV/DIV
3071 G52
1ms/DIV
3071 G50
350
20µs/DIV
5
3071 G48
Bias Voltage Line Transient
Response
VIN
50mV/DIV
2
4
3
OUTPUT CURRENT (A)
Output Noise (10Hz to 100kHz)
50
Input Voltage Line Transient
Response
VOUT
1mV/DIV
1
60
3071 G49
VIN = 1.3V
VOUT = 1V
IOUT = 5A
COUT = 16.9µF
0
VIN = VOUT(NOMINAL) + 300mV
VBIAS = 3.3V
COUT = 16.9µF
10
10
300
RMS Output Noise
vs Output Current
Output Noise Spectral Density
0.1
VBIAS = 3.3V
VIN = VOUT(NOM) + 300mV
EN = LOW TO HIGH
IOUT = 5A (SET BY A RESISTOR LOAD)
TJ = 25°C
VOUT = 1.8V,
COUT = 117µF
VOUT = 1.2V,
COUT = 117µF
VOUT = 0.8V,
COUT = 117µF
350
3071 G47
3071 G46
1.0
Nap Mode Recovery Time vs IOUT
400
NAP MODE RECOVERY TIME (µs)
Input Voltage Line Regulation
340
VBIAS = 2.5V
330
320
310
300
290
280
270
260
250
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G54
Rev. D
10
For more information www.analog.com
LT3071
TYPICAL PERFORMANCE CHARACTERISTICS
VIOC Amplifier Output Current
vs Temperature
Transient Load Response
Transient Load Response
VIOC AMPLIFIER OUTPUT CURRENT (µA)
300
275
IVIOC SOURCING
250
VOUT
50mV/DIV
AC-COUPLED
VOUT
50mV/DIV
AC-COUPLED
IOUT
2A/DIV
∆I = 500mA
TO 5A
IOUT
2A/DIV
∆I = 500mA
TO 5A
IVIOC SINKING
225
200
175
150
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3071 G56
VOUT = 1V
20µs/DIV
COUT = 10µF + 4.7µF + 2.2µF
IOUT tRISE/tFALL = 100ns
VOUT = 1V
20µs/DIV
COUT = 117µF
IOUT tRISE/tFALL = 100ns
3071 G57
3071 G55
Transient Load Response
Transient Load Response
VOUT
50mV/DIV
AC-COUPLED
VOUT
50mV/DIV
AC-COUPLED
IOUT
2A/DIV
∆I = 500mA
TO 5A
IOUT
2A/DIV
∆I = 500mA
TO 5A
VOUT = 1V
20µs/DIV
COUT = 10µF + 4.7µF + 2.2µF
IOUT tRISE/tFALL = 1µs
3071 G58
VOUT = 1V
20µs/DIV
COUT = 117µF
IOUT tRISE/tFALL = 1µs
3071 G59
Rev. D
For more information www.analog.com
11
LT3071
PIN FUNCTIONS
VIOC (Pin 1): Voltage for In-to-Out Control. The IC incorporates a unique tracking function to control a buck regulator
powering the LT3071’s input. The VIOC pin is the output
of this tracking function that drives the buck regulator to
maintain the LT3071’s input voltage at VOUT + 300mV.
This function maximizes efficiency and minimizes power
dissipation. See the Applications Information section for
more information on proper control of the buck regulator.
PWRGD (Pin 2): Power Good. The PWRGD pin is an opendrain NMOS output that actively pulls low if any one of
these fault modes is detected:
• VOUT is less than 90% of VOUT(NOMINAL) on the rising
edge of VOUT .
• VOUT drops below 85% of VOUT(NOMINAL) for more than
25µs.
• Junction temperature typically exceeds 145°C.
• VBIAS is less than its undervoltage lockout threshold.
• The OUT-to-IN reverse-current detector activates.
See the Applications Information section for more information on PWRGD fault modes.
REF/BYP (Pin 3): Reference Filter. The pin is the output
of the bandgap reference and has an impedance of approximately 19kΩ. This pin must not be externally loaded.
Bypassing the REF/BYP pin to GND with a 10nF capacitor
decreases output voltage noise and provides a soft-start
function to the reference. LTC recommends the use of a
high quality, low leakage capacitor. See the Applications
Information section for more information on noise and
output voltage margining considerations.
GND (Pins 4, 9-14, 20, 26, Exposed Pad Pin 29): Ground.
The exposed pad of the QFN package is an electrical connection to GND. To ensure proper electrical and thermal
performance, solder Pin 29 to the PCB ground and tie to
all GND pins of the package. These GND pins are fused
to the internal die attach paddle and the exposed pad to
optimize heat sinking and thermal resistance characteristics. See the Applications Information section for thermal
considerations and calculating junction temperature.
IN (Pins 5, 6, 7, 8): Input Supply. These pins supply
power to the high current pass transistor. Tie all IN pins
together for proper performance. The LT3071 requires a
bypass capacitor at IN to maintain stability and low input
impedance over frequency. A 47µF input bypass capacitor
suffices for most battery and power plane impedances.
Minimizing input trace inductance optimizes performance.
Applications that operate with low VIN-VOUT differential
voltages and that have large, fast load transients may require
much higher input capacitor requirements to prevent the
input supply from drooping and allowing the regulator to
enter dropout. See the Applications Information section
for more information on input capacitor requirements.
OUT (Pins 15, 16, 17, 18): Output. These pins supply
power to the load. Tie all OUT pins together for proper
performance. A minimum output capacitance of 15µF is
required for stability. LTC recommends low ESR, X5R or
X7R dielectric ceramic capacitors for best performance.
A parallel ceramic capacitor combination of 10µF + 4.7µF
+ 2.2µF or 15 1µF ceramic capacitors in parallel provide
excellent stability and load transient response. Large load
transient applications require larger output capacitors to
limit peak voltage transients. See the Applications Information section for more information on output capacitor
requirements.
SENSE (Pin 19): Kelvin Sense for OUT . The SENSE pin is
the inverting input to the error amplifier. Optimum regulation is obtained when the SENSE pin is connected to
the OUT pins of the regulator. In critical applications, the
resistance (RP) of PCB traces between the regulator and the
load cause small voltage drops, creating a load regulation
error at the point of load. Connecting the SENSE pin at
the load instead of directly to OUT eliminates this voltage
error. Figure 1 illustrates this Kelvin-Sense connection
method. Note that the voltage drop across the external
PCB traces adds to the dropout voltage of the regulator.
The SENSE pin input bias current depends on the selected
output voltage. SENSE pin input current varies from 50µA
typically at VOUT = 0.8V to 300µA typically at VOUT = 1.8V.
Rev. D
12
For more information www.analog.com
LT3071
PIN FUNCTIONS
IMON (Pin 21): Output Current Monitor. The IMON pin
sources a current typically equal to IOUT/2500 or 400µA
per amp of output current. Terminating this pin with a
resistor to GND produces a voltage proportional to IOUT .
For example, at IOUT = 5A, IMON typically sources 2mA.
With a 1k resistor to GND, this produces 2V. If IMON is
unused, tie this pin to VBIAS.
Applications Information section that defines the VO2, VO1
and VO0 settings versus VOUT .
BIAS (Pin 27): Bias Supply. This pin supplies current to
the internal control circuitry and the output stage driving
the pass transistor. The LT3071 requires a minimum 2.2µF
bypass capacitor for stability and proper operation. To
ensure proper operation, the BIAS voltage must satisfy
the following conditions: 2.2V ≤ VBIAS ≤ 3.6V and VBIAS ≥
(1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the minimum BIAS
voltage is limited to 2.2V.
MARGA (Pin 22): Analog Margining. This pin margins the
output voltage over a continuous analog range of ±10%.
Tying this pin to GND adjusts output voltage by –10%.
Driving this pin to 1.2V adjusts output voltage by +10%. A
voltage source or a voltage output DAC is ideal for driving
this pin. If the MARGA function is not used, either float
this pin or terminate with a 1nF capacitor to GND.
EN (Pin 28): Enable. This pin enables/disables the output
device only. The internal reference and all support functions
are active if VBIAS is above its UVLO threshold. Pulling EN
low keeps the reference circuit active, but disables the
output pass transistor and puts the LT3071 into a low
power nap mode. The maximum rising EN threshold is
ratioed to 0.56% of VBIAS and the minimum falling ENx
threshold is 0.36% of VBIAS. Drive the EN pin with either
a digital logic port or an open-collector NPN or an opendrain NMOS terminated with a pull-up resistor to VBIAS.
The pull-up resistor must be less than 35k to meet the VIH
condition of the EN pin. If unused, connect EN to BIAS.
VO0, VO1 and VO2 (Pins 23, 24, 25): Output Voltage Select. These three-state pins combine to select a nominal
output voltage from 0.8V to 1.8V in increments of 50mV.
Output voltage is limited to 1.8V maximum by an internal
override of VO1 when VO2 = high. The input logic low
threshold is less than 250mV referenced to GND and the
logic high threshold is greater than VBIAS – 250mV. The
range between these two thresholds as set by a window
comparator defines the logic Hi-Z state. See Table 1 in the
+
VBIAS
BIAS
EN
IN
VO0
+
PWRGD
SENSE
LT3071
OUT
VO1
VIN
RP
VO2
MARGA
VIOC
IMON
LOAD
REF/BYP
GND
RP
3071 F01
Figure 1. Kelvin Sense Connection
Rev. D
For more information www.analog.com
13
LT3071
BLOCK DIAGRAM
27
BIAS
IN
5-8
UVLO AND
THERMAL
SHUTDOWN
+
+
IMON
ISENSE
REF/BYP
–
+
21
–
EAMP
BUF
–
OUT
15-18
LDO CORE
SENSE
PWRGD
DETECT
+
–
1
VIOC
19
2
VOUT(NOM) + 300mV
REF/BYP
VREF
GND
4,9-14,20,26,29
600mV
3
PROGRAM CONTROL
EN
28
VO2
25
VO1
24
VO0
MARGA
23
22
LOGIC HIGH STATE
28
VBIAS – 0.25V
EN
500k
TO INTERNAL ENABLE
(SEE ENABLE
THRESHOLD CURVE)
–
+
LOGIC HIGH STATE
VBIAS
100k
VBIAS – 0.9V
100k
0.75V
VO2, VO1, VO0
+
–
+
–
HIGH IF IN > VBIAS – 0.25V
HIGH IF IN < VBIAS – 0.9V
AND IN > 0.75V
TO LOGIC
HIGH IF IN < 0.25V
LOGIC LOW STATE
–
0.25V
+
3070 BD
Rev. D
14
For more information www.analog.com
LT3071
APPLICATIONS INFORMATION
Introduction
Current generation FPGA and ASIC processors place
stringent demands on the power supplies that power the
core, I/O and transceiver channels. These microprocessors
may cycle load current from near zero to amps in tens of
nanoseconds. Output voltage specifications, especially in
the 1V range, require tight tolerances including transient
response as part of the requirement. Some ASIC processors
require only a single output voltage from which the core
and I/O circuitry operate. Some high performance FPGA
processors require separate power supply voltages for the
processor core, the I/O, and the transceivers. Often, these
supply voltages must be low noise and high bandwidth
to achieve the lowest bit-error rates. These requirements
mandate the need for very accurate, low noise, high current, very high speed regulator circuits that operate at low
input and output voltages.
The LT3071 is a low voltage, UltraFast transient response
linear regulator. The device supplies up to 5A of output
current with a typical dropout voltage of 85mV. A 0.01µF
reference bypass capacitor decreases output voltage noise
to 25µVRMS (BW = 10Hz to 100kHz). The LT3071’s high
bandwidth provides UltraFast transient response using low
ESR ceramic output capacitors (15µF minimum), saving
bulk capacitance, PCB area and cost.
The LT3071’s features permit state-of-the-art linear regulator performance. The LT3071 is ideal for high performance
FPGAs, microprocessors, sensitive communication supplies, and high current logic applications that also operate
over low input and output voltages.
Output voltage for the LT3071 is digitally selectable in
50mV increments over a 0.8V to 1.8V range. An analog
margining function allows the user to adjust system output
voltage over a continuous ±10% range.
The LT3071 provides an output current monitor that
typically sources a current of IOUT/2500 or 400µA per
amp of IOUT at its IMON pin. Terminating the IMON pin to
GND with a resistor produces a voltage proportional to
output current. This permits a user to measure system
performance such as output power or if output current
exceeds or falls below some threshold.
The IC incorporates a unique tracking function, which if
enabled by the user, controls an upsteam regulator powering the LT3071’s input (see Figure 8). This tracking function
drives the buck regulator to maintain the LT3071’s input
voltage to VOUT + 300mV. This input-to-output voltage
control allows the user to change the regulator output
voltage, and have the switching regulator powering the
LT3071’s input to track to the optimum input voltage with
no component changes.
This combines the efficiency of a switching regulator
with superior linear regulator response. It also permits
thermal management of the system even with a maximum
5A output load.
LT3071 internal protection includes input undervoltage
lockout (UVLO), reverse-current protection, precision current limiting with power foldback and thermal shutdown.
The LT3071 regulator is available in a thermally enhanced
28-lead, 4mm × 5mm QFN package.
The LT3071’s architecture drives an internal N-channel
power MOSFET as a source follower. This configuration
permits a user to obtain an extremely low dropout, UltraFast transient response regulator with excellent high frequency PSRR performance. The LT3071 achieves superior
regulator bandwidth and transient load performance by
eliminating expensive bulk tantalum or electrolytic capacitors in the most modern and demanding microprocessor
applications. Users realize significant cost savings as all
additional bulk capacitance is removed. The additional
savings of insertion cost, purchasing/inventory cost and
board space are readily apparent. Precision incremental
output voltage control accommodates legacy and future
microprocessor power supply voltages.
Output capacitor networks simplify to direct parallel combinations of ceramic capacitors. Often, the high frequency
ceramic decoupling capacitors required by these various
Rev. D
For more information www.analog.com
15
LT3071
APPLICATIONS INFORMATION
FPGA and ASIC processors are sufficient to stabilize the
system (see Stability and Output Capacitance section). This
regulator design provides ample bandwidth and responds
to transient load changes in a few hundred nanoseconds
versus regulators that respond in many microseconds.
The LT3071 also incorporates precision current limiting, enable/disable control of output voltage and integrated overvoltage and thermal shutdown protection.
The LT3071’s unique design combines the benefits of
low dropout voltage, high functional integration, precision
performance and UltraFast transient response, as well as
providing significant cost savings on the output capacitance
needed in fast load transient applications.
As lower voltage applications become increasingly prevalent with higher frequency switching power supplies, the
LT3071 offers superior regulation and an appreciable
component cost savings. The LT3071 steps to the next
level of performance for the latest generation FPGAs, DSPs
and microprocessors. The simple versatility and benefits
derived from these circuits exceed the power supply needs
of today’s high performance microprocessors.
Programming Output Voltage
Three tri-level input pins, VO2, VO1 and VO0, select the
value of output voltage. Table 1 illustrates the 3-bit digital
word to output voltage resulting from setting these pins
high, low or allowing them to float.
These pins may be tied high or low by either pin-strapping
them to VBIAS or driving them with digital ports. Pins that
float may either actually float or require logic that has
Hi-Z output capability. This allows output voltage to be
dynamically changed if necessary.
Output voltage is selectable from a minimum of 0.8V to
a maximum of 1.8V in increments of 50mV. The MSB,
VO2, sets the pedestal voltage, and the LSB’s, VO1 and
VO0 increment VOUT .
Output voltage is limited to 1.8V maximum by an internal
override of VO1 (default to low) when VO2 = high.
Table 1: VO2 to VO0 Settings vs Output Voltage
VO2
VO1
VO0
VOUT(NOM)
VO2
VO1
VO0
VOUT(NOM)
0
0
0
0.80V
Z
0
1
1.35V
0
0
Z
0.85V
Z
Z
0
1.40V
0
0
1
0.90V
Z
Z
Z
1.45V
0
Z
0
0.95V
Z
Z
1
1.50V
0
Z
Z
1.00V
Z
1
0
1.55V
0
Z
1
1.05V
Z
1
Z
1.60V
0
1
0
1.10V
Z
1
1
1.65V
0
1
Z
1.15V
1
X
0
1.70V
0
1
1
1.20V
1
X
Z
1.75V
Z
0
0
1.25V
1
X
1
1.80V
Z
0
Z
1.30V
X = Don’t Care, 0 = Low, Z = Float, 1 = High
The input logic low threshold is less than 250mV referenced to GND and the logic high threshold is greater than
VBIAS – 250mV. The range between these two thresholds
as set by a window comparator defines the logic Hi-Z state.
REF/BYP—Voltage Reference
This pin is the buffered output of the internal bandgap
reference and has an output impedance of ≅ 19kΩ. The
design includes an internal compensation pole at fC =
4kHz. A 10nF REF/BYP capacitor to GND creates a lowpass pole at fLP = 840Hz. The 10nF capacitor decreases
reference voltage noise to about 10µVRMS and soft-starts
the reference. The LT3071 only soft-starts the reference
voltage during an initial turn-on sequence. If the EN pin
is toggled low after initial turn-on, the reference remains
powered-up. Therefore, toggling the EN pin from low to
high does not soft-start the reference. Only by turning
the BIAS supply voltage on and off will the reference be
soft-started. Output voltage noise is the RMS sum of the
reference voltage noise in addition to the amplifier noise.
The REF/BYP pin must not be DC loaded by anything except
for applications that parallel other LT3071 regulators for
higher output currents. Consult the Applications section
on Paralleling for further details.
Rev. D
16
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LT3071
APPLICATIONS INFORMATION
Output Voltage Margining
The LT3071’s analog margining pin, MARGA, provides a
continuous output voltage adjustment range of ±10%. It
margins VOUT by adjusting the internal 600mV reference
voltage up and down. The MARGA pin’s typical input
impedance is 190kΩ between MARGA and the internal
VREF node. Driving MARGA with 600mV to 1.2V provides
0% to 10% of adjustment. Driving MARGA with 600mV to
0V provides 0% to –10% of adjustment. If unused, allow
MARGA to float or bypass this pin with a 1nF capacitor to
GND. Note that the analog margining function does not
adjust the PWRGD threshold. Therefore, negative analog
margining may trip the PWRGD comparator and toggle
the PWRGD flag.
Enable Function—Turning On and Off
The EN pin enables/disables the output device only. The
LT3071 reference and all support functions remain active
if VBIAS is above its UVLO threshold. Pulling the EN pin
low puts the LT3071 into nap mode. In nap mode, the
reference circuit is active, but the output is disabled and
quiescent current decreases.
Drive the EN pin with either a digital logic port or an opencollector NPN or an open-drain NMOS terminated with
a pull-up resistor to VBIAS. The pull-up resistor must be
less than 35k to meet the VIH condition of the EN pin. If
unused, connect EN to BIAS.
Input Undervoltage Lockout on BIAS Pin
An internal undervoltage lockout (UVLO) comparator
monitors the BIAS supply voltage. If VBIAS drops below
the UVLO threshold, all functions shut down, the pass
transistor is gated off and output current falls to zero. The
typical BIAS pin UVLO threshold is 1.55V on the rising
edge of VBIAS. The UVLO circuit incorporates about 150mV
of hysteresis on the falling edge of VBIAS.
High Efficiency Linear Regulator—Input-to-Output
Voltage Control
The VIOC (voltage input-to-output control) pin is a function to control a switching regulator and facilitate a design
solution that maximizes system efficiency at high load currents and still provides low dropout voltage performance.
The VIOC pin is the output of an integrated transconductance amplifier that sources and sinks about 250µA
of current. It typically regulates the output of most LTC®
switching regulators or LTM® power modules, by sinking
current from the ITH compensation node. The VIOC function
controls a buck regulator powering the LT3071’s input by
maintaining the LT3071’s input voltage to VOUT + 300mV.
This 300mV VIN-VOUT differential voltage is chosen to
provide fast transient response and good high frequency
PSRR while minimizing power dissipation and maximizing
efficiency. For example, 1.5V to 1.2V conversion and 1.3V
to 1V conversion yield 1.5W maximum power dissipation
at 5A full output current.
Figure 2 depicts that the switcher’s feedback resistor network sets the maximum switching regulator output voltage
if the linear regulator is disabled. However, once the LT3071
is enabled, the VIOC feedback loop decreases the switching
regulator output voltage back to VOUT + 300mV.
Using the VIOC function creates a feedback loop between
the LT3071 and the switching regulator. As such, the
feedback loop must be frequency compensated for stability. Fortunately, the connection of VIOC to many LTC
switching regulator ITH pins represents a high impedance
characteristic which is the optimum circuit node to frequency compensate the feedback loop. Figure 2 illustrates
the typical frequency compensation network used at the
VIOC node to GND.
The VIOC amplifier characteristics are:
gm = 3.2mS, IOUT = ±250µA, BW = 10MHz.
If the VIOC function is not used, terminate the VIOC
pin to GND with a small capacitor (1000pF) to prevent
oscillations.
Rev. D
For more information www.analog.com
17
LT3071
APPLICATIONS INFORMATION
IN
LT3071
OUT
SWITCHING REGULATOR
REF
+
–
LOAD
PWM
FB
VOUT +
VREF 300mV
VIOC
REFERENCE
ITH
3071 F02
Figure 2. VIOC Control Block Diagram
PWRGD—Power Good
PWRGD pin is an open-drain NMOS digital output that
actively pulls low if any one of these fault modes is detected:
• VOUT is less than 90% of VOUT(NOMINAL) on the rising
edge of VOUT .
• VOUT drops below 85% of VOUT(NOMINAL) for more than
25µs.
• VBIAS is less than its undervoltage lockout threshold.
• The OUT-to-IN reverse-current detector activates.
• Junction temperature exceeds 145°C typically.*
*The junction temperature detector is an early warning
indicator that trips approximately 20°C before thermal
shutdown engages.
Stability and Output Capacitance
The LT3071’s feedback loop requires an output capacitor
for stability. Choose COUT carefully and mount it in close
proximity to the LT3071’s OUT and GND pins. Include wide
routing planes for OUT and GND to minimize inductance.
If possible, mount the regulator immediately adjacent to
the application load to minimize distributed inductance for
optimal load transient performance. Point-of-load applications present the best case layout scenario for extracting
full LT3071 performance.
Low ESR, X5R or X7R ceramic chip capacitors are the
LTC recommended choice for stabilizing the LT3071. Additional bulk capacitors distributed beyond the immediate
decoupling capacitors are acceptable as their parasitic ESL
and ESR, combined with the distributed PCB inductance
isolates them from the primary compensation pole provided
by the local surface mount ceramic capacitors.
The LT3071 requires a minimum output capacitance of
15µF for stability. LTC strongly recommends that the output
capacitor network consist of several low value ceramic
capacitors in parallel.
Why Do Multiple, Small-Value Output Capacitors
Connected in Parallel Work Better?
The LT3071’s unity-gain bandwidth with COUT of 15µF is
about 1MHz at its full-load current of 5A. Surface mounted
MLCC capacitors have a self-resonance frequency of
fR = 1/(2π√LC), which must be pushed to a frequency higher
than the regulator bandwidth. Standard MLCC capacitors
are acceptable. To keep the resonant frequency greater
than 1MHz, the product 1/(2π√LC) must be greater than
1MHz. At this bandwidth, PCB vias can add significant
inductance, thus the fundamental decoupling capacitors
must be mounted on the same plane as the LT3071.
Rev. D
18
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LT3071
APPLICATIONS INFORMATION
Typical 0603 or 0805 case-size capacitors have an ESL of
~800pH and PCB mounting can contribute up to ~200pH.
Thus, it becomes necessary to reduce the parasitic inductance by using a parallel capacitor combination. A
suitable methodology must control this paralleling as
capacitors with the same self-resonant frequency, fR, will
form a tank circuit that can induce ringing of their own
accord. Small amounts of ESR (5mΩ to 20mΩ) have some
benefit in dampening the resonant loop, but higher ESRs
degrade the capacitor response to transient load steps
with rise/fall times less than 1µs. The most area efficient
parallel capacitor combination is a graduated 4/2/1 scale
of fR of the same case size. Under these conditions, the
individual ESLs are relatively uniform, and the resonance
peaks are deconstructively spread beyond the regulator
bandwidth. The recommended parallel combination that
approximates 15µF is 10µF + 4.7µF + 2.2µF. Capacitors
with case sizes larger than 0805 have higher ESL and
lower ESR (
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