LT6372-0.2
Precision, Funneling Instrumentation Amplifier
with Level Shift and Output Clamping
FEATURES
DESCRIPTION
Single Gain Set Resistor: G = 0.2 to >200
n Excellent DC Precision
n Input Offset Voltage: 60μV Max
n Input Offset Voltage Drift: 0.6μV/°C Max
n Low Gain Error: 0.012% Max (G = 0.2)
n Low Gain Drift: 35ppm/°C Max (G > 0.2)
n High DC CMRR: 80dB Min (G = 0.2)
n Integrated Output Clamps
n Integrated Output Level Shift
n Input Bias Current: 800pA Max
n 4MHz –3dB Bandwidth (G = 0.2)
n Low Noise:
n 0.1Hz to 10Hz Noise: 0.2μV
P-P
n 1kHz Voltage Noise: 7nV/√Hz
n Integrated Input RFI Filter
n Wide Supply Range 4.75V to 35V
n Temperature Ranges: –40°C to 85°C and –40°C to 125°C
n MS16E and 20-Lead 3mm × 4mm QFN Packages
The LT®6372-0.2 is a gain programmable, high precision
funneling instrumentation amplifier that delivers industry
leading DC precision. This high precision enables smaller
signals to be sensed and eases calibration requirements,
particularly over temperature. The LT6372-0.2 incorporates features into the LT6370 which further improve
accuracy and simplify interfacing to an ADC.
n
APPLICATIONS
Bridge Amplifier
Data Acquisition
n Thermocouple Amplifier
n Strain Gauge Amplifier
n Medical Instrumentation
n Transducer Interfaces
n Differential to Single-Ended Conversion
n
n
The LT6372-0.2 uses a proprietary high performance
bipolar process which enables industry leading accuracy coupled with exceptional long-term stability. The
LT6372-0.2 is laser trimmed for very low input offset voltage (60µV) and high CMRR (80dB, G = 0.2). Proprietary
on-chip test capability allows the gain drift (35ppm/°C)
to be guaranteed with automated testing.
The LT6372-0.2’s difference amplifier uses a split reference configuration which simplifies level shifting the
amplifier’s output to the center of the ADC’s input range.
Output clamp pins are also provided to limit the voltage
which can be applied to an ADC’s input. EMI filtering is
integrated on the LT6372-0.2’s inputs to maintain accuracy in the presence of harsh RF interference.
The LT6372-0.2 is available in a compact MS16E or a 20-pin
3mm x 4mm QFN. The LT6372-0.2 is fully specified over the
–40°C to 85°C and –40°C to 125°C temperature ranges.
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
LT6372-0.2 Funnels and Level Shifts
±10V Inputs to 5V ADC Input Range
12.5
4.5V
+
2.5V
V+
LT6372-0.2
0V
20V
VIN
–
REF1
V–
VIN
CLHI
CLLO
VOUT
7.5
2.5V
REF
91Ω
10nF
VIN
VOUT
10.0
LTC6655-5 VOUT
4V
0.5V
REF2
10V
15V
VDD
LTC2367-16
5.0
VOLTAGE (V)
15V
ADC INPUT
RANGE
2.5
0
–2.5
–5.0
GND
–10V
–7.5
–15V
637202 TA01a
–10.0
–12.5
10µs/DIV
637202 TA01b
Rev. 0
Document Feedback
For more information www.analog.com
1
LT6372-0.2
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage (V+ to V–)..................................36V
Input Voltage (+IN, –IN, +RG,S, +RG,F, –RG,S, –RG,F,
REF1, REF2, CLHI, CLLO).... (V– – 0.3V) to (V+ + 0.3V)
Differential Input Voltage
(+IN to –IN)..........................................................±36V
(REF1 to REF2)......................................................±8V
Input Current
(+RGS, +RGF, –RGS, –RGF)...................................±2mA
(+IN, –IN, CLLO)............................................... ±10mA
(REF1, REF2, CLHI)...........................................–10mA
Output Short-Circuit Duration..............Thermally Limited
Output Current........................................................80mA
Operating and Specified Temperature Range
I-Grade.................................................–40°C to 85°C
H-Grade.............................................. –40°C to 125°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
PIN CONFIGURATION
+RG,S
NIC 1
16 NIC
–IN 2
15 REF2
NIC 3
NIC 4
13 OUTPUT
+IN 5
12 REF1
NIC 6
11 NIC
7
8
9 10
CLHI
MSE PACKAGE
16-LEAD PLASTIC MSOP
θJA = 35°C/W
EXPOSED PAD (PIN 17) MUST FLOAT OR
BE CONNECTED TO V+ IN ADDITION TO PIN 12
14 V+
21
V–
DNC
+RG,F
+RG,S
NIC
REF2
V+
OUTPUT
REF1
CLHI
CLLO
17
16
15
14
13
12
11
10
9
V–
1
2
3
4
5
6
7
8
+RG,F
20 19 18 17
TOP VIEW
–RG,F
–RG,S
NIC
–IN
+IN
NIC
CLLO
V–
–RG,F
–RG,S
TOP VIEW
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
θJA = 52°C/W
EXPOSED PAD (PIN 21) IS CONNECTED
–
TO V (PIN 7) (PCB CONNECTION OPTIONAL)
ORDER INFORMATION
TUBE
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT6372IMSE-0.2#PBF
LT6372IMSE-0.2#TRPBF
637202
16-Lead Plastic MSOP
–40°C to 85°C
LT6372HMSE-0.2#PBF
LT6372HMSE-0.2#TRPBF
637202
16-Lead Plastic MSOP
–40°C to 125°C
LT6372IUDC-0.2#PBF
LT6372IUDC-0.2#TRPBF
LHHQ
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 85°C
LT6372HUDC-0.2#PBF
LT6372HUDC-0.2#TRPBF
LHHQ
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
2
Rev. 0
For more information www.analog.com
LT6372-0.2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 4kΩ.
SYMBOL PARAMETER
CONDITIONS
MIN
G
Gain Range
G = 0.2 • (1 + 24.2k/RG) (Note 2)
0.2
Gain Error (Notes 3, 4)
G = 0.2
G = 0.2
G=1
G=1
G = 10
G = 10
G = 100
G = 100
G = 200
G = 200
Gain vs Temperature (Notes 3, 4)
G = 0.2 (Note 5)
G > 0.2 (Note 6)
Gain Nonlinearity (Notes 3, 7)
VOUT = 0V to 4.096V, G = 0.2
VOUT = 0V to 4.096V, G = 1
VOUT = 0V to 4.096V, G = 10
VOUT = 0V to 4.096V, G = 100
VOUT = 0V to 4.096V, G = 200
TYP
MAX
UNITS
200
V/V
0.002
0.012
0.015
0.15
0.45
0.15
0.45
0.15
0.45
0.15
0.53
%
%
%
%
%
%
%
%
%
%
l
0.01
l
0.02
l
0.02
l
0.03
l
0.2
20
0.5
35
ppm/°C
ppm/°C
3
4
5
6
12
5
60
80
ppm
ppm
ppm
ppm
ppm
±15
±60
±175
μV
μV
±30
l
±175
±300
μV
μV
l
±0.6
μV/°C
l
l
VOST, Total Input Referred Offset Voltage, VOST = VOSI + VOSO/G
VOSI
VOSO
VOSI/T
Input Offset Voltage
(Note 8)
Output Offset Voltage (Note 8)
Input Offset Voltage Drift
(Notes 5, 8)
Input Offset Voltage
Hysteresis (Note 9)
VOSO/T
IB
IOS
l
TA = –40°C to 125°C
Output Offset Voltage Drift
(Notes 5, 8)
l
Output Offset Voltage Hysteresis (Note 9) TA = –40°C to 125°C
l
Input Bias Current
TA = –40°C to 85°C
TA = –40°C to 125°C
±3
l
±2
±10
μV
±0.8
±1.5
±3
nA
nA
nA
±0.2
±1.4
±4
nA
nA
l
0.1Hz to 10Hz, G = 0.2
0.1Hz to 10Hz, G = 200
μV/°C
±0.1
l
l
Input Offset Current
Input Noise Voltage (Note 10)
μV
4
0.2
μVP-P
μVP-P
Total RTI Noise = √eni2 + (eno/G)2 (Note 10)
eni
Input Noise Voltage Density
f = 1kHz
7
nV/√Hz
eno
Output Noise Voltage Density
f = 1kHz
32
nV/√Hz
Input Noise Current
0.1Hz to 10Hz
10
pAP-P
in
Input Noise Current Density
f = 1kHz
200
fA/√Hz
RIN
Input Resistance
VIN = –12.6V to 13V
225
GΩ
CIN
Differential
Common Mode
f = 100kHz
f = 100kHz
0.9
15.9
pF
pF
VCM
Input Voltage Range
Guaranteed by CMRR
l
V– + 1.8/V+ – 1.4
V+ – 2
V– + 2.4
V
V
Rev. 0
For more information www.analog.com
3
LT6372-0.2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 4kΩ.
SYMBOL PARAMETER
CONDITIONS
CMRR
DC to 60Hz, 1k Source Imbalance,
VCM = –12.6V to 13V
G = 0.2
G = 0.2
G=1
G=1
G = 10
G = 10
G = 100
G = 200
G = 200
Common Mode Rejection Ratio
AC Common Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
MIN
TYP
96
l
80
74
95
89
114
108
l
125
119
l
l
110
130
146
146
dB
dB
dB
dB
f = 20kHz, MS16E Package
G = 0.2
G=2
G = 20
G = 200
80
100
104
104
dB
dB
dB
dB
121
dB
dB
dB
dB
dB
dB
dB
dB
dB
VS = ±2.375V to ±17.5V
G = 0.2
G = 0.2
G=1
G=1
G = 10
G = 10
G = 100
G = 100
G = 200
l
106
104
120
117
128
122
128
122
4.75
l
l
l
Guaranteed by PSRR
l
IS
Supply Current
VS = ±15V
TA = –40°C to 85°C
TA = –40°C to 125°C
l
l
VS = ±2.375V
TA = –40°C to 85°C
TA = –40°C to 125°C
l
l
VS = ±15V, RL = 10kΩ
135
140
142
146
35
V
2.75
2.85
3
3.1
mA
mA
mA
2.65
2.7
2.85
2.95
mA
mA
mA
–14.4
–14.2
–14.7/14
l
13.6
13.5
V
V
–0.7
–0.5
–1/1.6
l
1.4
1.2
V
V
35
30
55
l
mA
mA
VS = ±2.375V, RL = 10kΩ
IOUT
dB
dB
dB
dB
dB
dB
dB
dB
dB
62
82
104
104
Supply Voltage
Output Voltage Swing
UNITS
f = 20kHz, QFN20 Package
G = 0.2
G=2
G = 20
G = 200
VS
VOUT
MAX
Output Short Circuit Current
BW
–3dB Bandwidth
G = 0.2
G=1
G = 10
G = 100
G = 200
4
2
1
140
15
MHz
MHz
MHz
kHz
kHz
SR
Slew Rate
G = 1, VOUT = ±2.5V
3.5
V/μs
4
Rev. 0
For more information www.analog.com
LT6372-0.2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 4kΩ.
SYMBOL PARAMETER
CONDITIONS
tS
Settling Time
4.096V Output Step to 0.0015%
G = 0.2
G=1
G = 10
G = 100
G = 200
MIN
RREFIN
REF Input Resistance
REF1 or REF2, Untested REF pin floating
IREFIN
REF Input Current
V+IN = V–IN = VREF1 = VREF2= 0V, REF1 or REF2
VREF
REF Voltage Range
REF1 or REF2
AVREF
REF Gain to Output
VREF1 = 0V to 5V, VREF2 = 0V
REF Gain Error
VREF1 = 0V to 5V, VREF2 = 0V
l
–36
–50
l
V–
TYP
MAX
1.8
2.5
12.4
68
135
μs
μs
μs
μs
μs
14
kΩ
–24
–12
0
V+
0.5
l
–250
–300
UNITS
±75
μA
μA
V
V/V
250
300
ppm
ppm
CLLO Input Current
VCLLO = 0V
l
1
µA
CLHI Input Current
VCLHI = 5V
l
1
µA
V+ – 2
V
V+ – 2.5
CLLO Input Operating Voltage Range
Outside this Range CLLO is Disabled
l
V– + 3
CLHI Input Operating Voltage Range
Outside this Range CLHI is Disabled
l
V– + 2
l
–0.57
–0.74
CLLO Clamp Voltage (VOUT – VCLLO)
CLHI Clamp Voltage (VOUT – VCLHI)
–0.45
0.45
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Gains higher than 200 are possible but the resulting low RG values
can make PCB and package lead resistance a significant error source.
Note 3: For gains greater than 0.2V/V, gain tests are performed with –IN at
mid-supply and +IN driven. The gain of 0.2V/V testing is performed with
–IN and +IN driven differentially.
Note 4: When the gain is greater than 0.2 the gain error and gain drift
specifications do not include the effect of external gain set resistor RG.
Note 5: This specification is guaranteed by design.
Note 6: This specification is guaranteed with high-speed automated testing.
Note 7: This parameter is measured in a high speed automatic tester that
does not measure the thermal effects with longer time constants. The
V
V
V
0.55
0.755
V
V
magnitude of these thermal effects are dependent on the package used,
PCB layout, heat sinking and air flow conditions.
Note 8: For more information on how offsets relate to the amplifiers, see
section “Input and Output Offset Voltage” in the Applications section.
Note 9: Hysteresis in output voltage is created by mechanical stress
that differs depending on whether the IC was previously at a higher or
lower temperature. Output voltage is always measured at 25°C, but
the IC is cycled to the hot or cold temperature limit before successive
measurements. Hysteresis is roughly proportional to the square of the
temperature change. For instruments that are stored at well controlled
temperatures (within 20 or 30 degrees of operational temperature),
hysteresis is usually not a significant error source. Typical hysteresis is the
worst case of 25°C to cold to 25°C or 25°C to hot to 25°C, preconditioned
by one thermal cycle.
Note 10: Referred to the input.
Rev. 0
For more information www.analog.com
5
LT6372-0.2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 4k, unless otherwise noted.
Distribution of Input Offset
Voltage, MS16E Package
50
50
40
40
TA = –40°C TO 85°C
45 50 UNITS
50 UNITS
40
PERCENTAGE OF PARTS (%)
35
30
25
20
15
10
35
30
25
20
15
10
25
20
15
10
5
5
0
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
0
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
45
637202 G03
637202 G02
Distribution of Input Offset
Voltage Drift, QFN Package
Distribution of Input Offset
Voltage Drift, QFN Package
50
50
40
40
TA = –40°C TO 85°C
45 50 UNITS
50 UNITS
PERCENTAGE OF PARTS (%)
40
35
30
25
20
15
10
TA = –40°C TO 125°C
45 50 UNITS
PERCENTAGE OF PARTS (%)
50
PERCENTAGE OF PARTS (%)
30
0
–50 –40 –30 –20 –10 0 10 20 30 40 50
INPUT OFFSET VOLTAGE (µV)
Distribution of Input Offset
Voltage, QFN Package
35
30
25
20
15
10
35
30
25
20
15
10
5
5
5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50
INPUT OFFSET VOLTAGE (µV)
0
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
0
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
637202 G04
637202 G05
Distribution of Output Offset
Voltage, MS16E Package
50
45
637202 G06
Distribution of Output Offset
Voltage Drift, MS16E Package
Distribution Output Offset Voltage
Drift, MS16E Package
50
50 UNITS
60
TA = –40°C TO 85°C
45 50 UNITS
40
PERCENTAGE OF PARTS (%)
PERCENTAGE OF PARTS (%)
35
5
637202 G01
35
30
25
20
15
10
55
40
35
30
25
20
15
10
50
TA = –40°C TO 125°C
50 UNITS
45
40
35
30
25
20
15
10
5
5
5
0
–240 –180 –120 –60 0
60 120 180 240
OUTPUT OFFSET VOLTAGE (µV)
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
OUTPUT OFFSET VOLTAGE DRIFT (µV/°C)
0
–2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5
OUTPUT OFFSET VOLTAGE DRIFT (µV/°C)
637202 G07
6
TA = –40°C TO 125°C
45 50 UNITS
PERCENTAGE OF PARTS (%)
PERCENTAGE OF PARTS (%)
45
Distribution of Input Offset
Voltage Drift, MS16E Package
PERCENTAGE OF PARTS (%)
50
Distribution of Input Offset
Voltage Drift, MS16E Package
637202 G08
637202 G09
Rev. 0
For more information www.analog.com
LT6372-0.2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 4k, unless otherwise noted.
Distribution of Output Offset
Voltage Drift, QFN Package
Distribution of Output Offset
Voltage, QFN Package
50 UNITS
50
50
40
40
TA = –40°C TO 85°C
45 50 UNITS
45
PERCENTAGE OF PARTS (%)
PERCENTAGE OF PARTS (%)
50
40
35
30
25
20
15
10
TA = –40°C TO 125°C
45 50 UNITS
PERCENTAGE OF PARTS (%)
55
35
30
25
20
15
10
30
25
20
15
10
5
5
0
–240 –180 –120 –60 0
60 120 180 240
OUTPUT OFFSET VOLTAGE (µV)
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
OUTPUT OFFSET VOLTAGE DRIFT (µV/°C)
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
OUTPUT OFFSET VOLTAGE DRIFT (µV/°C)
637202 G11
45
40
Distribution of REF Divide
Gain Error
Distribution of Gain Error
50
G = 0.2
TA = 25°C
360 UNITS
45
PERCENTAGE OF PARTS (%)
50
637202 G12
35
30
25
20
15
10
40
50
G = 200
TA = 25°C
360 UNITS
45
PERCENTAGE OF PARTS (%)
Distribution of Gain Error
PERCENTAGE OF PARTS (%)
35
5
637202 G10
35
30
25
20
15
10
5
5
0
–25 –20 –15 –10 –5 0 5 10 15 20 25
GAIN ERROR (ppm)
0
–800
40
35
30
25
20
15
10
–600
–400
–200
GAIN ERROR (ppm)
0
0
–200
200
REF Divider Gain Drift
Gain Drift (G = 0.2)
50
50
30
30
20
20
G = 0.2
40 18 UNITS
GAIN ERROR (ppm)
0
–20
–40
GAIN ERROR (ppm)
REF1 = REF2
40 8 UNITS
REF1 = 0V
80 REF2 = ±10V
8 UNITS
60
10
0
–10
–20
10
0
–10
–20
–60
–30
–30
–80
–40
–40
–100
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
637202 G16
–50
–50
–25
0
25
50
75
TEMPERATURE (°C)
200
637202 G15
REF Gain Drift
20
–100
0
100
GAIN ERROR (ppm)
637202 G14
100
40
REF2 = 0V
REF1 = 0V to 5V
TA = 25°C
360 UNITS
5
637202 G13
GAIN ERROR (ppm)
Distribution of Output Offset
Voltage Drift, QFN Package
100
125
637202 G17
–50
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
637202 G18
Rev. 0
For more information www.analog.com
7
LT6372-0.2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 4k, unless otherwise noted.
Lead Free Reflow Profile Due to
IR Reflow
0
300
G = 200
–600 17 UNITS
TL = 217°C
TS(MAX) = 200°C
225
–1800
TS = 190°C
–2400
–3000
–4200
40s
–5400
0
25
50
75
TEMPERATURE (°C)
100
0
125
Gain Nonlinearity (G = 1)
15
0
2
4
6
MINUTES
–5
–15
10
8
GAIN NONLINEARITY (ppm)
5
0
–5
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
0
–5
–40
HARMONIC DISTORTION (dBc)
40
–50
20
0
–20
–40
–60
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
5
637202 G25
4.5
5
0
–10
–20
0
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
–30
5
0
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
–40
VREF1 = 0V
VREF2 = 5V
V+= +15V
V– = –15V
VOUT = 5VP-P
–50
–70
–80
–90
–100
HD2
HD3
THD
–120
0.1
1
10
FREQUENCY (kHz)
100
637202 G26
4
4.5
5
637202 G24
Harmonic Distortion vs
Frequency, G = 0.25, RL = 2k
–110
0
4
10
637202 G23
Gain Nonlinearity (G = 200)
VOUT = 0V to 5V
VREF1 = VCLLO = 0V
VREF2 = VCLHI = 5V
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
VOUT = 0V to 5V
VREF1 = VCLLO = 0V
VREF2 = VCLHI = 5V
20
637202 G22
60
1
Gain Nonlinearity (G = 100)
30
5
–15
5
0.5
637202 G21
–10
0
0
637202 G20
VOUT = 0V to 5V
VREF1 = VCLLO = 0V
VREF2 = VCLHI = 5V
10
–10
GAIN NONLINEARITY (ppm)
0
Gain Nonlinearity (G = 10)
15
VOUT = 0V to 5V
VREF1 = VCLLO = 0V
VREF2 = VCLHI = 5V
10
8
5
–10
GAIN NONLINEARITY (ppm)
–25
637202 G19
–60
VOUT = 0V to 5V
VREF1 = VCLLO = 0V
VREF2 = VCLHI = 5V
10
120s
–6000
–50
GAIN NONLINEARITY (ppm)
tP
30s
tL
130s
RAMP TO
150°C
75
–4800
RAMP
DOWN
T = 150°C
150
–3600
–15
TP = 260°C
HARMONIC DISTORTION (dBc)
GAIN ERROR (ppm)
–1200
380s
Gain Nonlinearity (G = 0.2)
15
GAIN NONLINEARITY (ppm)
Gain Drift (G = 200)
–60
Harmonic Distortion vs
Frequency, G = 1, RL = 2k
VREF1 = 0V
VREF2 = 5V
V+ = +15V
V– = –15V
VOUT = 5VP-P
–70
–80
–90
–100
HD2
HD3
THD
–110
–120
0.1
1
10
FREQUENCY (kHz)
100
637202 G27
Rev. 0
For more information www.analog.com
LT6372-0.2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 4k, unless otherwise noted.
–60
–70
–80
–90
–100
HD2
HD3
THD
–110
–120
0.1
1
10
FREQUENCY (kHz)
REF1 = 0V
REF2= 5V
V+= +15V
V–= –15V
f= 2kHz
–80
80
5
6
7
8
9
OUTPUT SWING (Vpp)
80
G = 0.2
G=2
G = 20
G = 200
100
1k
10k
FREQUENCY (Hz)
160
120
100
80
60
G = 0.2
G=2
G = 20
G = 200
40
20
0.1
100k
1
10
100 1k 10k 100k
FREQUENCY (Hz)
G = 0.2
G=2
G = 20
G = 200
10
100
1k
FREQUENCY (Hz)
10k
1M
100k
637202 G34
VS = ±15V
120
100
80
60
G = 0.2
G=2
G = 20
G = 200
40
20
10
100
1k
10k
FREQUENCY (Hz)
1M
637202 G33
0.1Hz to 10Hz Noise Voltage,
G = 0.2, RTI
VS = ±15V
TA = 25°C
G = 0.2
UNBALANCED SOURCE R
BALANCED SOURCE R
100
10
0.1
100k
NOISE VOLTAGE (1µV/DIV)
CURRENT NOISE DENSITY (fA/√Hz)
VOLTAGE NOISE DENSITY (nV/√Hz)
1000
100k
140
637202 G32
1k
10
1k
10k
FREQUENCY (Hz)
160
Current Noise Density vs
Frequency
100
100
Negative Power Supply Rejection
Ratio vs Frequency
140
Input-Referred Voltage Noise
Density vs Frequency
1
10
637202 G30
VS = ±15V
637202 G31
1
0.1
40
11
NEGATIVE POWER SUPPLY REJECTION
RATIO (dB)
100
10
10
637202 G29
POSITIVE POWER SUPPLY REJECTION
RATIO (dB)
CMRR (dB)
120
40
G = 0.2
G=2
G = 20
G = 200
60
Positive Power Supply Rejection
Ratio vs Frequency
QFN PACKAGE
VS = ±15V
TA = 25°C
60
100
–100
CMRR vs Frequency, RTI
QFN Package
140
MS16E PACKAGE
VS = ±15V
TA = 25°C
140
120
637202 G28
160
160
HD2
HD3
THD
–90
–110
100
CMRR vs Frequency, RTI
MS16E Package
Harmonic Distortion vs Output
Swing, G = 10, RL = 2k
CMRR (dB)
HARMONIC DISTORTION (dBc)
–50
–70
VREF1 = 0V
VREF2 = 5V
V+ = 15V
V– = –15V
VOUT = 5VP-P
HARMONIC DISTORTION (dBc)
–40
Harmonic Distortion vs
Frequency, G = 10, RL = 2k
1
10
100
1k
FREQUENCY (Hz)
10k
100k
TIME (1s/DIV)
637202 G35
637202 G36
Rev. 0
For more information www.analog.com
9
LT6372-0.2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 4k, unless otherwise noted.
0.1Hz to 10Hz Noise Voltage,
G = 20, RTI
VS = ±15V
TA = 25°C
G = 20
VS = ±15V
TA = 25°C
G = 200
NOISE VOLTAGE (50nV/DIV)
VS = ±15V
TA = 25°C
G=2
TIME (1s/DIV)
TIME (1s/DIV)
TIME (1s/DIV)
637202 G37
637202 G38
0.1Hz to 10Hz Noise Current,
Unbalanced Source R
637202 G39
0.1Hz to 10Hz Noise Current,
Balanced Source R
UNBALANCED SOURCE R
VS = ±15V
TA = 25°C
REF Pin Current vs Input
Common Mode Voltage
1600
BALANCED SOURCE R
VS = ±15V
TA = 25°C
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
1200
REF PIN CURRENT (µA)
NOISE CURRENT (500fA/DIV)
NOISE CURRENT (1pA/DIV)
0.1Hz to 10Hz Noise Voltage,
G = 200, RTI
NOISE VOLTAGE (50nV/DIV)
NOISE VOLTAGE (100nV/DIV)
0.1Hz to 10Hz Noise Voltage,
G = 2, RTI
800
400
0
–400
–800
–1200
–1600
–15
TIME (1s/DIV)
TIME (1s/DIV)
637202 G40
Input Bias and Offset Current vs
Temperature
1.0
0.8
0.8
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–15
+IN BIAS CURRENT
–IN BIAS CURRENT
OFFSET CURRENT
–10
–5
0
5
10
INPUT COMMON–MODE VOLTAGE (V)
15
637202 G43
10
Supply Current vs Supply Voltage
3.0
2.5
0.6
SUPPLY CURRENT (mA)
INPUT BIAS, OFFSET CURRENTS (nA)
INPUT BIAS, OFFSET CURRENTS (nA)
1.0
0.4
0.2
0.0
–0.2
–0.4
–0.6
+IN BIAS CURRENT
–IN BIAS CURRENT
OFFSET CURRENT
–0.8
–1.0
–50
15
6370 G42
637202 G41
Input Bias Current vs Common
Mode Voltage
0.6
–10
–5
0
5
10
COMMON-MODE INPUT VOLTAGE (V)
–25
0
25
50
75
TEMPERATURE (°C)
100
125
637202 G44
2.0
1.5
1.0
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
0.5
0
0
5
10 15 20 25 30
SUPPLY VOLTAGE (V)
35
40
637202 G45
Rev. 0
For more information www.analog.com
LT6372-0.2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 4k, unless otherwise noted.
Positive Output Swing vs
Resistive Load
6.0
14.5
5.9
14.0
5.8
13.5
13.0
12.5
12.0
11.5
TA = 125°C
VS = ±15V
11.0 REF1
TA = 85°C
= REF2 = 10V
TA = 25°C
10.5 G = 200
VIN = 2V
TA = –40°C
10.0
1
10
100
RESISTIVE LOAD (kΩ)
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
5.7
5.6
5.5
5.4
SWING LIMITED AT
5.3 PRE–AMPLIFIER OUTPUTS
V = ±15V
5.2 S
REF1 = REF2 = 0V
5.1 G = 200
VIN = 2V
5.0
0.1
1
10
RESISTIVE LOAD (kΩ)
637202 G46
–6.0
0.1
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
1
10
RESISTIVE LOAD (kΩ)
–14.5
–15.0
100
VOUT
1V/DIV
1
10
RESISTIVE LOAD (kΩ)
100
637202 G48
Slew Rate vs Temperature
60
G = 0.2
9 VOUT = 4VP-P
50
7
RISING
FALLING
8
40
30
20
10
0
–50
±15V, SINK
±15V, SOURCE
±4.75V, SINK
±4.75V, SINK
–25
0
25
50
75
TEMPERATURE (°C)
6
5
4
3
2
1
100
125
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
637202 G50
VOUT
1V/DIV
100
125
637202 G51
Large Signal Transient Response
Large Signal Transient Response
G = 0.2
VS = ±15V
TA = 25°C
CL = 100pF
–14.0
10
637202 G49
2µs/DIV
–13.5
SLEW RATE (V/µs)
–5.6
SHORT CIRCUIT CURRENT (mA)
NEGATIVE OUTPUT SWING (V)
–5.5
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
–13.0
70
SWING LIMITED AT
–5.1 PRE-AMPLIFIER OUTPUTS
VS = ±15V
–5.2
REF1 = REF2 = 0V
–5.3 G = 200
VIN = –2V
–5.4
–5.9
VS = ±15V
REF1 = REF2 = –10V
–12.5 G = 200
VIN = –2V
Short-Circuit Current vs
Temperature
–5.0
–5.8
100
–12.0
637202 G47
Negative Output Swing vs
Resistive Load
–5.7
Negative Output Swing vs
Resistive Load
NEGATIVE OUTPUT SWING (V)
15.0
POSITIVE OUTPUT SWING (V)
POSITIVE OUTPUT SWING (V)
Positive Output Swing vs
Resistive Load
Large Signal Transient Response
VOUT
1V/DIV
637202 G52
G=2
VS = ±15V
TA = 25°C
CL = 100pF
4µs/DIV
637202 G53
G = 20
VS = ±15V
TA = 25°C
CL = 100pF
10µs/DIV
637202 G54
Rev. 0
For more information www.analog.com
11
LT6372-0.2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 4k, unless otherwise noted.
Small Signal Transient Response
Large Signal Transient Response
Small Signal Transient Response
VOUT
5mV/DIV
VOUT
1V/DIV
637202 G55
100µs/DIV
G = 200
VS = ±15V
TA = 25°C
CL = 100pF
VOUT
5mV/DIV
G = 0.2
VS = ±15V
TA = 25°C
CL = 100pF
637202 G56
1µs/DIV
Small Signal Transient Response
Small Signal Transient Response
637202 G57
1µs/DIV
G=2
VS = ±15V
TA = 25°C
CL = 100pF
Gain vs Frequency
56
VS = ±15V
TA = 25°C
46
36
VOUT
5mV/DIV
26
GAIN (dB)
VOUT
5mV/DIV
16
6
–4
–14
637202 G58
10µs/DIV
G = 20
VS = ±15V
TA = 25°C
CL = 100pF
G = 200
VS = ±15V
TA = 25°C
CL = 100pF
100µs/DIV
–24
637202 G59
–34
–44
100
G = 0.2
G=2
G = 20
G = 200
1k
10k
100k
FREQUENCY (Hz)
1M
10M
637202 G60
Supply Current While Clamping
VIN
200mV/DIV
OUT
IN
VCHI = 4.1V
VCLO = 0V
VREF1 = 0V
VREF2 = 4.1V
10µs/DIV
637202 G61
VOUT
I+
I–
7
600
6
5
4
6
3
4
2
2
0
–2
VS = ±15V
VREF2 = VCLHI = 4.1V
VREF1 = VCLLO = 0V
RL = 10kΩ
G = 20
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5
INPUT VOLTAGE (V)
637202 G62
12
800
SUPPLY CURRENT (mA)
VOUT
2V/DIV
CLAMPED OUTPUT VOLTAGE (V)
VS = ± 15V
G = 20
Clamp Voltage vs Temperature
8
CLAMPED OUTPUT VOLTAGE (mV)
Clamp Transient Response
VS = ±15V
VCLHI = VCLLO = 0V
400
CLAMPED HIGH
200
0
–200
CLAMPED LOW
–400
–600
–800
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
637202 G63
Rev. 0
For more information www.analog.com
LT6372-0.2
PIN FUNCTIONS
(MS16E/QFN20)
–RG,F (Pin 1/Pin 19): For use with an external gain setting
resistor. This connection should be routed to the gain setting resistor separately from –RG,S in order to minimize
gain errors.
REF1 (Pin 10/Pin 12): Reference for the output voltage.
REF1 can be tied to REF2 and used as a reference for the
output. REF1 can also be used with REF2 to form a voltage
divider and level shift the output.
–RG,S (Pin 2/Pin 20): For use with an external gain setting resistor. This connection should be routed to the gain
setting resistor separately from –RG,F in order to minimize
gain errors.
OUTPUT (Pin 11/Pin 13): Output voltage referenced to
the REF pins.
–IN (Pin 4/Pin 2): Negative Input Terminal. This input is
high impedance.
+IN (Pin 5/Pin 5): Positive Input Terminal. This input is
high impedance.
REF2 (Pin 13/Pin 15): Reference for the output voltage.
REF2 can be tied to REF1 and used as a reference for the
output. REF2 can also be used with REF1 to form a voltage
divider and level shift the output.
CLLO (Pin 7/Pin 8): Low Side Clamp Input. The voltage
applied to the CLLO pin defines the lower voltage limit
of the output. Typically, the output clamps 500mV below
the voltage applied to the CLLO pin. Do not float CLLO.
+RG,S (Pin 15/Pin 17): For use with an external gain setting resistor. This connection should be routed to the gain
setting resistor separately from +RG,F in order to minimize
gain errors.
V– (Pin 8/Pin 7): Negative Power Supply. A bypass capacitor should be used between supply pins and ground.
+RG,F (Pin 16/Pin 18): For use with an external gain setting resistor. This connection should be routed to the gain
setting resistor separately from +RG,S in order to minimize
gain errors.
CLHI (Pin 9/Pin 10): High Side Clamp Input. The voltage
applied to the CLHI pin defines the upper voltage limit of
the output. Typically, the output clamps 500mV above the
voltage applied to the CLHI pin. Do not float CLHI.
V+ (Pin 12/Pin 14): Positive Power Supply. A bypass
capacitor should be used between supply pins and ground.
NIC (Pins 3, 6, 14/Pins 1, 3, 4, 6, 11, 16): No Internal
Connection.
DNC (QFN Pin 9): Do Not Connect. This pin should float.
Rev. 0
For more information www.analog.com
13
LT6372-0.2
SIMPLIFIED BLOCK DIAGRAM
V+
R1
12.1k
I1
D2
C1
D1
–IN
EMI
FILTER
200Ω
V+
Q1
D3
D4
I3
–
I2
VB
–RG,F
+
R6
2k
R5
10k
A1
OUTPUT
D13
V–
V–
–RG,S
D20
D9
D14
V–
V+
D21
+RG,S
D13
+
V+
R2
12.1k
I4
D6
EMI
FILTER
CLHI
–
D15
+RG,F
+IN
D11
D18
A3
V–
D17
R9
4k
C2
V–
D5
200Ω
D8
I6
REF2
D19
Q2
D7
CLLO
–
I5
VB
+
A2
R7
10k
R8
4k
V–
REF1
D10
V–
V–
D16
V+
V–
PREAMP STAGE
DIFFERENCE AMPLIFIER STAGE
637202 BD
14
Rev. 0
For more information www.analog.com
LT6372-0.2
THEORY OF OPERATION
The LT6372-0.2 is an improved version of the classic three
op amp instrumentation amplifier topology that incorporates features to improve accuracy and simplify interfacing
to ADCs. Laser trimming and proprietary monolithic construction allow for tight matching and extremely low drift
of circuit parameters over the specified temperature range.
Refer to the Simplified Block Diagram to aid in understanding the following circuit description. The collector currents
in Q1 and Q2 as well as I1 and I4 are trimmed to minimize
input offset voltage drift, thus assuring a high level of performance. R1 and R2 are trimmed to an absolute value of
12.1k to assure that the gain can be set accurately (0.15%
at G = 100) with only one external resistor, RG. The value of
RG determines the transconductance of the preamp stage.
As RG is reduced to increase the programmed gain, the
transconductance of the input preamp stage also increases
to that of the input transistors Q1 and Q2. This causes the
open-loop gain to increase when the programmed gain is
increased, reducing the input related errors and noise. The
input voltage noise at high gains is determined only by Q1
and Q2. At lower gains, noise of the difference amplifier
and preamp gain setting resistors may increase the noise.
The gain bandwidth product is determined by C1, C2 and
the preamp transconductance, which increases with programmed gain. Therefore, the bandwidth is self-adjusting
and does not drop directly proportional to gain.
The input transistors Q1 and Q2 offer excellent matching,
drift and noise performance, which is due to using a proprietary high performance process, as well as low input
bias current due to the high beta of these input devices.
The input bias current is further reduced by trimming I3
and I6. The collector currents in Q1 and Q2 are held constant due to the feedback through the Q1-A1-R1 loop and
Q2-A2-R2 loop. The action of the amplifier loops impresses
the differential input voltage across the external gain set
resistor RG. Since the current that flows through RG also
flows through R1 and R2, the ratios provide a gained-up
differential voltage,
G = 1+
R1+R2
RG
to the difference amplifier A3. The difference amplifier
removes the common mode voltage and provides a single-ended output voltage referenced to the average of the
voltages on REF1 and REF2. This split reference resistor
configuration allows the output voltage to be easily level
shifted to the center of an ADCs input range without external components. The offset voltage of the difference amplifier is trimmed to minimize output offset voltage drift, thus
assuring a high level of performance, even in low gains.
Resistors R5 to R9 are trimmed to maximize CMRR and
minimize gain error. The resulting gain equation is:
⎛ 24.2k ⎞
G = 0.2 ⎜ 1+
RG ⎟⎠
⎝
Solving for the gain set resistor gives:
RG =
24.2k
5G– 1
Table 1 shows appropriate 1% resistor values for a variety of gains.
Table 1. LT6372-0.2 Gain and RG Lookup.
Resulting Gains for Various 1% Standard Resistor Values
Gain
Standard 1% Resistor Value (Ω)
0.2
–
0.399
24.3k
0.499
16.2k
0.8
8.06k
1.001
6.04k
2.013
2.67k
5.04
1k
9.9
499
20.12
243
49.79
97.6
99.58
48.7
199.4
24.3
496.1
9.76
994
4.87
Additionally, The LT6372-0.2 has two integrated output
voltage clamps which can be used to limit the voltage
Rev. 0
For more information www.analog.com
15
LT6372-0.2
APPLICATIONS INFORMATION
applied to an ADCs input. Typically, CLHI is tied to the
ADC’s reference and CLLO is tied to the ADC’s ground
connection.
Valid Input and Output Range
Instrumentation amplifiers traditionally specify a valid
input common mode range and an output swing range.
This however often fails to identify limitations associated
with internal swing limits. Referring to the Simplified Block
Diagram, the output swing of pre-amplifiers A1 and A2
as well as the common-mode input range of the difference amplifier A3 impose limitations on the valid operating
range. Figure 1 shows the operating region where a valid
output is produced for various configurations. Further
valid input and output range plots can be generated using
the Diamond Plot Tool.
VD/2
+
+15V
V+
VCM
+
–
LT6370
LT6372-0.2
REF1,2
VD/2
–
OUT
V–
637202 F01a
–15V
INPUT COMMON–MODE VOLTAGE (V)
15
G = 0.2
VS = ±15V
10 VREF2 = 0V
VREF1 = 0V
VCLHI = V+
–
5 V
CLLO = V
0
–5
–10
–15
–10 –8 –6 –4 –2 0 2 4
OUTPUT VOLTAGE (V)
6
8
10
637202 F01b
VD/2
+
+15V
V+
VCM
+
–
RG
243Ω
VD/2
LT6370
LT6372-0.2
REF1,2
–
OUT
V–
–15V
637202 F01c
INPUT COMMON-MODE VOLTAGE (V)
15
G = 20
VS = ±15V
10 VREF2 = 0V
VREF1 = 0V
VCLHI = V+
–
5 V
CLLO = V
0
–5
–10
–15
–10 –8 –6 –4 –2 0 2 4
OUTPUT VOLTAGE (V)
6
8
10
637202 F01d
Figure 1. Input Common Mode Range vs Output Voltage
16
Rev. 0
For more information www.analog.com
LT6372-0.2
APPLICATIONS INFORMATION
VD/2
+
+15V
+5V
V+
VCM
+
–
RG
243Ω
VD/2
LT6370
LT6370-0.2
–
V–
CLHI
REF1,2
OUT
CLLO
–15V
637202 F01m
INPUT COMMON-MODE VOLTAGE (V)
15
G = 20
VS = ±15V
10 VREF2 = 0V
VREF1 = 0V
VCLHI = 5V
5 VCLLO = 0V
0
–5
–10
–15
–10 –8 –6 –4 –2 0 2 4
OUTPUT VOLTAGE (V)
6
8
10
637202 F01n
VD/2
+
+5V
V+
VCM
+
–
LT6370
LT6372-0.2
REF1,2
VD/2
–
OUT
V–
–5V
637202 F01e
INPUT COMMON–MODE VOLTAGE (V)
5
G = 0.2
4 VS = ±5V
VREF2 = 0V
3
VREF1 = 0V
+
2 VCLHI = V –
VCLLO = V
1
0
–1
–2
–3
–4
–5
–5 –4 –3 –2 –1 0 1 2
OUTPUT VOLTAGE (V)
3
4
5
637202 F01f
VD/2
+
+5V
V+
VCM
+
–
RG
243Ω
VD/2
LT6370
LT6372-0.2
–
REF1,2
V–
–5V
637202 F01g
OUT
INPUT COMMON-MODE VOLTAGE (V)
5
G = 20
4 VS = ±5V
VREF2 = 0V
3
VREF1 = 0V
+
2 VCLHI = V
VCLLO = V–
1
0
–1
–2
–3
–4
–5
–5 –4 –3 –2 –1 0 1 2
OUTPUT VOLTAGE (V)
3
4
5
637202 F01h
Figure 1 (Continued). Input Common Mode Range vs Output Voltage
Rev. 0
For more information www.analog.com
17
LT6372-0.2
APPLICATIONS INFORMATION
VD/2
+
+5V
V+
VCM
+
–
REF2
LT6370
LT6372-0.2
REF1
VD/2
–
OUT
V–
637202 F01i
INPUT COMMON-MODE VOLTAGE (V)
5.0
G = 0.2
4.5 VS = 5V
V
= 5V
4.0 VREF2 = 0V
REF1
+
3.5 VCLHI = V –
VCLLO = V
3.0
2.5
2.0
1.5
1.0
0.5
0
0
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
5
637202 F01j
VD/2
+
+5V
V+
VCM
+
–
RG
243Ω
VD/2
LT6370
LT6372-0.2
–
REF2
OUT
REF1
V–
637202 F01k
INPUT COMMON-MODE VOLTAGE (V)
5.0
G = 20
4.5 VS = 5V
VREF2 = 5V
4.0
VREF1 = 0V
+
3.5 VCLHI = V
VCLLO = V–
3.0
2.5
2.0
1.5
1.0
0.5
0
0
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
5
637202 F01l
Figure 1 (Continued). Input Common Mode Range vs Output Voltage
18
Rev. 0
For more information www.analog.com
LT6372-0.2
APPLICATIONS INFORMATION
Output Level Shifting with Split Reference Pins
The LT6372-0.2’s difference amplifier features split reference pins, REF1 and REF2, which allow the output to
be easily and accurately level shifted without the use of
external circuitry. REF1 and REF2 are typically tied to an
ADC ground and reference respectively. In this configuration the amplifier’s output is conveniently level shifted to
the center of the ADC input range.
If REF1 and REF2 are shorted to each other, they can
function as the reference for the output voltage like a traditional instrumentation amplifier.
Parasitic resistance in series with REF1 and REF2 should
be minimized to preserve CMRR and gain performance. It
is also important to note that the drift in any circuitry used
to drive REF1 or REF2 can result in an additional output
drift term. Therefore, it may be important to consider the
temperature accuracy of the circuitry used to drive the
REF pin.
Gain Setting Resistor Connections
Each pre-amplifier gives a set of RG connection terminals which should be routed separately to the gain setting
resistor. Doing this minimizes the impact which parasitic
trace and lead resistance has on gain accuracy. When
routing to the gain setting resistors, large loops should
be avoided as they can couple noise into the amplifier.
In applications where clamping is not desired, CLLO
should be tied to V– and CLHI to V+ to disable clamping.
Input and Output Offset Voltage
The offset voltage of the LT6372-0.2 has two main components: the input offset voltage due to the input amplifiers and the output offset due to the output amplifier. The
total offset voltage referred to the input (RTI) is found by
dividing the output offset by the programmed gain and
adding it to the input offset voltage. At high gains the input
offset voltage dominates, whereas at low gains the output
offset voltage dominates. The total offset voltage is:
Total input offset voltage (RTI) = VOSI + VOSO/G
Total output offset voltage (RTO) = VOSI • G + VOSO
The preceding equations can also be used to calculate
offset drift in a similar manner.
Output Offset Trimming
The LT6372-0.2 is laser trimmed for low offset voltage
so that no external offset trimming is required for most
applications. In the event that the offset voltage needs
to be adjusted, the circuit in Figure 2 is an example of
an optional offset adjustment circuit. The op amp buffer
provides a low impedance signal to the REF pin in order
to achieve the best CMRR and lowest gain error.
V+ 5V
Output Clamps
CLHI and CLLO are high impedance inputs and do not
conduct significant current during clamping. Rather, internal amplifier nodes are controlled by CLHI and CLLO to
limit the output voltage.
REF2
LT6372-0.2
REF1
V+
OUTPUT
–
V–
±5mV
ADJUSTMENT
RANGE
R1
+10mV
100Ω
LTC2057
+
When the CLLO is tied to 0V, attempts to drive the output
below 0V will be clamped at –0.45V typically. When CLHI
is tied to 5V, attempts to drive the output above 5V will
be clamped at 5.45V typically.
+
–
The CLHI and CLLO clamp pins limit the output voltage
swing of the LT6372-0.2. CLHI and CLLO are typically
tied to the ADC supply/reference and ADC ground respectively. In this case the ADC input is protected from being
overdriven by the LT6372-0.2 which is likely running off
a higher supply voltage.
10k
100Ω
–10mV
R2
V
–
637202 F02
Figure 2. Optional Trimming of Output Offset Voltage
Thermocouple Effects
In order to achieve accuracy on the microvolt level, thermocouple effects must be considered. Any connection
of dissimilar metals forms a thermoelectric junction and
Rev. 0
For more information www.analog.com
19
LT6372-0.2
APPLICATIONS INFORMATION
In order to minimize thermocouple-induced errors, attention must be given to circuit board layout and component
selection. It is good practice to minimize the number of
junctions in the amplifier’s input and RG signal paths and
avoid connectors, sockets, switches, and relays whenever
possible. If such components are required, they should be
selected for low thermal EMF characteristics. Furthermore,
the number, type, and layout of junctions should be matched
for both inputs with respect to thermal gradients on the circuit board. Doing so may involve deliberately introducing
dummy junctions to offset unavoidable junctions.
Air currents can also lead to thermal gradients and cause
significant noise in measurement systems. It is important
to prevent airflow across sensitive circuits. Doing so will
often reduce thermocouple noise substantially. Placing
PCB input traces close together, and on an internal PCB
layer, can help minimize temperature differentials resulting from air currents reacting with the input trace thermal
surface area.
20
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
MICROVOLTS REFERRED TO 25°C
Connectors, switches, relay contacts, sockets, resistors,
and solder are all candidates for significant thermal EMF
generation. Even junctions of copper wire from different
manufacturers can generate thermal EMFs of 200nV/°C,
which is comparable to the maximum input offset voltage
drift specification of the LT6372-0.2. Figure 3 and Figure 4
illustrate the potential magnitude of these voltages and their
sensitivity to temperature.
25
35
30
45
40
TEMPERATURE (°C)
637202 F04
Figure 3. Thermal EMF Generated by Two Copper Wires
From Different Manufacturers
THERMALLY PRODUCED VOLTAGE IN MICROVOLTS
generates a small temperature-dependent voltage. Also
known as the Seebeck Effect, these thermal EMFs can be
the dominant error source in low-drift circuits.
100
SLOPE ≈ 1.5µV/°C
BELOW 25°C
50
0
64% SN/36% Pb
60% Cd/40% SN
SLOPE ≈ 160nV/°C
BELOW 25°C
–50
–100
10
30
0
40
50
20
SOLDER-COPPER JUNCTION DIFFERENTIAL TEMPERATURE
SOURCE: NEW ELECTRONICS 02-06-77
637202 F05
Figure 4. Solder-Copper Thermal EMFs
Rev. 0
For more information www.analog.com
LT6372-0.2
Reducing Board-Related Leakage Effects
Figure 5 and Figure 6 show the force and sense RG connections as a single RG connection for simplicity.
Leakage currents can have a significant impact on system
accuracy, particularly in high temperature and high voltage
applications. Quality insulation materials should be used,
and insulating surfaces should be cleaned to remove fluxes
and other residues. For humid environments, surface coating may be necessary to provide a moisture barrier.
For the lowest leakage, amplifiers can be used to drive the
guard ring. These buffers must have very low input bias
current since that will now be a leakage.
Leakage into the RG pin conducts through the on-chip feedback resistor, creating an error at the output of the preamplifiers. This error is independent of gain and degrades
accuracy the most at low gains. This leakage can be minimized by encircling the RG connections with a guard-ring
operated at a potential very close to that of the RG pins.
NIC pins adjacent to each RG pin can be used to simplify
the implementation of this guard-ring. These NIC pins do
not provide any bias and have no internal connections. In
some cases, the guard-ring can be connected to the input
voltage which biases one diode drop below RG.
RG
RG
637202 F07
Figure 6. Guard-Rings Can Be Used to Minimize
Leakage into the Input Pins
Input Bias Current Return Path
The low input bias current of the LT6372-0.2 (800pA max)
and high input impedance (225GΩ) allow the use of high
impedance sources without introducing additional offset
voltage errors, even when the full common mode range is
required. However, a path must be provided for the input
bias currents of both inputs when a purely differential signal
is being amplified. Without this path, the inputs will float to
either rail and exceed the input common mode range of the
LT6372-0.2, resulting in a saturated input amplifier. Figure 7
shows three examples of an input bias current path. The
first example is of a purely differential signal source with a
10kΩ input current path to ground. Since the impedance of
the signal source is low, only one resistor is needed. Two
matching resistors are needed for higher impedance signal
sources as shown in the second example. Balancing the
input impedance improves both AC and DC common mode
rejection and DC offset. The need for input resistors is eliminated if a center tap is present as shown in the third example.
+IN
+RG
LT6372-0.2
–RG
–IN
637202 F06
Figure 5. Guard-Rings Can Be Used to Minimize
Leakage into the RG Pins
Leakage into the input pins reacts with the source resistance, creating an error directly at the input. This leakage
can be minimized by encircling the input connections with
a guard-rings operated at a potential very close to that
of the input pins. In some cases, the guard-ring can be
connected to RG which biases one diode above the input.
–
THERMOCOUPLE
RG
–
LT6372-0.2
REF1,2
MICROPHONE,
HYDROPHONE,
ETC
RG
–
LT6372-0.2
+
200k
RG
LT6372-0.2
REF1,2
+
10k
+IN
+RG
LT6372-0.2
–RG
–IN
REF1,2
+
200k
CENTER-TAP PROVIDES
BIAS CURRENT RETURN
637202 F08
Figure 7. Providing an Input Common Mode Current Path
Rev. 0
For more information www.analog.com
21
LT6372-0.2
APPLICATIONS INFORMATION
Input Protection
Additional input protection can be achieved by adding
external resistors in series with each input. If low value
resistors are needed, a clamp diode from the positive
supply to each input will help improve robustness. A
2N4394 drain/source to gate is a good low leakage diode
which can be used as shown in Figure 8. Robust input
resistors should be chosen, such as carbon composite
or bulk metal foil. Metal film and carbon film should not
be used because of their poor performance.
VCC
VCC
J1
2N4393
J2
2N4393
RIN
OPTIONAL FOR HIGHEST
ESD PROTECTION
+
RG
VCC
LT6372-0.2
REF1,2
OUT
–
RIN
VEE
637202 F08
Figure 8. Input Protection
Maintaining AC CMRR
To achieve optimum AC CMRR, it is important to balance
the capacitance on the RG gain setting pins. Furthermore,
if the source resistance on each input is not equal, adding an additional resistance to one input to improve input
source resistance matching will improve AC CMRR.
RFI Reduction/Internal RFI Filter
In many industrial and data acquisition applications, the
LT6372-0.2 will be used to amplify small signals accurately in the presence of large common mode voltages or
high levels of noise. Typically, the sources of these very
small signals (on the order of microvolts or millivolts) are
sensors that can be a significant distance from the signal
conditioning circuit. Although these sensors may be connected to signal conditioning circuitry using shielded or
unshielded twisted-pair cabling, the cabling may act as
an antenna, conveying very high frequency interference
directly into the input stage of the LT6372-0.2.
22
The amplitude and frequency of the interference can have
an adverse effect on an instrumentation amplifier’s input
stage by causing any unwanted DC shift in the amplifier’s
input offset voltage. This well known effect is called RFI
rectification and is produced when out-of-band interference is coupled (inductively, capacitively or via radiation)
and rectified by the instrumentation amplifier’s input transistors. These transistors act as high frequency signal
detectors, in the same way diodes were used as RF envelope detectors in early radio designs. Regardless of the
type of interference or the method by which it is coupled
into the circuit, an out-of-band error signal appears in
series with the instrumentation amplifier’s inputs.
To help minimize this effect, the LT6372-0.2 has 50MHz
on-chip RFI filters to help attenuate high frequencies
before they can interact with its input transistors. These
on-chip filters are well matched due to their monolithic
construction, which helps minimize any degradation in
AC CMRR. To reduce the effect of these out-of-band signals on the input offset voltage of the LT6372-0.2 further,
an additional external low-pass filter can be used at the
inputs. The filter should be located very close to the input
pins of the circuit. An effective filter configuration is illustrated in Figure 9, where three capacitors have been added
to the inputs of the LT6372-0.2.
The filter limits the input signal according to the following
relationship:
FilterFreqDIFF =
FilterFreqCM =
1
2πR(2CD +CC )
1
2πRCC
where CD ≥10CC.
CD affects the difference signal. CC affects the common-mode signal. Any mismatch in R × CC degrades
the LT6372-0.2 CMRR. To avoid inadvertently reducing
CMRR-bandwidth performance, make sure that CC is at
least one magnitude smaller than CD.The effect of mismatched CCs is reduced with a larger CD:CC ratio.
Rev. 0
For more information www.analog.com
LT6372-0.2
APPLICATIONS INFORMATION
IN +
R
1.54k
CC
10n
CD
100n
IN –
R
1.54k
1. Pick R and CD to have a low pass pole at least 10x
higher than the highest signal of interest (e.g. 500Hz for
a 50Hz signal) using:
V+
+
RG
LT6372-0.2
VOUT
FilterFreqDIFF =
–
CC
10n
V–
f– 3dB ≈ 500Hz
637202 F09
EXTERNAL RFI
FILTER
Figure 9. Adding a Simple External RC Filter at the Inputs to
an Instrumentation Amplifier Is Effective in Further Reducing
Rectification of High Frequency Out-Of-Band Signals
To avoid any possibility of common mode to differential
mode signal conversion, match the common mode lowpass filter on each input to 1% or better. Here are the steps
to help determine appropriate values for the filter:
1
2πR(2CD +CC )
=
1
2πR(2CD + 0.1CD )
=
1
4.2πRCD
2. Select CC = CD/10.
If implemented this way, the common-mode pole frequency is placed about 20x higher than the differential
pole frequency. Here are the differential and commonmode low pass pole frequencies for the values shown in
Figure 9:
FilterFreqDIFF = 500Hz
FilterFreqCM = 10kHz
Rev. 0
For more information www.analog.com
23
LT6372-0.2
APPLICATIONS INFORMATION
Benefits when using LT6372-0.2 as an ADC Driver
The LT6372-0.2 incorporates several features which
enable better interface to ADCs compared to traditional
instrumentation amplifiers. Often, larger signals need
to be attenuated to match the input range of an ADC.
Additionally, a level shift is often required to center the
amplifier’s output to the ADC’s input range. Figure 10
shows the LT6372-0.2 performing both these functions
while maintaining high input impedance and providing
protective clamping to the ADC’s input.
Consider the alternative circuit in Figure 11, which shows
a traditional instrumentation amplifier with a handful of
additional components to perform the attenuation and
15V
15V
+
level shifting functions. The added resistive dividers to
attenuate the output and the ADC reference must have
excellent initial tolerance and temperature coefficient.
The operational amplifiers use to buffer the divided down
reference and amplifier output must also have precision
specifications over temperature. In order to protect the
ADC in this configuration, U1 should run off the same
supplies as the ADC. This requires that the input and output of U1 be rail-to-rail, limiting choices and likely giving
up some input range on the ADC. These additional components take up space, draw power, add noise, increase
cost and add complexity when compared to the LT63720.2 solution.
LTC6655-5
2.5V
V+
REF2
LT6372-0.2
–
REF
CLHI
VDD
CLLO
REF1
V–
GND
–15V
637202 F10
Figure 10. LT6372-0.2 Integrated ADC Driving Solution
15V
LTC6655-5
2.5V
–
15V
+
V+
LT6370
–
V–
–15V
+
4R
REF
VDD
U1
R
R
GND
+
R
U2
637202 F11
–
Figure 11. Alternative IA-ADC Interfacing Circuit
24
Rev. 0
For more information www.analog.com
LT6372-0.2
TYPICAL APPLICATIONS
Differential Output Instrumentation Amplifier
VBIAS
–
–
12pF
10k
–
–IN
OUTPUT
R1
500k
C1
0.3µF
–VS
LTC2057
–
LTC2057
–OUT
637202 TA02
f –3dB =
1
(2π)(R1)(C1)
= 1.06Hz
637202 TA03
Precision Voltage-to-Current Converter
VS
+
+IN
RX
LT6372-0.2
REF1,2
RG
VX
–
–IN
–V S
IL =
IL
LTC2057
+
–VS
LT6372-0.2
REF1,2
10k
REF1,2
–IN
RG
+OUT
LT6372-0.2
+VS
–
RG
+
+IN
+
+IN
+VS
+
+
AC Coupled Instrumentation Amplifier
VX !"(+IN)–(–IN)#$G
=
RX
RX
LOAD
% 24.2k (
G= ''
+1** • 0.2
& RG
)
637202 TA04
High Side, Bidirectional Current Sense
IL = ±2A
VBUS
VBUS > –12V
VBUS < 11V
RSENSE
0.05Ω
+
RG
499Ω
+VS
LT6372-0.2
LOAD
! 24.2k $
VOUT =IL •RSENSE • # 1+
• 0.2
RG &%
"
REF1,2
= 0.5V / A
–
637202 TA05
–VS
Rev. 0
For more information www.analog.com
25
LT6372-0.2
PACKAGE DESCRIPTION
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
1.50 REF
2.65 ±0.05
1.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ±0.05
4.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ±0.10
0.75 ±0.05
1.50 REF
19
R = 0.05 TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
20
0.40 ±0.10
1
PIN 1
TOP MARK
(NOTE 6)
4.00 ±0.10
2
2.65 ±0.10
2.50 REF
1.65 ±0.10
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
26
Rev. 0
For more information www.analog.com
LT6372-0.2
PACKAGE DESCRIPTION
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
5.10
(.201)
MIN
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
8
1
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102 3.20 – 3.45
(.065 ±.004) (.126 – .136)
0.305 ±0.038
(.0120 ±.0015)
TYP
16
0.50
(.0197)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
9
NO MEASUREMENT PURPOSE
0.280 ±0.076
(.011 ±.003)
REF
16151413121110 9
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
1234567 8
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0213 REV F
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
moreby
information
www.analog.com
27
LT6372-0.2
TYPICAL APPLICATION
Programmable Gain Amplifier with Gains of 0.5V/V, 1V/V, 2V/V and 10V/V
P3
P2
P4
P1
D4 D3 D2 D1
IN4 IN3 IN2 IN1
S4 S3 S2 S1
VSS GND VDD
ADG441
15V
BRIDGE
PROGRAMMABLE
GAIN AMPLIFIER
R9
1k
5.1V
D1
1N751
C1
0.1µF
R4
200k
15V
RF4
1.6k
R2
200k
R3
200k
R1
200k
R6
350Ω
P1
P2
P3
P4
RF4
1.6k
RF2
4.02k
R5
350Ω
RG
806Ω
SW1
GAIN
SELECT
SWITCH
15V
RF3
2k
RF3
2k
15V
V+
R7
350Ω
+RGS
+RGF
+IN
R8
350Ω
–IN
–RGF
–RGS
RF2
4.02k
LT6372-0.2
OUTPUT
REF2
V–
REF1
5.1V
2.55V NOMINAL
(0V DIFFERENTIAL INPUT)
C2
0.1µF
–15V
15V
S4 S3 S2 S1
VSS GND VDD
D4 D3 D2 D1
IN4 IN3 IN2 IN1
ADG441
P4
P1
P3
P2
637202 TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Instrumentation Amplifiers
AD8429
Low Noise Instrumentation Amplifier
VS = 36V, IS = 6.7mA, VOS = 50µV, BW = 15MHz, eni = 1nV/√Hz, eno = 45nV/√Hz
LT6372-1
Low Drift Instrumentation Amplifier
LT6372-0.2 with Min Gain = 1V/V
LT6370
Low Drift Instrumentation Amplifier
VS = 30V, IS = 2.65mA, VOS = 25µV, BW = 3.1MHz, eni = 7nV/√Hz, eno = 65nV/√Hz
LTC1100
Zero-Drift Instrumentation Amplifier
VS = 18V, IS = 2.4mA, VOS = 10μV, BW = 19kHz, 1.9µVP-P DC to 10Hz
AD8421
Low Noise Instrumentation Amplifier
VS = 36V, IS = 2mA, VOS = 25μV, BW = 10MHz, eni = 3nV/√Hz, eno = 60nV/√Hz
AD8221
Low Power Instrumentation Amplifier
VS = 36V, IS = 900μA, VOS = 25μV, BW = 825kHz, eni = 8nV/√Hz, eno = 75nV/√Hz
LT1167
Instrumentation Amplifier
VS = 36V, IS = 900μA, VOS = 40μV, BW = 1MHz, eni = 7.5nV/√Hz, eno = 67nV/√Hz
AD620
Low Power Instrumentation Amplifier
VS = 36V, IS = 900μA, VOS = 50μV, BW = 1MHz, eni = 9nV/√Hz, eno = 72nV/√Hz
LTC6800
RRIO Instrumentation Amplifier
VS = 5.5V, IS = 800μA, VOS = 100μV, BW = 200kHz, 2.5µVP-P DC to 10Hz
LTC2053
Zero-Drift Instrumentation Amplifier
VS = 11V, IS = 750μA, VOS = 10μV, BW = 200kHz, 2.5µVP-P DC to 10Hz
LT1168
Low Power Instrumentation Amplifier
VS = 36V, IS = 350μA, VOS = 40μV, BW = 400kHz, eni = 10nV/√Hz, eno = 165nV/√Hz
Operational Amplifiers
LTC2057
40V Zero Drift Op Amp
VOS = 4μV, Drift = 15nV/°C, IB = 200pA, IS = 900μA
Analog to Digital Converters
LTC2389-16
16-Bit SAR ADC
2.5Msps, 96dB SNR, 162.5mW
LTC2367-16
16-Bit SAR ADC
500ksps, 94.7dB SNR, 6.8mW
28
Rev. 0
11/20
www.analog.com
For more information www.analog.com
ANALOG DEVICES, INC. 2020
工商网监
湘ICP备2023018690号
