LTC1282
3V 140ksps 12-Bit
Sampling A/D Converter
with Reference
FEATURES
DESCRIPTION
Single Supply 3V or ±3V Operation
nn 140ksps Throughput Rate
nn 12mW (Typ) Power Dissipation
nn On-Chip 25ppm/°C Reference
nn Internal Synchronized Clock; No Clock Required
nn High Impedance Analog Input
nn 69dB S/(N + D) and 77dB THD at Nyquist
nn ±0.5LSB INL and ±0.75LSB DNL Max (A Grade)
nn 2.7V Guaranteed Minimum Supply Voltage
nn ESD Protected On All Pins
nn 24-Pin SW Package
nn 0V to 2.5V or ±1.25V Input Ranges
The LTC®1282 is a 6µs, 140ksps, sampling 12-bit A/D
converter that draws only 12mW from a single 3V or dual
±3V supply. This easy-to-use device comes complete with
1.14µs sample-and-hold, precision reference and internally trimmed clock. Unipolar and bipolar conversion
modes provide flexibility for various applications. They are
built with LTBiCMOSTM switched capacitor technology.
nn
The LTC1282 has a 25ppm/°C (max) internal reference
and converts 0V to 2.5V unipolar inputs from a single
3V supply. With ±3V supplies its input range is ±1.25V
with two’s complement output format. Maximum DC
specifications include ±0.5LSB INL, ±0.75LSB DNL and
25ppm/°C full-scale drift over temperature. Outstanding
AC performance includes 69dB S/(N + D) and 77dB THD
at the Nyquist input frequency of 70kHz.
APPLICATIONS
3V Powered Systems
High Speed Data Acquisition
nn Digital Signal Processing
nn Multiplexed Data Acquisition Systems
nn Audio and Telecom Processing
nn Spectrum Analysis
nn
The internal clock is trimmed for 6µs maximum conversion time. The clock automatically synchronizes to each
sample command eliminating problems with asynchronous clock noise found in competitive devices. A high
speed parallel interface eases connections to FIFOs, DSPs
and microprocessors.
nn
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
Single 3V Supply, 140ksps, 12-Bit Sampling A/D Converter
10µF
+
3V
24
23
22
21
19
10µF
µP CONTROL
LINES
18
17
16
15
14
13
74
12
0.1µF
11
68
10
62
NYQUIST
FREQUENCY
9
8
7
6
5
4
56
50
S/(N + D) (dB)
20
+
ENOBs (EFFECTIVE NUMBER OF BITS)
1.20V
VREF
OUTPUT
LTC1282
ANALOG INPUT 1 A
VDD
(0V TO 2.5V) 2 IN
VREF
VSS
3
AGND
BUSY
0.1µF
4
D11(MSB) CS
5
D10
RD
6
D9
HBEN
7
D8
NC
8
D7
NC
9
D6
D0/8
10
8- OR 12-BIT
D5
D1/9
PARALLEL BUS
11
D4
D2/10
12
DGND
D3/11
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
3
2
1
0
fSAMPLE = 140kHz
1k
10k
INPUT FREQUENCY (Hz)
100k
LTC1282 • TA02
1282 TA01
Rev. B
Document Feedback
For more information www.analog.com
1
LTC1282
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1 and 2)
TOP VIEW
Supply Voltage (VDD).................................................12V
Negative Supply Voltage (VSS)...................... –6V to GND
Total Supply Voltage (VDD to VSS).............................12V
Analog Input Voltage
(Note 3)............................... VSS – 0.3V to VDD + 0.3V
Digital Input Voltage (Note 4)...............VSS – 0.3V to 12V
Digital Output Voltage
(Note 3)............................... VSS – 0.3V to VDD + 0.3V
Power Dissipation............................................... 500mW
Specified Temperature Range (Note 14)........ 0°C to 70°C
Operating Temperature Range
LTC1282AC, LTC1282BC........................... 0°C to 70°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
AIN
1
24 VDD
VREF
2
23 VSS
AGND
3
22 BUSY
D11(MSB)
4
21 CS
D10
5
20 RD
D9
6
19 HBEN
D8
7
18 NC
D7
8
17 NC
D6
9
16 D0/8
D5 10
15 D1/9
D4 11
14 D2/10
DGND 12
13 D3/11
SW PACKAGE
24-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 130°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1282ACSW#PBF
LTC1282ACSW#TRPBF
LTC1282ACSW
24-Lead Plastic SO Wide
0°C to 70°C
LTC1282BCSW#PBF
LTC1282BCSW#TRPBF
LTC1282BCSW
24-Lead Plastic SO Wide
0°C to 70°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
CONVERTER
CHARACTERISTICS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5 and 6)
LTC1282A
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
l
TYP
LTC1282B
MAX
12
MIN
TYP
MAX
12
UNITS
Bits
±1/2
±1/2
±3/4
±1
±1
±1
LSB
LSB
LSB
Integral Linearity Error
(Note 7)
Commercial
Military
l
l
Differential Linearity Error
Commercial
Military
l
l
±3/4
±1
±1
±1
LSB
LSB
Offset Error
(Note 8)
l
±3
±4
±4
±6
LSB
LSB
±10
±15
LSB
±45
ppm/°C
Gain Error
Gain Error Tempco
IOUT(REF) = 0
Power Supply Rejection
(Note 9) VDD ±10%
(Note 10) VSS ±10%
l
±5
±0.3
±0.1
±25
±10
±0.3
±0.1
LSB
LSB
Rev. B
2
For more information www.analog.com
LTC1282
DYNAMIC ACCURACY
(Note 5)
LTC1282A/LTC1282B
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
S/(N + D)
Signal-to-Noise Plus Distortion Ratio
10kHz/70kHz Input Signal
71/69
dB
THD
Total Harmonic Distortion
10kHz/70kHz Input Signal, Up to 5th Harmonic
–82/–77
dB
Peak Harmonic or Spurious Noise
10kHz/70kHz Input Signal
–82/–77
dB
IMD
Intermodulation Distortion
fIN1 = 19.0kHz, fIN2 = 20.6kHz
–78
dB
Full Power Bandwidth
Full Linear Bandwidth (S/(N + D) ≥ 68dB)
ANALOG INPUT
MAX
UNITS
4
MHz
200
kHz
(Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
VIN
Analog Input Range (Note 11)
2.7V ≤ VDD ≤ 3.6V (Unipolar Mode)
3V ≤ VDD ≤ 3.6V, –3.3V ≤ VSS ≤ –2.5V (Bipolar Mode)
IIN
Analog Input Leakage Current
CS = High
CIN
Analog Input Capacitance
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
tACQ
Sample-and-Hold
Acquisition Time
Commercial
Military
TYP
MAX
UNITS
0 to 2.5
±1.25
V
V
±1
l
µA
63
5
0.45
l
l
pF
pF
1.14
1.5
µs
µs
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
IOUT = 0
VREF Line Regulation
2.7V ≤ VDD ≤ 3.6V
0.55
0.55
LSB/V
–3.6V ≤ VSS ≤ –2.7V
0.02
0.02
LSB/V
3
3
VREF Load Regulation
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
1.1900
1.200
1.210
1.190
1.200
1.210
V
±5
±25
±10
±45
l
0V ≤ |IOUT| ≤ 1mA
ppm/°C
LSB/mA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 3.6V
l
VIL
Low Level Input Voltage
VDD = 2.7V
l
0.45
V
IIN
Digital Input Current
VIN = 0V to VDD
l
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
MIN
VDD = 2.7V
IO = –10µA
IO = –200µA
l
VDD = 2.7V
IO = 160µA
IO = 1.6mA
l
TYP
MAX
1.9
2.3
UNITS
V
5
pF
2.6
V
V
0.05
0.10
0.4
V
V
IOZ
High Z Output Leakage D11-D0/8
VOUT = 0V to VDD, CS High
l
±10
µA
COZ
High Z Output Capacitance D11-D0/8
CS High (Note 12 )
l
15
pF
ISOURCE
Output Source Current
VOUT = 0V
–4.5
mA
ISINK
Output Sink Current
VOUT = VDD
4.5
mA
Rev. B
For more information www.analog.com
3
LTC1282
POWER
REQUIREMENTS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
VDD
Positive Supply Voltage
Unipolar Mode (Note 13)
Bipolar Mode (Note 13)
2.7
3.0
TYP
MAX
3.6
3.6
UNITS
V
V
VSS
Negative Supply Voltage
Bipolar Operation (Note 13)
–3.6
–2.5
V
IDD
Positive Supply Current
fSAMPLE = 140ksps
l
4
7.8
mA
ISS
Negative Supply Current
fSAMPLE = 140ksps
l
0.03
0.15
mA
PD
Power Dissipation
fSAMPLE = 140ksps
l
12
24
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 1 and 5)
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE(MAX) Maximum Sampling Frequency
tCONV
Conversion Time
Commercial
Military
t1
CS to RD Setup Time
t2
RD↓ to BUSY↓ Delay
t3
Data Access Time After RD↓
MIN
Commercial (Note 13)
Military (Note 13)
l
l
TYP
140
120
l
l
l
CL = 20pF (Note 13)
Commercial
Military
l
l
CL = 100pF (Note 13)
Commercial
Military
l
l
UNITS
kHz
kHz
6.0
6.5
l
l
CL = 50pF
Commercial
Military
MAX
0
µs
µs
ns
140
200
230
260
ns
ns
ns
100
180
200
220
ns
ns
ns
110
200
240
260
ns
ns
ns
t4
RD Pulse Width
(Note 13)
l
t3
ns
t5
CS to RD Hold Time
(Note 13)
l
0
ns
t6
Data Setup Time After BUSY↑
(Note 13)
Commercial
Military
l
l
(Note 13)
Commercial
Military
l
l
40
40
40
t7
Bus Relinquish Time
60
85
110
120
ns
ns
ns
60
120
130
150
ns
ns
ns
t8
HBEN to RD Setup Time
(Note 13)
l
0
ns
t9
HBEN to RD Hold Time
(Note 13)
l
0
ns
t10
Delay Between RD Operations
t11
Delay Between Conversions
t12
Aperture Delay of Sample-and-Hold
Commercial (Note 13)
Military (Note 13)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 60mA below VSS or above VDD without latchup.
l
40
l
l
1140
1500
ns
450
ns
ns
30
ns
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
60mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 3V, VSS = 0V for unipolar mode and VSS = –3V for bipolar
mode, fSAMPLE = 140kHz, tr = tf = 5ns unless otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Rev. B
4
For more information www.analog.com
LTC1282
TIMING CHARACTERISTICS
(Note 5)
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the different voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Full-scale change when VSS = 0V (Unipolar Mode) or –3V
(Bipolar Mode).
Note 10: Full-scale change when VDD = 3V.
Note 11: The LTC1282 can perform unipolar and bipolar conversions.
When VSS is grounded (i.e. –0.1V ≤ VSS), the ADC will convert in unipolar
mode with input voltage of 0V to 2.5V. When VSS is taken negative (i.e.
VSS ≤ –2.5V), the ADC will convert in bipolar mode with an input voltage of
±1.25V. AIN must not exceed VDD or fall below VSS by more than 50mV for
specified accuracy.
Note 12: Guaranteed by design, not subject to test.
Note 13: Recommended operating conditions.
Note 14: Commercial grade parts are designed to operate over the
temperature range of –40°C to 85°C but are neither tested nor guaranteed
beyond 0°C to 70°C. Industrial grade parts specified and tested over
–40°C to 85°C are available on special request. Consult factory.
Slow Memory Mode, Parallel Read Timing Diagram
ROM Mode, Parallel Read Timing Diagram
CS
CS
t1
t5
t2
BUSY
t3
TRACK
t6
OLD DATA
DB11 TO DB0
DATA
t11
tCONV
t10
t2
BUSY
t7
t3
NEW DATA
DB11 TO DB0
HOLD
LTC1282 • TC01
t1
t11
tCONV
t7
t4
t2
t3
OLD DATA
DB11 TO DB0
DATA
t12
t5
t4
RD
RD
HOLD
t1
t1
t12
TRACK
t5
tCONV
t7
NEW DATA
DB11 TO DB0
t12
LTC1282 • TC02
Rev. B
For more information www.analog.com
5
LTC1282
TIMING CHARACTERISTICS
Slow Memory Mode, Two Byte Read Timing Diagram
HBEN
t8
t9
t8
t9
CS
t1
t5
t1
RD
t10
t2
tCONV
BUSY
t3
t6
OLD DATA
DB7 TO DB0
DATA
t5
t4
t10
t11
t3
t7
NEW DATA
DB7 TO DB0
t7
NEW DATA
DB11 TO DB8
t12
HOLD
t12
TRACK
LTC1282 • TC03
ROM Mode, Two Byte Read Timing Diagram
HBEN
t8
t9
t9
t8
t9
t8
CS
t1
t4
RD
t5
t2
HOLD
t7
OLD DATA
DB7 TO DB0
DATA
t4
t5
t3
t1
t10
t11
tCONV
BUSY
t3
t1
t7
t4
t2
t3
NEW DATA
DB11 TO DB8
t12
t5
t7
NEW DATA
DB7 TO DB0
t12
LTC1282 • TC04
TRACK
Rev. B
6
For more information www.analog.com
LTC1282
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
0.5
0
–0.5
10
1
8
0.5
0
–0.5
512 1024 1536 2048 2560 3072 3584 4096
CODE
–1
0
EFFECTIVE NUMBER OF BITS (ENOBs)
SUPPLY CURRENT (mA)
SINGLE
SUPPLY
10
DUAL
SUPPLIES
6
4
2
3
4
4.5
3.5
SUPPLY VOLTAGE (V)
5
10
UNIPOLAR
(0V – 2.5V INPUT)
9
5
4
3
1
0
fSAMPLE = 160kHz
VS = ±2.7V BIPOLAR
VS = 3V UNIPOLAR
10k
100k
1M
INPUT FREQUENCY (Hz)
1k
–60
–70
–100
3rd HARMONIC
2nd HARMONIC
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
–20
–30
–40
–50
THD
–60
3rd HARMONIC
–70
2nd HARMONIC
–80
–90
–100
10M
LTC1282 • TPC07
10k
100k
1M
INPUT FREQUENCY (Hz)
1k
Intermodulation Distortion Plot
0
fSAMPLE = 140kHz
VDD (VRIPPLE = 2.5mV)
VSS (VRIPPLE = 2.5mV)
DGND (VRIPPLE = 250mV)
–10
–20
–30
10M
LTC1282 • TPC06
fSAMPLE = 160kHz
fIN1 = 19.0kHz
fIN2 = 20.6kHz
VDD = 3V
UNIPOLAR
–20
AMPLITUDE (dB)
–50
THD
10M
fSAMPLE = 160kHz
3V SUPPLY
UNIPOLAR
–10
LTC1282 • TPC05
AMPLITUDE OF
POWER SUPPLY FEEDTHROUGH (dB)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
–40
–80
56
7
6
0
–30
–90
62
0
Power Supply Feedthrough
vs Ripple Frequency
fSAMPLE = 140kHz
±3V SUPPLIES
BIPOLAR
–20
68
50
Distortion vs Input Frequency
(Bipolar)
–10
BIPOLAR
(±1.25V
INPUT)
8
2
125
100
Distortion vs Input Frequency
(Unipolar)
74
11
LTC1282 • TPC04
0
50
25
0
75
TEMPERATURE (°C)
LTC1282 • TPC03
S/(N + D) (dB)
14
0
2.5
3
0
–50 –25
512 1024 1536 2048 2560 3072 3584 4096
CODE
12
16
8
4
ENOBs and S/(N + D)
vs Input Frequency
fSAMPLE = 160kHz
TA = 25°C
12
5
LTC1282 • TPC02
Supply Current (IDD)
vs Supply Voltage
18
6
1
LTC1282 • TPC01
20
7
2
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
fSAMPLE = 160kHz
VDD = 3V
9
SUPPLY CURRENT (mA)
DIFFERENTIAL NONLINEARITY ERROR (LSBs)
INTEGRAL NONLINEARITY ERROR (LSBs)
1
–1
Supply Current (IDD) vs
Temperature
Differential Nonlinearity
–40
–50
–60
–70
–80
–40
–60
–80
–100
–90
–100
1k
10k
100k
RIPPLE FREQUENCY (Hz)
1M
LTC1282 • TPC08
–120
0
10k
20k 30k 40k 50k 60k 70k
FREQUENCY (Hz)
80k
LTC1282 • TPC09
Rev. B
For more information www.analog.com
7
LTC1282
TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency and
Amplitude (Unipolar, VDD = 3V)
60
VIN = –20dB
50
40
30
20
VIN = –60dB
10
0
10k
100k
1M
INPUT FREQUENCY (Hz)
1k
70
VIN = –20dB
50
40
30
20
VIN = –60dB
10k
100k
1M
INPUT FREQUENCY (Hz)
1k
SIGNAL/(NOISE + DISTORTION) (dB)
1.200
1.195
1.190
1.185
1.180
1.175
–2
–1
–3
LOAD CURRENT (mA)
0
70
RS = 1k
RS = 5k
50
40
30
20
VDD = 3V
VSS = –3V
BIPOLAR
10
0
1
RS = 500Ω
60
5
10k
100k
1M
INPUT FREQUENCY (Hz)
1k
10M
3
2
1
100
125
LTC1282 • TPC16
0.4
fSAMPLE = 140kHz
VDD = 2.7V
0.3
0.2
0.1
0
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
1M
5
4
fSAMPLE = 140kHz
VDD = 2.7V
3
2
1
0
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
LTC1282 • TPC15
Change in Differential Nonlinearity
(DNL) vs Temperature
0.5
fSAMPLE = 140kHz
VDD = 2.7V
1k
10k
100k
INPUT FREQUENCY (Hz)
LTC1282 • TPC12
Change in Integral Nonlinearity
(INL) vs Temperature
MAGNITUDE OF
INTEGRAL NONLINEARITY CHANGE (LSBs)
MAGNITUDE OF GAIN ERROR CHANGE (LSBs)
–100
100
LTC1282 • TPC14
Change in Gain Error
vs Temperature
50
25
0
75
TEMPERATURE (°C)
–70
Change in Offset Voltage
vs Temperature
RS = 50Ω
LTC1282 • TPC13
0
–50 –25
–60
MAGNITUDE OF
DIFFERENTIAL NONLINEARITY CHANGE (LSBs)
REFERENCE VOLTAGE (V)
1.205
–4
–50
S/(N +D) vs Input Frequency vs
Source Resistance (Bipolar)
1.210
4
10M
80
–5
–40
LTC1282 • TPC10
1.220
1.215
–30
–90
Reference Voltage
vs Load Current
VDD = 3V
fSAMPLE = 160kHz
VDD = 3V
UNIPOLAR
–80
10
LTC1282 • TPC10
1.170
–10
–20
60
0
10M
0
fSAMPLE = 160kHz
VIN = 0dB
AMPLITUDE (dB)
70
80
fSAMPLE = 160kHz
UNIPOLAR
Spurious Free Dynamic Range
vs Input Frequency
MAGNITUDE OF OFFSET VOLTAGE CHANGE (LSBs)
VIN = 0dB
SIGNAL/(NOISE + DISTORTION) (dB)
SIGNAL/(NOISE + DISTORTION) (dB)
80
S/(N + D) vs Input Frequency and
Amplitude (Bipolar, ± 3V Supplies)
125
LTC1282 • TPC17
0.5
0.4
fSAMPLE = 140kHz
VDD = 2.7V
0.3
0.2
0.1
0
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
LTC1282 • TPC18
Rev. B
8
For more information www.analog.com
LTC1282
Change in Offset Voltage
vs Supply Voltage
1
Change in Gain Error
vs Supply Voltage
MAGNITUDE OF GAIN ERROR CHANGE (LSBs)
MAGNITUDE OF OFFSET VOLTAGE CHANGE (LSBs)
TYPICAL PERFORMANCE CHARACTERISTICS
fSAMPLE = 140kHz
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2
2.5
3.5
4
3
SUPPLY VOLTAGE (V)
4.5
5
5
fSAMPLE = 140kHz
4
3
2
1
0
2
2.5
3
3.5
4
SUPPLY VOLTAGE (V)
Change in Integral Nonlinearity
(INL) vs Supply Current
Change in Differential Nonlinearity
(DNL) vs Supply Current
MAGNITUDE OF
DIFFERENTIAL NONLINEARITY CHANGE (LSBs)
MAGNITUDE OF
INTEGRAL NONLINEARITY CHANGE (LSBs)
0.5
fSAMPLE = 140kHz
0.4
0.3
0.2
0.1
2
2.5
3
3.5
4
SUPPLY VOLTAGE (V)
4.5
5
LTC1282 • TPC20
LTC1282 • TPC19
0
4.5
5
0.5
fSAMPLE = 140kHz
0.4
0.3
0.2
0.1
0
2
LTC1282 • TPC21
2.5
3
3.5
4
SUPPLY VOLTAGE (V)
4.5
5
LTC1282 • TPC22
Rev. B
For more information www.analog.com
9
LTC1282
PIN FUNCTIONS
AIN (Pin 1): Analog Input. 0V to 2.5V (Unipolar), ±1.25V
(Bipolar).
VREF (Pin 2): +1.20V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
AGND (Pin 3): Analog Ground.
D11-D4 (Pins 4 to 11): Three-State Data Outputs. D11 is
the Most Significant Bit.
DGND (Pin 12): Digital Ground.
D3/11-D0/8 (Pins 13 to 16): Three-State Data Outputs.
NC (Pins 17 and 18): No Connection.
HBEN (Pin 19): High Byte Enable Input. This pin is used
to multiplex the internal 12-bit conversion result into the
lower bit outputs (D7 and D0/8). See Table 1. HBEN also
disables conversion start when HIGH.
RD (Pin 20): READ Input. This active low signal starts a
conversion when CS and HBEN are low. RD also enables
the output drivers when CS is low.
CS (Pin 21): The CHIP SELECT Input must be low for the
ADC to recognize RD and HBEN inputs.
BUSY (Pin 22): The BUSY Output shows the converter
status. It is low when a conversion is in progress.
VSS (Pin 23): Bipolar Mode — Negative Supply, –3V.
Bypass to AGND with 0.1µF ceramic.
Unipolar Mode — Tie to DGND.
VDD (Pin 24): Positive Supply, 3V. Bypass to AGND (10µF
tantalum in parallel with 0.1µF ceramic).
Table 1. Data Bus Output, CS and RD = LOW
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Pin 11
Pin 13
Pin 14
Pin 15
Pin 16
MNEMONIC*
D11
D10
D9
D8
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
HBEN = LOW
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
HBEN = HIGH
DB11
DB10
DB9
DB8
LOW
LOW
LOW
LOW
DB11
DB10
DB9
DB8
* D11...D0/8 are the ADC data output pins.
DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
TEST CIRCUITS
Load Circuits for Output Float Delay
Load Circuits for Access Time
5V
5V
3k
DBN
3k
DBN
DBN
3k
CL
DGND
(A) Hi-Z TO VOH, (t3)
AND VOL TO VOH, (t 6)
CL
DBN
3k
10pF
DGND
DGND
(B) Hi-Z TO VOL, (t3)
AND VOH TO VOL, (t 6)
1282 TC01
(A) VOH TO Hi-Z
10pF
DGND
(B) VOL TO Hi-Z
1282 TC02
Rev. B
10
For more information www.analog.com
LTC1282
FUNCTIONAL BLOCK DIAGRAM
SAMPLE
AIN
SAMPLE
COMPARATOR
–
HOLD
+
12
12-BIT
CAPACITIVE
DAC
VREF(OUT)
VSS (–3V FOR BIPOLAR MODE,
AGND FOR UNIPOLAR MODE)
VDD
CSAMPLE
SUCCESSIVE
APPROXIMATION
REGISTER
12
D11
OUTPUT
LATCHES
•
•
•
D0/8
BUSY
1.2V
REFERENCE
AGND
DGND
INTERNAL
CLOCK
CS
RD
HBEN
CONTROL
LOGIC
LTC1282 • FBD
APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1282 uses a successive approximation and an
internal sample-and-hold circuitry to convert an analog
signal to a 12-bit parallel or 2-byte output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microprocessors and DSPs. Please refer to the Digital Interface section
for the data format.
Conversion start is controlled by the CS, RD and HBEN
inputs. At the start of conversion the successive approximation register (SAR) is reset and the three-state data
outputs are enabled. Once a conversion cycle has begun
it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capacitor during the sample phase, and the comparator
offset is nulled by the feedback switch. In this sample
phase, a minimum delay of 1.14µs will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
compare mode. The input switch switches CSAMPLE to
ground, injecting the analog input charge to the summing
junction. This input charge is successively compared with
the binary-weighted charges supplied by the capacitive
DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the
AIN input charge. The SAR contents (a 12-bit data word)
which represent the AIN are loaded into the 12-bit latch.
SAMPLE
SAMPLE
SI
CSAMPLE
–
AIN
HOLD
+
CDAC
DAC
COMPARATOR
VDAC
S
A
R
LTC1282 • F01
12-BIT
LATCH
Figure 1. AIN Input
Rev. B
For more information www.analog.com
11
LTC1282
APPLICATIONS INFORMATION
EFFECTIVE NUMBER OF BITS (ENOBs)
The LTC1282 has exceptionally high speed sampling
capability. FFT (Fast Fourier Transform) test techniques
are used to characterize the ADC’s frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADC’s spectral content can
be examined for frequencies outside the fundamental.
Figure 2 shows a typical LTC1282 FFT plot.
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical LTC1282 FFT plot.
fSAMPLE = 160kHz
VDD = 3V
UNIPOLAR
AMPLITUDE (dB)
–20
10
9
10
20
30 40 50 60
FREQUENCY (kHz)
70
56
50
8
7
6
5
4
3
2
1
0
fSAMPLE = 160kHz
VS = ±2.7V BIPOLAR
10k
100k
1M
INPUT FREQUENCY (Hz)
1k
10M
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the
frequency band between DC and half the sampling frequency. THD is expressed as:
THD = 20 log
V22 + V32 + V42 … + VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. The typical THD specification
in the Dynamic Accuracy table includes the 2nd through
5th harmonics. With a 70kHz input signal, the LTC1282
has a typical – 82dB THD as shown in Figure 4.
–100
0
62
Figure 3. ENOBs and S/(N + D) vs Input Frequency
–80
–120
68
LTC1282 • F03
–40
–60
BIPOLAR
(±1.25V
INPUT)
11
Signal-to-(Noise + Distortion) Ratio
0
74
12
S/(N + D) (dB)
DYNAMIC PERFORMANCE
80
Figure 2. LTC1282 Nonaveraged, 1024 Point FFT Plot
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement
of the resolution of an ADC and is directly related to
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 140kHz the LTC1282 maintains 11.3 ENOBs at
70kHz input frequency. Refer to Figure 3.
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
LT1282 • F02
0
fSAMPLE = 140kHz
±3V SUPPLIES
BIPOLAR
–10
–20
–30
–40
–50
–60
–70
–80
THD
–90
–100
3rd HARMONIC
2nd HARMONIC
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
10M
LTC1282 • F04
Figure 4. Distortion vs Input Frequency (Bipolar)
Rev. B
12
For more information www.analog.com
LTC1282
APPLICATIONS INFORMATION
Intermodulation Distortion
Full Power and Full Linear Bandwidth
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full-scale input signal.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb)
and (fa – fb) while the 3rd order IMD terms include (2fa
+ fb), (2fa – fb), (fa + 2fb), and (fa – 2fb) if the two input
sine waves are equal in magnitude, the value (in decibels)
of the 2nd order. IMD products can be expressed by the
following formula:
IMD (fa ± fb) = 20log
Amplitude at (fa ± fb)
Amplitude at fa
Figure 5 shows the IMD performance at a 20kHz input.
0
fSAMPLE = 160kHz
fIN1 = 19.0kHz
fIN2 = 20.6kHz
VDD = 3V
UNIPOLAR
AMPLITUDE (dB)
–20
–40
Driving the Analog Input
The analog input of the LTC1282 is easy to drive. It draws
only one small current spike while charging the sampleand-hold capacitor at the end of conversion. During
conversion the analog input draws no current. The only
requirement is that the amplifier driving the analog input
must settle after the small current spike before the next
conversion starts. Any op amp that settles in 1.14µs to
small current transients will allow maximum speed operation. If slower op amps are used, more settling time can
be provided by increasing the time between conversions.
Suitable devices capable of driving the ADC’s AIN input
®
include the LT 1190/LT1191, LT1007, LT1220, LT1223
and LT1224 op amps.
The analog input tolerates source resistance very well.
Here again, the only requirement is that the analog input
must settle before the next conversion starts. For larger
source resistance, full accuracy can be obtained if more
time is allowed between conversions.
–60
–80
–100
–120
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1282 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency.
Internal Reference
0
10
20
30 40 50 60
FREQUENCY (kHz)
70
80
LTC1282 • F05
Figure 5. Intermodulation Distortion Plot
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value
of a full-scale input signal.
The LTC1282 has an on-chip, temperature compensated,
curvature corrected, bandgap reference which is factory
trimmed to 1.20V. It is internally connected to the DAC
and is available at pin 2 to provide up to 0.3mA current
to an external load.
For minimum code transition noise the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (10µF tantalum in parallel with
a 0.1µF ceramic).
Rev. B
For more information www.analog.com
13
LTC1282
APPLICATIONS INFORMATION
The VREF pin can be driven above its normal value with
a DAC or other means to provide input span adjustment.
Figure 6 shows an LT1006 op amp driving the reference
pin. The VREF pin must be driven to at least 1.25V to
prevent conflict with the internal reference. The reference
should be driven to no more than 1.44V in unipolar mode
or 2.88V for bipolar mode to keep the input span within
the single 3V or ± 3V supplies.
INPUT RANGE
±1.033VREF(OUT)
AIN
VDD
3V
0.61mV. Figure 9 shows the input/output transfer characteristics for the LTC1282 in bipolar operation. The full
scale for LTC1282 in bipolar mode is still 2.5V and 1LSB
= 0.61mV.
FS = 2.5V
1LSB = FS/4096
111...111
111...110
111...101
OUTPUT CODE
Overdriving the Internal Reference
111...100
UNIPOLAR
ZERO
000...011
+
LT1006
VREF(OUT) ≥ 1.25V
–
LTC1282
000...010
VREF
000...001
000...000
3Ω
10µF
AGND VSS
–3V
0V
1
LSB
FS – 1LSB
INPUT VOLTAGE (V)
LTC1282 • F06
Figure 8. LTC1282 Unipolar Transfer Characteristic
Figure 7 shows a typical reference, the LT1019A-2.5 connected to the LTC1282 operating in bipolar mode. This
will provide an improved drift (due to the 5ppm/°C of the
LT1019A-2.5) and a ±2.604V full scale.
5V
3V
LTC1282
VIN
VOUT
LT1019A-2.5
GND
VDD
AIN
000...001
000...000
111...111
111...110
100...010
FS = 2.5V
1LSB = FS/4096
100...000
3Ω
10µF
BIPOLAR
ZERO
011...110
100...001
VREF
+
011...111
OUTPUT CODE
Figure 6. Driving the VREF with the LT1006 Op Amp
INPUT RANGE
±2.60V
–FS/2
AGND VSS
LTC1282 • F08
–3V
LTC1282 • F07
Figure 7. Supplying a 2.5V Reference Voltage
to the LTC1282 with the LT1019A-2.5
UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT
Figure 8 shows the ideal input/output characteristics
for the LTC1282. The code transitions occur midway
between successive integer LSB values (i.e., 0.5LSB,
1.5LSBs, 2.5LSBs, FS – 1.5LSBs). The output code
is natural binary with 1LSB = FS/4096 = 2.5V/4096 =
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
LTC1282 • F09
Figure 9. LTC1282 Bipolar Transfer Characteristic
Unipolar Offset and Full-Scale Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero.
Figure 10 shows the extra components required for
full-scale error adjustment. If both offset and full-scale
adjustments are needed, the circuit in Figure 11 can be
used. Offset should be adjusted before full scale. To
adjust offset, apply 0.305mV (i.e., 0.5LSB) at V1 and
Rev. B
14
For more information www.analog.com
LTC1282
APPLICATIONS INFORMATION
adjust the op amp offset voltage until the LTC1282 output code flickers between 0000 0000 0000 and 0000
0000 0001. For zero full-scale error, apply an analog
input of 2.49909V (i.e., FS – 1.5LSBs or last code transition) at the input and adjust the full-scale trim until the
LTC1282 output code flickers between 1111 1111 1110
and 1111 1111 1111.
R1
50Ω
V1
–
R2
10k
R5
10k
R4
100Ω
AGND
LTC1282 • F10
Figure 10. Full-Scale Adjust Circuit
5V
R1
10k
+
R2
10k
R9
20Ω
AIN
–
R4
100k
R5
4.3k
FULL-SCALE
ADJUST
R3
100k R7
100k
R6
400Ω
AIN
–
R4
100k
R3
100k R7
100k
R6
200Ω
LTC1282
FULL-SCALE
ADJUST
+
R2
10k
R5
4.3k
FULL-SCALE
ADJUST
AIN
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
10k
R1
10k
+
A1
ANALOG
INPUT
0V TO 2.5V
ANALOG
INPUT
1.25V
LTC1282
5V
R8
10k
OFFSET
ADJUST
LTC1282 • F11
Figure 11. Unipolar Offset and Full-Scale Adjust Circuit
Bipolar Offset and Full-Scale Adjustment
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Figure 10 shows the extra
components required for full-scale error adjustment. If
both offset and full-scale adjustments are needed, the
circuit in Figure 12 can be used. Again, bipolar offset
must be adjusted before full-scale error. Bipolar offset
error adjustment is achieved by trimming the offset
LTC1282
5V
R8
20k
OFFSET
ADJUST
LTC1282 • F12
–5V
Figure 12. Bipolar Offset and Full-Scale Adjust Circuit
adjustment of Figure 12 while the input voltage is 0.5LSB
below ground. This is done by applying an input voltage of – 0.305mV (–0.5LSB for LTC1282) to the input
in Figure 12 and adjusting R8 until the ADC output code
flickers between 0000 0000 0000 and 1111 1111 1111.
For full-scale adjustment, an input voltage of 1.24909V
(FS – 1.5LSBs for LTC1282) is applied to the input and
R5 is adjusted until the output code flickers between 0111
1111 1110 and 0111 1111 1111.
BOARD LAYOUT AND BYPASSING
The LTC1282 is easy to use. To obtain the best performance from the device, a printed circuit board is recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated
as much as possible. In particular, care should be taken
not to run any digital track alongside an analog signal
track or underneath the ADC. The analog input should be
screened by AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in
Figure 13. In bipolar mode, a 0.1µF ceramic provides
adequate bypassing for the VSS pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Rev. B
For more information www.analog.com
15
LTC1282
APPLICATIONS INFORMATION
1
ANALOG
INPUT
CIRCUITRY
+
–
DIGITAL
SYSTEM
LTC1282
AIN
AGND
3
2
10µF
DGND
VDD
VREF
24
0.1µF
10µF
12
0.1µF
ANALOG GROUND PLANE
GROUND CONNECTION
TO DIGITAL CIRCUITRY
LTC1282 • F13
Figure 13. Power Supply Grounding Practice
Noise: Input signal leads to AIN and signal return leads
from AGND (Pin 3) should be kept as short as possible to
minimize input noise coupling. In applications where this
is not possible, a shielded cable between source and ADC
is recommended. Also, since any potential difference in
grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedances as much as possible.
DIGITAL INTERFACE
A single point analog ground separate from the logic
system ground should be established with an analog
ground plane at pin 3 (AGND) or as close as possible to
the ADC, as shown in Figure 13. Pin 12 ( DGND) and all
other analog grounds should be connected to this single
analog ground point. No other digital grounds should
be connected to this analog ground point. Low impedance analog and digital power supply common returns
are essential to low noise operation of the ADC and the
foil width for these tracks should be as wide as possible.
The LTC1282 interfaces well to 5V logic because the
ESD clamps on the inputs do not clamp to the positive
supply (see Figure 14). Inputs of 0V to 5V do not bother
the ADC at all. In addition, the 0V to 3V outputs of the 3V
ADC are more than adequate to meet TTL input levels in
the 5V logic. (5V logic with CMOS input levels requires
a level shift.)
In applications where the ADC data outputs and control
signals are connected to a continuously active microprocessor bus, it is possible to get errors in conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or
by using three-state buffers to isolate the ADC data bus.
The ADC is designed to interface with microprocessors as
a memory mapped device. The CS and RD control inputs
are common to all peripheral memory interfacing. The
HBEN input serves as a data byte select for 8-bit processors and is normally either connected to the microprocessor address bus or grounded.
Connecting to 5V Logic Systems
3V
LTC1282
3V ADC
LTC ESD
CLAMP
5V
ADC OUTPUTS
0V TO 3V
ADC INPUTS
0V TO 5V
TTL
INPUT
LEVELS
CMOS
OUTPUT
LEVELS
5V
LOGIC
LTC1282 • F14
Figure 14. 3V ADC ESD Protection Handles
0V to 5V Swings Easily
Rev. B
16
For more information www.analog.com
LTC1282
APPLICATIONS INFORMATION
Internal Clock
The LTC1282 has an internal clock that eliminates the
need for synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 5.5µs, and a maximum conversion time over the
full operating temperature range of 6.0µs. No external
adjustments are required and, with the guaranteed maximum acquisition time of 1.14µs, throughput performance
of 140ksps is assured.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: HBEN, CS and RD. Figure 15 shows
the logic structure associated with these inputs. The three
signals are internally gated so that a logic “0” is required
on all three inputs to initiate a conversion. Once initiated
it cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output, and
this is low while conversion is in progress.
LTC1282
HBEN 19
CS
21
RD 20
BUSY
D
Q
CONVERSION
START (RISING
EDGE TRIGGER)
FLIP
FLOP
CLEAR
ACTIVE HIGH
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
D11....D0/8 = DB11....DB0
ENABLE THREE-STATE OUTPUTS
D11....D8 = DB11....DB8
D7....D4 = LOW
D3/11....D0/8 = DB11....DB8
* D11....D0/8 ARE THE ADC DATA OUTPUT PINS
DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS
LTC1282 • F15
Figure 15. Internal Logic for Control Inputs CS, RD and HBEN
There are two modes of operation as outlined by the timing diagrams of Figures 16 to 19. Slow Memory Mode is
designed for microprocessors which can be driven into
a WAIT state. A READ operation brings CS and RD low
which initiates a conversion and data is read when conversion is complete. The second is the ROM Mode which
does not require microprocessor WAIT states. A READ
operation brings CS and RD low which initiates a conversion and reads the previous conversion result.
Data Format
The output format can be either a complete parallel load
for 16-bit microprocessors or a two byte load for 8-bit
microprocessors. Data is always right justified (i.e., LSB
is the most right-hand bit in a 16-bit word). For a two byte
read, only data outputs D7...D0/8 are used. Byte selection is governed by the HBEN input which controls an
internal digital multiplexer. This multiplexes the 12-bits of
conversion data onto the lower D7...D0/8 outputs (4MSBs
or 8MSBs) where it can be read in two read cycles. The
4MSBs always appear on D11...D8 whenever the threestate output drivers are turned on.
Slow Memory Mode, Parallel Read (HBEN = LOW)
Figure 16 and Table 2 show the timing diagram and data
bus status for Slow Memory Mode, Parallel Read. CS and
RD going low trigger a conversion and the ADC acknowledges by taking BUSY low. Data from the previous conversion appears on the three-state data outputs. BUSY
returns high at the end of conversion when the output
latches have been updated and the conversion result is
placed on data outputs D11...D0/8.
Slow Memory Mode, Two Byte Read
For a two byte read, only 8 data outputs D7...D0/8 are
used. Conversion start procedure and data output status
for the first read operation are identical to Slow Memory
Mode, Parallel Read. See Figure 17 timing diagram and
Table 3 data bus status. At the end of the conversion, the
low data byte (D7...D0/8) is read from the ADC. A second
READ operation with the HBEN high, places the high byte
on data outputs D3/11...D0/8 and disables conversion
start. Note the 4MSBs appear on data output D11...D8
during the two READ operations.
Rev. B
For more information www.analog.com
17
LTC1282
APPLICATIONS INFORMATION
CS
t1
t5
t1
RD
t2
tCONV
BUSY
t7
t6
t3
OLD DATA
DB11-DB0
DATA
t10
t11
NEW DATA
DB11-DB0
t12
HOLD
TRACK
LTC1282 • F16
Figure 16. Slow Memory Mode, Parallel Read Timing Diagram
Table 2. Slow Memory Mode, Parallel Read Data Bus Status
Data Outputs
Read
D11
D10
D9
D8
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
Db11
Db10
Db9
Db8
Db7
Db6
Db5
Db4
Db3
Db2
Db1
Db0
HBEN
t8
t9
t8
t9
CS
t1
t5
t1
t5
t4
RD
t2
t10
t10
t11
t CONV
BUSY
t3
t6
OLD DATA
DB7-DB0
DATA
t7
t3
t7
NEW DATA
DB11-DB8
NEW DATA
DB7-DB0
t12
HOLD
t12
TRACK
LTC1282 • F17
Figure 17. Slow Memory Mode, Two Byte Read Timing Diagram
Table 3. Slow Memory Mode, Two Byte Read Data Bus Status
Data Outputs
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
First Read
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Second Read
Low
Low
Low
Low
DB11
DB10
DB9
DB8
Rev. B
18
For more information www.analog.com
LTC1282
APPLICATIONS INFORMATION
CS
t1
t5
t4
t1
RD
t11
t2
t CONV
BUSY
t3
DATA
HOLD
t7
t5
t4
t2
t CONV
t3
t7
OLD DATA
DB11-DB0
NEW DATA
DB11-DB0
t12
t12
TRACK
LTC1282 • F18
Figure 18. ROM Mode, Parallel Read Timing Diagram (HBEN = LOW)
Table 4. Rom Mode, Parallel Read Data Bus Status
Data Outputs
D11
D10
D9
D8
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
First Read (Old Data)
Db11
Db10
Db9
Db8
Db7
Db6
Db5
Db4
Db3
Db2
Db1
Db0
Second Read
Db11
Db10
Db9
Db8
Db7
Db6
Db5
Db4
Db3
Db2
Db1
Db0
ROM Mode, Parallel Read (HBEN = LOW)
The ROM Mode avoids placing a microprocessor into a
WAIT state. A conversion is started with a READ operation,
and the 12 bits of data from the previous conversion are
available on data outputs D11...D0/8 (see Figure 18 and
Table 4). This data may be disregarded if not required. A
second READ operation reads the new data (DB11...DB0)
and starts another conversion. A delay at least as long
as the ADC’s conversion time plus the 1.0µs minimum
delay between conversions must be allowed between
READ operations.
ROM Mode, Two Byte Read
As previously mentioned for a two byte read, only data
outputs D7...D0/8 are used. Conversion is started in the
normal way with a READ operation and the data output
status is the same as the ROM mode, Parallel Read (see
Figure 19 timing diagram and Table 5 data bus status).
Two more READ operations are required to access the new
conversion result. A delay equal to the ADC’s conversion
time must be allowed between conversion start and the
second data READ operation. The second READ operation with HBEN high disables conversion start and places
the high byte (4MSBs) on data outputs D3/11...D0/8. A
third read operation accesses the low data byte (DB7...
DB0) and starts another conversion. The 4MSBs appear
on data outputs D11...D8 during all three read operations.
MICROPROCESSOR INTERFACING
The LTC1282 allows easy interfacing to digital signal
processors as well as modern high speed, 8-bit or
16-bit microprocessors. Here are several examples.
TMS320C25
Figure 20 shows an interface between the LTC1282 and
the TMS320C25.
The R/W signal of the DSP initiates a conversion and
conversion results are read from the LTC1282 using the
following instruction:
IN
D, PA
Rev. B
For more information www.analog.com
19
LTC1282
APPLICATIONS INFORMATION
HBEN
t8
t9
t8
t9
t9
t8
CS
t1
t5
t4
RD
t2
t1
t5
t4
t1
t11
tCONV
t4
t5
t10
t2
BUSY
t3
t7
t3
OLD DATA
DB7-DB0
DATA
t7
t3
NEW DATA
DB11-DB8
t12
t12
HOLD
t7
NEW DATA
DB7-DB0
TRACK
LTC1282 • F19
Figure 19. ROM Mode Two Byte Read Timing Diagram
Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
First Read (Old Data)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Second Read (New Data)
Low
Low
Low
Low
DB11
DB10
DB9
DB8
Third Read (New Data)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
A16
A1
IS
TMS320C25
EN
LTC1282
CS
BUSY
RD
R/W
D0
MC68000 Microprocessor
ADDRESS
DECODE
READY
D16
where D is Data Memory Address and PA is the PORT
ADDRESS.
ADDRESS BUS
DATA BUS
D11
D0/8
HBEN
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1282 • F20
Figure 20. TMS320C25 Interface
Figure 21 shows a typical interface for the MC68000.
The LTC1282 is operating in the Slow Memory Mode.
Assuming the LTC1282 is located at address C000, then
the following single 16-bit MOVE instruction both starts
a conversion and reads the conversion result:
Move.W $C000,D0
At the beginning of the instruction cycle when the ADC
address is selected, BUSY and CS assert DTACK so that
the MC68000 is forced into a WAIT state. At the end of
conversion, BUSY returns high and the conversion result
is placed in the D0 register of the microprocessor.
Rev. B
20
For more information www.analog.com
LTC1282
APPLICATIONS INFORMATION
A23
A1
AS
ADDRESS BUS
EN
MC68000
ADDRESS
DECODE
DTACK
RD
R/W
D11
D0
LTC1282
CS
BUSY
TMS32010 Microcomputer
D11
DATA BUS
D0/8
HBEN
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1282 • F21
Figure 21. MC68000 Interface
8085A/Z80 Microprocessor
Figure 22 shows an LTC1282 interface for the Z80 and
8085A. The LTC1282 is operating in the Slow Memory
Mode and a two byte read is required. Not shown in
the figure is the 8-bit latch required to demultiplex the
8085A common address/data bus. A0 is used to assert
HBEN so that an even address (HBEN = LOW) to the
LTC1282 will start a conversion and read the low data
byte. An odd address (HBEN = HIGH) will read the high
data byte. This is accomplished with the single 16-bit
LOAD instruction below.
For the 8085A
For the Z80
This is a two byte read instruction which loads the ADC
data (address B000) into the HL register pair. During the
first read operation, BUSY forces the microprocessor
to WAIT for the LTC1282 conversion. No WAIT states
are inserted during the second read operation when the
microprocessor is reading the high data byte.
LHLD (B000)
LDHL, (B000)
Figure 23 shows an LTC1282/TMS32010 interface. The
LTC1282 is operating in the ROM Mode. The interface
is designed for a maximum TMS32010 clock frequency
of 18MHz but will typically work over the full TMS32010
clock frequency range.
The LTC1282 is mapped at a port address. The following
I/O instruction starts a conversion and reads the previous
conversion result into data memory.
IN A,PA
(PA = PORT ADDRESS)
When conversion is complete, a second I/O instruction
reads the up-to-date data into memory and starts another
conversion. A delay at least as long as the ADC conversion
time must be allowed between I/O instructions.
PA2
PA0
DEN
TMS32010
PORT ADDRESS BUS
EN
ADDRESS
DECODE
LTC1282
CS
A15
A0
ADDRESS BUS
MREQ
ADDRESS
DECODE
Z80
8085A
A0
RD
EN
D11
HBEN
RD
CS
BUSY
LTC1282
RD
D7
D7
WAIT
D0
DATA BUS
D0
DATA BUS
D11
D0/8
HBEN
LINEAR CIRCUITRY OMITTED FOR CLARITY
LTC1282 • F23
Figure 23. TMS32010 Interface
D0/8
LINEAR CIRCUITRY OMITTED FOR CLARITY
LTC1282 • F22
Figure 22. 8085A and Z80 Interface
Rev. B
For more information www.analog.com
21
LTC1282
APPLICATIONS INFORMATION
MUXing with CD4051
The high input impedance of the LTC1282 provides an
easy, cheap, fast, and accurate way to multiplex many
channels of data through one converter. Figure 24 shows
a low cost CD4051, one of the most common multiplexers connected to the LTC1282. The LTC1282’s input
draws no DC input current so it can be accurately driven
by the unbuffered MUX. The CD4520 counter increments
the MUX channel after each sample is taken.
100ps Resolution ∆Time Measurement with LTC1282
events. The LTC1282 digitizes this final value and outputs the digital data.
3V
CD4051
NO
BUFFER
REQUIRED
D11
•
•
•
AIN
LTC1282
8 INPUT
CHANNELS
±1.25V
INPUT
VARIES
µP
OR
DSP
D0
CS
RD
BUSY
–3V
Figure 25 shows a circuit that precisely measures the
difference in time between two events. It has a 400ns full
scale and 100ps resolution. The start signal releases the
ramp generator made up of the PNP current source and
the 500pF capacitor. The circuit ramps until the stop
signal shuts off the current source. The final value of
the ramp represents the time between the start and stop
VSS
A
LTC1282 • F24
B C
ENABLE
CD4520
COUNTER
Q0 RESET
Q2
Q1
Figure 24. MUXing the LTC1282 with CD4051
3.3V
65Ω
2N2369
65Ω
10µF
2N2369
200k
10µF
1N457
2N5771
REFOUT
20k
430Ω
LM134
250pF
POLYSTYRENE
45.3Ω
1N457
5V
D
START↑
1k
D
Q
CLK
Q
CLR
5V
CS VSS GND RD BUSY
Q
CLR
STOP↑
12-BIT
DATA
OUTPUT
Q
CLK
5V
LTC1282
74HC03
74HC74
45.3Ω
AIN
VDD
1N4148
DATA
LATCH
SIGNAL
10k
5V
1N4148
1k
100k
100pF
0.001µF
1k
10k
10pF
LTC1282 • F25
Figure 25. ∆ Time Measurement with the LTC1282
Rev. B
22
For more information www.analog.com
LTC1282
APPLICATIONS INFORMATION
Other High Speed A/D Converters
LTC makes a family of high speed sampling ADCs for a
variety of applications. Both single 5V and ± 5V supply
devices are available at high speeds. The high speed
12-bit family is summarized below.
Comparison of Specifications and Features
300ksps and 500ksps 12-Bit Sampling A/D Converters
Built-In
Sample & Hold
2.42V
VREF
OUTPUT
2.7µs Conversion
Time
LTC1273/5/6
ANALOG INPUT
AIN
VDD
+
VREF
NC
0.1µF
10µF
AGND
D11 (MSB)
D10
Reference
Output For
System Use
D9
10µF
+
CS
RD
HBEN
D7
Parallel Outputs
For The Fastest
Data Transfer Rates
5V
BUSY
D8
8- OR 12-BIT
PARALLEL BUS
Reference On Board
D6
D0/8
D5
D1/9
D4
D2/10
DGND
D3/11
µP CONTROL
LINES
0.1µF
Only 75mW
Power
Consumption
No Negative
Supply Required
for Unipolar
Operation
Internal Clock
No Crystal
Required
DEVICE
TYPE
SAMPLING S/(N + D)
FREQ
@ NYQUIST
INPUT
RANGE
POWER
POWER
SUPPLY DISSIPATION
LTC1272
250kHz
65dB
0V-5V
5V
75mW
LTC1273
300kHz
70dB
0V-5V
5V
75mW
LTC1275
300kHz
70dB
±2.5V
±5V
75mW
LTC1276
300kHz
70dB
±5V
±5V
75mW
LTC1278
500kHz
70dB
0V-5V
or ±2.5V
5V
or ±5V
75mW
6mW*
LTC1282
140kHz
68dB
0V-2.5V
or ±1.25V
3V
or ±3V
12mW
*6mW power shutdown with instant wake up
Rev. B
For more information www.analog.com
23
LTC1282
PACKAGE DESCRIPTION
SW Package
24-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
N
24
23
22
21
.598 – .614
(15.190 – 15.600)
NOTE 4
20 19 18 17 16
15
14
13
N
.325 ±.005
.420
MIN
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
.005
(0.127)
RAD MIN
.009 – .013
(0.229 – 0.330)
NOTE:
1. DIMENSIONS IN
.291 – .299
(7.391 – 7.595)
NOTE 4
.010 – .029 × 45°
(0.254 – 0.737)
1
2
3
4
5
6
.093 – .104
(2.362 – 2.642)
7
8
9
10
11
12
.037 – .045
(0.940 – 1.143)
0° – 8° TYP
NOTE 3
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.356 – 0.482)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.004 – .012
(0.102 – 0.305)
S24 (WIDE) 0502
Rev. B
24
For more information www.analog.com
LTC1282
REVISION HISTORY
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
B
09/19
Removed 24-Pin Narrow PDIP package option.
PAGE NUMBER
1, 2, 23
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
25
LTC1282
RELATED PARTS
PART NUMBER
RESOLUTION
SPEED
COMMENTS
LTC1604
16
333ksps
±2.5V Input Range, ±5V Supply
LTC1605
16
100ksps
±10V Input Range, Single 5V Supply
LTC1419
14
800ksps
150mW, 81.5dB SINAD and 95dB SFDR
LTC1416
14
400ksps
75mW, Low Power with Excellent AC Specs
LTC1418
14
200ksps
15mW, Single 5V, Serial/Parallel I/O
12
1.25Msps
150mW, 71.5dB SINAD and 84dB THD
16-Bit
14-Bit
12-Bit
LTC1410
LTC1415
12
1.25Msps
55mW, Single 5V Supply
LTC1409
12
800ksps
80mW, 71.5dB SINAD and 84dB THD
LTC1279
12
600ksps
60mW, Single 5V or ±5V Supply
LTC1404
12
600ksps
High Speed Serial I/O in SO-8 Package
LTC1278-5
12
500ksps
75mW, Single 5V or ±5V Supply
LTC1278-4
12
400ksps
75mW, Single 5V or ±5V Supply
LTC1400
12
400ksps
High Speed Serial I/O in SO-8 Package
Rev. B
26
09/19
www.analog.com
For more information www.analog.com
ANALOG DEVICES, INC. 1993-2019
工商网监
湘ICP备2023018690号
