LTC1407/LTC1407A
Serial 12-Bit/14-Bit, 3Msps
Simultaneous Sampling
ADCs with Shutdown
FEATURES
DESCRIPTION
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The LTC®1407/LTC1407A are 12-bit/14-bit, 3Msps ADCs
with two 1.5Msps simultaneously sampled differential
inputs. The devices draw only 4.7mA from a single 3V
supply and come in a tiny 10-lead MS package. A Sleep
shutdown feature lowers power consumption to 10μW.
The combination of speed, low power and tiny package
makes the LTC1407/LTC1407A suitable for high speed,
portable applications.
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3Msps Sampling ADC with Two Simultaneous
Differential Inputs
1.5Msps Throughput per Channel
Low Power Dissipation: 14mW (Typ)
3V Single Supply Operation
2.5V Internal Bandgap Reference with External
Overdrive
3-Wire Serial Interface
Sleep (10μW) Shutdown Mode
Nap (3mW) Shutdown Mode
80dB Common Mode Rejection at 100kHz
0V to 2.5V Unipolar Input Range
Tiny 10-Lead MS Package
The LTC1407/LTC1407A contain two separate differential
inputs that are sampled simultaneously on the rising edge
of the CONV signal. These two sampled inputs are then
converted at a rate of 1.5Msps per channel.
The 80dB common mode rejection allows users to eliminate
ground loops and common mode noise by measuring
signals differentially from the source.
APPLICATIONS
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Telecommunications
Data Acquisition Systems
Uninterrupted Power Supplies
Multiphase Motor Control
I and Q Demodulation
Industrial Control
The devices convert 0V to 2.5V unipolar inputs differentially.
The absolute voltage swing for CH0+, CH0–, CH1+ and
CH1– extends from ground to the supply voltage.
The serial interface sends out the two conversion results in 32
clocks for compatibility with standard serial interfaces.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
BLOCK DIAGRAM
3V
+
CH0–
2
–
S AND H
MUX
CH1+
4
+
S AND H
CH1–
5
3
10μF
–
GND
11
–44
LTC1407A
–50
–56
THREESTATE
SERIAL
OUTPUT
PORT
SDO
8
10
CONV
9
SCK
TIMING
LOGIC
VREF
6
3Msps
14-BIT ADC
VDD
THD, 2nd, 3rd (dB)
1
14-BIT LATCH
7
CH0+
THD, 2nd and 3rd
vs Input Frequency
14-BIT LATCH
10μF
THD
2nd
–62
–68
–74
3rd
–80
–86
–92
–98
2.5V
REFERENCE
–104
0.1
1
10
FREQUENCY (MHz)
100
1407 G02
EXPOSED PAD
1407A BD
1407fb
1
LTC1407/LTC1407A
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VDD) .................................................4V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................. –0.3V to (VDD + 0.3V)
Power Dissipation ...............................................100mW
Operation Temperature Range
LTC1407C/LTC1407AC ............................. 0°C to 70°C
LTC1407I/LTC1407AI ...........................– 40°C to 85°C
LTC1407H/LTC1407AH .......................– 40°C to 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
TOP VIEW
CH0+
CH0–
VREF
CH1+
CH1–
1
2
3
4
5
10
9
8
7
6
11
CONV
SCK
SDO
VDD
GND
MSE PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN #) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1407CMSE#PBF
LTC1407CMSE#TRPBF
LTBDQ
10-Lead Plastic MSOP
0°C to 70°C
LTC1407IMSE#PBF
LTC1407IMSE#TRPBF
LTBDR
10-Lead Plastic MSOP
–40°C to 85°C
LTC1407HMSE#PBF
LTC1407HMSE#TRPBF
LTBDR
10-Lead Plastic MSOP
–40°C to 125°C
LTC1407ACMSE#PBF
LTC1407ACMSE#TRPBF
LTAFE
10-Lead Plastic MSOP
0°C to 70°C
LTC1407AIMSE#PBF
LTC1407AIMSE#TRPBF
LTAFF
10-Lead Plastic MSOP
–40°C to 85°C
LTC1407AHMSE#PBF
LTC1407AHMSE#TRPBF
LTAFF
10-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
PARAMETER
CONDITIONS
MIN
l
Resolution (No Missing Codes)
LTC1407
LTC1407A
LTC1407H
LTC1407AH
TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
12
14
12
14
UNITS
Bits
Integral Linearity Error
(Notes 5, 17)
l
–2
±0.25
2
–4
±0.5
4
–2
±0.25
2
–4
±0.5
4
LSB
Offset Error
(Notes 4, 17)
l
–10
±1
10
–20
±2
20
–20
±1
20
–30
±2
30
LSB
Offset Match from CH0 to CH1
(Note 17)
–5
±0.5
5
–10
±1
10
–5
±0.5
5
–10
±1
10
LSB
Gain Error
(Notes 4, 17)
–30
±5
30
–60 ±10
60
–40
±5
40
–80 ±10
80
LSB
Gain Match from CH0 to CH1
(Note 17)
–5
±1
5
–10
10
–5
±1
5
–10
10
LSB
Gain Tempco
Internal Reference (Note 4)
External Reference
l
±15
±1
±2
±15
±1
±15
±1
±2
±15
±1
ppm/°C
ppm/°C
1407fb
2
LTC1407/LTC1407A
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Differential Input Range (Notes 3, 9)
VCM
Analog Common Mode + Differential
Input Range (Note 10)
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
tACQ
Sample-and-Hold Acquisition Time
tAP
Sample-and-Hold Aperture Delay Time
tJITTER
MIN
2.7V ≤ VDD ≤ 3.3V
TYP
MAX
UNITS
0 to 2.5
V
0 to VDD
V
l
1
μA
39
ns
13
pF
l
(Note 6)
1
ns
Sample-and-Hold Aperture Delay Time Jitter
0.3
ps
tSK
Sample-and-Hold Aperture Skew from CH0 to CH1
200
ps
CMRR
Analog Input Common Mode Rejection Ratio
–60
–15
dB
dB
fIN = 1MHz, VIN = 0V to 3V
fIN = 100MHz, VIN = 0V to 3V
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
LTC1407/LTC1407H LTC1407A/LTC1407AH
MIN
TYP MAX MIN
TYP MAX
SYMBOL PARAMETER
CONDITIONS
SINAD
Signal-to-Noise Plus
Distortion Ratio
100kHz Input Signal
750kHz Input Signal
750kHz Input Signal (H Grade)
100kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V
750kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V
Total Harmonic
Distortion
100kHz First 5 Harmonics
750kHz First 5 Harmonics
750kHz First 5 Harmonics (H Grade)
SFDR
Spurious Free
Dynamic Range
100kHz Input Signal
750kHz Input Signal
87
83
90
86
dB
dB
IMD
Intermodulation
Distortion
1.25V to 2.5V 1.40MHz into CH0+, 0V to 1.25V,
1.56MHz into CH0–. Also Applicable to CH1+ and CH1–
–82
–82
dB
Code-to-Code
Transition Noise
VREF = 2.5V (Note 17)
0.25
1
LSBRMS
Full Power Bandwidth
VIN = 2.5VP-P, SDO = 11585LSBP-P (–3dBFS) (Note 15)
50
50
MHz
Full Linear Bandwidth
S/(N + D) ≥ 68dB
5
5
MHz
THD
l
l
l
l
68
67
70.5
70.5
70.5
72.0
72.0
–87
–83
–82
70
69
73.5
73.5
73.5
76.3
76.3
–90
–86
–85
–77
–76
UNITS
dB
dB
dB
dB
dB
–80
–79
dB
dB
dB
INTERNAL REFERENCE CHARACTERISTICS TA = 25°C. VDD = 3V.
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
MIN
TYP
MAX
UNITS
2.5
V
15
ppm/°C
μV/V
VREF Line Regulation
VDD = 2.7V to 3.6V, VREF = 2.5V
600
VREF Output Resistance
Load Current = 0.5mA
0.2
Ω
2
ms
VREF Setting Time
1407fb
3
LTC1407/LTC1407A
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
VDD = 3.3V
l
VIL
Low Level Input Voltage
VDD = 2.7V
l
0.6
V
IIN
Digital Input Current
VIN = 0V to VDD
l
±10
μA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VDD = 3V, IOUT = –200μA
l
VOL
Low Level Output Voltage
VDD = 2.7V, IOUT = 160μA
VDD = 2.7V, IOUT = 1.6mA
l
VOUT = 0V to VDD
l
IOZ
Hi-Z Output Leakage DOUT
COZ
Hi-Z Output Capacitance DOUT
ISOURCE
Output Short-Circuit Source Current
ISINK
Output Short-Circuit Sink Current
2.4
V
2.5
5
pF
2.9
V
0.05
0.10
0.4
V
V
±10
μA
1
pF
VOUT = 0V, VDD = 3V
20
mA
VOUT = VDD = 3V
15
mA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
SYMBOL
PARAMETER
VDD
Supply Voltage
IDD
Supply Current
PD
CONDITIONS
MIN
TYP
MAX
2.7
l
l
l
l
Active Mode, fSAMPLE = 1.5Msps
Active Mode (LTC1407H/LTC1407AH)
Nap Mode
Nap Mode (LTC1407H/LTC1407AH)
Sleep Mode (LTC1407/LTC1407H)
Sleep Mode (LTC1407A/LTC1407AH)
4.7
5.2
1.1
1.2
2.0
2.0
Active Mode with SCK in Fixed State (Hi or Lo)
12
UNITS
3.6
V
7.0
8.0
1.5
1.8
15
10
mA
mA
mA
mA
μA
μA
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency per Channel
(Conversion Rate)
l
tTHROUGHPUT
Minimum Sampling Period (Conversion + Acquisiton Period)
l
tSCK
Clock Period
(Note 16)
tCONV
Conversion Time
(Note 6)
32
t1
Minimum Positive or Negative SCLK Pulse Width
(Note 6)
2
t2
CONV to SCK Setup Time
(Notes 6, 10)
3
t3
SCK Before CONV
(Note 6)
0
ns
t4
Minimum Positive or Negative CONV Pulse Width
(Note 6)
4
ns
t5
SCK to Sample Mode
(Note 6)
4
ns
t6
CONV to Hold Mode
(Notes 6, 11)
1.2
ns
l
1.5
MHz
19.6
667
ns
10000
ns
34
SCLK cycles
ns
10000
ns
1407fb
4
LTC1407/LTC1407A
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V.
PARAMETER
CONDITIONS
t7
32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t8
Minimum Delay from SCK to Valid Bits 0 Through 11
(Notes 6, 12)
8
ns
t9
SCK to Hi-Z at SDO
(Notes 6, 12)
6
ns
t10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
2
ns
t12
VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and range specifications apply for a single-ended CH0+ or CH1+
input with CH0 – or CH1– grounded and using the internal 2.5V reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between CH0+ and CH0– or CH1+ and CH1–.
Note 9: The absolute voltage at CH0+, CH0–, CH1+ and CH1– must be
within this range.
74
11.5
71
10.5
65
10.0
62
9.5
59
9.0
56
8.5
53
8.0
0.1
1
10
FREQUENCY (MHz)
50
100
1407 G01
THD, 2nd, 3rd (dB)
ENOBs (BITS)
68
SFDR vs Input Frequency
98
THD
92
2nd
–62
86
–68
–74
3rd
–80
80
74
68
62
–86
–92
56
–98
50
–104
0.1
ms
104
–50
SINAD (dB)
11.0
UNITS
VDD = 3V, TA = 25°C (LTC1407A)
–44
–56
MAX
2
THD, 2nd and 3rd
vs Input Frequency
12.0
TYP
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A is measured and specified with 14-bit resolution
(1LSB = 152μV) and the LTC1407 is measured and specified with 12-bit
resolution (1LSB = 610μV).
TYPICAL PERFORMANCE CHARACTERISTICS
ENOBs and SINAD
vs Input Sinewave Frequency
MIN
SFDR (dB)
SYMBOL
1
10
FREQUENCY (MHz)
100
1407 G02
44
0.1
1
10
FREQUENCY (MHz)
100
1407 G19
1407fb
5
LTC1407/LTC1407A
TYPICAL PERFORMANCE CHARACTERISTICS
98kHz Sine Wave 4096 Point
FFT Plot
SNR vs Input Frequency
74
0
MAGNITUDE (dB)
68
SNR (dB)
65
62
59
1
10
FREQUENCY (MHz)
100
–20
–20
–30
–30
–40
–40
–50
–60
–70
–80
–90
–110
–110
–120
–120
0
100
200 300 400 500
FREQUENCY (kHz)
600
–40
–50
–60
–70
–80
–90
–100
–110
100
200 300 400 500
FREQUENCY (kHz)
600
700
1.0
2.0
1.6
0.6
1.2
0.4
0.2
0
–0.2
–0.4
–0.6
0
–0.4
–0.8
–1.2
–1.6
–2.0
0
4096
12288
8192
OUTPUT CODE
16384
4096
12288
8192
OUTPUT CODE
2.0
0.8
1.6
0.6
1.2
0.2
0
–0.2
–0.4
–0.6
0.4
0
–0.4
–0.8
–1.2
–1.6
–1.0
–2.0
1407 G17
1407 G16
0.8
–0.8
16384
16384
Integral Linearity End Point Fit for
CH1 with Internal 2.5V Reference
1.0
12288
8192
OUTPUT CODE
0
1407 G15
0.4
700
0.8
–1.0
INTEGRAL LINEARITY (LSB)
DIFFERENTIAL LINEARITY (LSB)
600
0.4
–0.8
Differential Linearity for CH1 with
Internal 2.5V Reference
4096
200 300 400 500
FREQUENCY (kHz)
Integral Linearity End Point Fit for
CH0 with Internal 2.5V Reference
0.8
1407 G06
0
100
1407 G05
INTEGRAL LINEARITY (LSB)
DIFFERENTIAL LINEARITY (LSB)
MAGNITUDE (dB)
–30
0
1407 G04
1.5Msps
0
700
Differential Linearity for CH0 with
Internal 2.5V Reference
–20
–120
–80
–100
1407 G03
0
–60
–70
–100
1403kHz Input Summed with
1563kHz Input IMD 4096 Point
FFT Plot
–10
–50
–90
56
53
0
1.5Msps
–10
MAGNITUDE (dB)
71
748kHz Sine Wave 4096 Point
FFT Plot
1.5Msps
–10
50
0.1
VDD = 3V, TA = 25°C (LTC1407A)
0
4096
12288
8192
OUTPUT CODE
16384
1407 G18
1407fb
6
LTC1407/LTC1407A
TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407/LTC1407A)
Full-Scale Signal Frequency
Response
CMRR vs Frequency
12
Crosstalk vs Frequency
–20
0
6
–30
–20
CROSSTALK (dB)
–40
–40
CMRR (dB)
–6
–12
–18
–60
CH0
CH1
–80
–100
–30
–36
1M
10M
100M
FREQUENCY (Hz)
1k
10k 100k
1M
FREQUENCY (Hz)
10M
1407 G07
CH1 TO CH0
CH0 TO CH1
100M
–90
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
1407 G09
1407 G08
Simultaneous Input Steps at CH0
and CH1 from 25Ω
PSSR vs Frequency
3.0
–25
2.6
–30
2.2
–35
–40
1.8
PSRR (dB)
ANALOG INPUTS (V)
–60
–80
–120
100
1G
–50
–70
–24
CH0
CH1
1.4
1.0
–45
–50
0.6
–55
0.2
–60
–0.2
–65
–70
–0.6
0
5
10
15
20
TIME (ns)
1
30
25
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
1407 G11
1407 G10
Reference Voltage
vs Load Current
Reference Voltage vs VDD
2.4902
2.4900
2.4900
2.4898
2.4898
VREF (V)
2.4902
VREF (V)
AMPLITUDE (dB)
0
2.4896
2.4896
2.4894
2.4894
2.4892
2.4892
2.4890
2.4890
2.6
2.8
3.0
3.2
VDD (V)
3.4
3.6
1407 G12
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (mA)
1407 G13
1407fb
7
LTC1407/LTC1407A
PIN FUNCTIONS
CH0+ (Pin 1): Noninverting Channel 0. CH0+ operates
fully differentially with respect to CH0– with a 0V to 2.5V
differential swing and a 0 to VDD absolute input range.
CH0– (Pin 2): Inverting Channel 0. CH0– operates fully
differentially with respect to CH0+ with a –2.5V to 0V differential swing and a 0 to VDD absolute input range.
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and
a solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum in parallel with 0.1μF ceramic). Can be
overdriven by an external reference voltage ≥ 2.55V and
≤VDD.
VDD (Pin 7): 3V Positive Supply. This single power pin
supplies 3V to the entire chip. Bypass to GND pin and
solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum) in parallel with 0.1μF ceramic. Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1μF bypass capacitor as close to Pins 6 and 7
as possible.
SDO (Pin 8): Three-State Serial Data Output. Each pair of
output data words represent the two analog input channels
at the start of the previous conversion.
CH1+ (Pin 4): Noninverting Channel 1. CH1+ operates
fully differentially with respect to CH1– with a 0V to 2.5V
differential swing and a 0 to VDD absolute input range.
SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising
edge. One or more pulses wake from sleep.
CH1– (Pin 5): Inverting Channel 1. CH1– operates fully
differentially with respect to CH1+ with a –2.5V to 0V differential swing and a 0 to VDD absolute input range.
CONV (Pin 10): Convert Start. Holds the two analog input
signals and starts the conversion on the rising edge. Two
pulses with SCK in fixed high or fixed low state starts Nap
mode. Four or more pulses with SCK in fixed high or fixed
low state starts Sleep mode.
GND (Pins 6, 11): Ground and Exposed Pad. This single
ground pin and the Exposed Pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these connections.
BLOCK DIAGRAM
3V
1
+
CH0–
2
–
S AND H
MUX
CH1+
4
CH1–
5
+
S AND H
3
10μF
–
6
11
LTC1407A
THREESTATE
SERIAL
OUTPUT
PORT
8
SDO
10
CONV
9
SCK
TIMING
LOGIC
VREF
GND
3Msps
14-BIT ADC
VDD
14-BIT LATCH
7
CH0+
14-BIT LATCH
10μF
2.5V
REFERENCE
EXPOSED PAD
1407A BD
1407fb
8
SDO
INTERNAL
S/H STATUS
CONV
SCK
SDO
INTERNAL
S/H STATUS
CONV
SCK
t6
t4
34
t6
t4
34
SAMPLE
33
SAMPLE
33
Hi-Z
t3
t8
2
3
D11
4
6
HOLD
7
1
Hi-Z
t3
2
t8
t2
3
D13
4
8
t1
9
t10
10
11
12
13
14
15
D10
D9
D8
6
HOLD
7
8
t1
D6
D4
9
t10
10
11
12-BIT DATA WORD
D5
D3
12
D2
13
D0
D12
D11
D10
D9
D8
D6
14-BIT DATA WORD
D7
D5
D4
X*
X*
17
19
14
15
D3
D2
D1
t9
16
D0
17
19
21
22
HOLD
23
24
25
26
27
28
29
30
t8
20
D10
21
D9
22
D8
HOLD
23
D7
24
D6
D4
25
26
27
12-BIT DATA WORD
D5
D3
28
D2
29
D1
30
D0
D12
D11
D10
D9
D8
D6
14-BIT DATA WORD
D7
D5
D4
D3
D2
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
D13
tTHROUGHPUT
tCONV
Hi-Z
18
t8
20
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
D11
tTHROUGHPUT
tCONV
Hi-Z
18
LTC1407A Timing Diagram
D1
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
5
D7
t9
16
LTC1407 Timing Diagram
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
5
*BITS MARKED “X” AFTER D0 SHOULD BE IGNORED
1
t2
t5
31
t5
31
D1
X*
t8
32
t8
32
D0
X*
34
tACQ
34
Hi-Z
t9
SAMPLE
33
t7
Hi-Z
t9
SAMPLE
tACQ
t7
33
HOLD
HOLD
1407A TD01
1
1407A TD01
1
LTC1407/LTC1407A
TIMING DIAGRAMS
1407fb
9
LTC1407/LTC1407A
TIMING DIAGRAMS
Nap Mode Waveforms
SCK
t1
CONV
NAP
Sleeep Mode Waveforms
SCK
t1
t1
CONV
NAP
SLEEP
t12
VREF
1407 TD02
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
SCK to SDO Delay
SCK
VIH
SCK
VIH
t8
t10
SDO
t9
VOH
90%
SDO
10%
VOL
1407 TD03
1407fb
10
LTC1407/LTC1407A
APPLICATIONS INFORMATION
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1407/LTC1407A are
easy to drive. The inputs may be driven differentially or as
a single-ended input (i.e., the CH0– input is grounded). All
four analog inputs of both differential analog input pairs,
CH0+ with CH0– and CH1+ with CH1–, are sampled at the
same instant. Any unwanted signal that is common to
both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The
inputs draw only one small current spike while charging
the sample-and-hold capacitors at the end of conversion.
During conversion, the analog inputs draw only a small
leakage current. If the source impedance of the driving
circuit is low, then the LTC1407/LTC1407A inputs can be
driven directly. As source impedance increases, so will
acquisition time. For minimum acquisition time with high
source impedance, a buffer amplifier must be used. The
main requirement is that the amplifier driving the analog
input(s) must settle after the small current spike before
the next conversion starts (settling time must be 39ns for
full throughput rate). Also keep in mind, while choosing
an input amplifier, the amount of noise and harmonic
distortion added by the amplifier.
CHOOSING AN INPUT AMPLIFIER
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (< 100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain
of 1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω.
The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate
small-signal settling for full throughput rate. If slower op
amps are used, more time for settling can be provided by
increasing the time between conversions. The best choice
for an op amp to drive the LTC1407/LTC1407A depends
on the application. Generally, applications fall into two
categories: AC applications where dynamic specifications
are most critical and time domain applications where DC
accuracy and settling time are most critical. The following
list is a summary of the op amps that are suitable for driving the LTC1407/LTC1407A. (More detailed information
is available in the Linear Technology Databooks and on
the LinearView™ CD-ROM.)
LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass Filter.
LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high AVOL, 500μV offset and
520ns settling to 0.5LSB for a 4V swing. THD and noise
are – 93dB to 40kHz and below 1LSB to 320kHz (AV = 1,
2VP-P into 1kΩ, VS = 5V), making the part excellent for
AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631.
LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and
400ns settling to 0.5LSB for a 4V swing. It is suitable for
applications with a single 5V supply. THD and noise are
– 93dB to 40kHz and below 1LSB to 800kHz (AV = 1,
2VP-P into 1kΩ, VS = 5V), making the part excellent for
AC applications where rail-to-rail performance is desired.
Quad version is available as LT1633.
LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/amplifier, 8.5nV/√Hz.
LT1806/LT1807: 325MHz GBWP, –80dBc distortion at
5MHz, unity-gain stable, rail-to-rail in and out, 10mA/amplifier, 3.5nV/√Hz.
LT1810: 180MHz GBWP, –90dBc distortion at 5MHz,
unity-gain stable, rail-to-rail in and out, 15mA/amplifier,
16nV/√Hz.
LinearView is a trademark of Linear Technology Corporation.
1407fb
11
LTC1407/LTC1407A
APPLICATIONS INFORMATION
LT1818/LT1819: 400MHz, 2500V/μs, 9mA, Single/Dual
Voltage Mode Operational Amplifier.
inputs to minimize noise. A simple 1-pole RC filter is
sufficient for many applications. For example, Figure 1
shows a 47pF capacitor from CHO+ to ground and a 51Ω
source resistor to limit the net input bandwidth to 30MHz.
The 47pF capacitor also acts as a charge reservoir for the
input sample-and-hold and isolates the ADC input from
sampling-glitch sensitive circuitry. High quality capacitors
and resistors should be used since these components
can add distortion. NPO and silvermica type dielectric
capacitors have excellent linearity. Carbon surface mount
resistors can generate distortion from self heating and
from damage that may occur during soldering. Metal
film surface mount resistors are much less susceptible
to both problems. When high amplitude unwanted signals
are close in frequency to the desired signal frequency a
multiple pole filter is required.
LT6200: 165MHz GBWP, –85dBc distortion at 1MHz,
unity-gain stable, rail-to-rail in and out, 15mA/amplifier,
0.95nV/√Hz.
LT6203: 100MHz GBWP, –80dBc distortion at 1MHz,
unity-gain stable, rail-to-rail in and out, 3mA/amplifier,
1.9nV/√Hz.
LT6600: Amplifier/Filter Differential In/Out with 10MHz
Cutoff.
INPUT FILTERING AND SOURCE IMPEDANCE
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1407/LTC1407A noise and distortion. The smallsignal bandwidth of the sample-and-hold circuit is 50MHz.
Any noise or distortion products that are present at the
analog inputs will be summed over this entire bandwidth.
Noisy input circuitry should be filtered prior to the analog
ANALOG
INPUT
51Ω*
High external source resistance, combined with 13pF
of input capacitance, will reduce the rated 50MHz input
bandwidth and increase acquisition time beyond 39ns.
1
47pF*
2
3
10μF
11
ANALOG
INPUT
51Ω*
4
47pF*
5
CH0+
CH0–
LTC1407/
LTC1407A
VREF
GND
CH1+
CH1–
1407 F01
*TIGHT TOLERANCE REQUIRED TO AVOID
APERTURE SKEW DEGRADATION
Figure 1. RC Input Filter
1407fb
12
LTC1407/LTC1407A
APPLICATIONS INFORMATION
INPUT RANGE
The analog inputs of the LTC1407/LTC1407A may be driven
fully differentially with a single supply. Either input may
swing up to 3V, provided the differential swing is no greater
than 2.5V. In the valid input range, the noninverting input
of each channel should always be more positive than the
inverting input of each channel. The 0V to 2.5V range is
also ideally suited for single-ended input use with single
supply applications. The common mode range of the
inputs extend from ground to the supply voltage VDD. If
the difference between the CH0+ and CH0– inputs or the
CH1+ and CH1– inputs exceeds 2.5V, the output code will
stay fixed at all ones, and if this difference goes below 0V,
the ouput code will stay fixed at all zeros.
INTERNAL REFERENCE
The LTC1407/LTC1407A have an on-chip, temperature
compensated, bandgap reference that is factory trimmed
near 2.5V to obtain a precise 2.5V input span. The reference amplifier output VREF, (Pin 3) must be bypassed with
a capacitor to ground. The reference amplifier is stable
with capacitors of 1μF or greater. For the best noise performance, a 10μF ceramic or a 10μF tantalum in parallel
with a 0.1μF ceramic is recommended. The VREF pin can be
overdriven with an external reference as shown in Figure 2.
The voltage of the external reference must be higher than
the 2.5V of the open-drain P-channel output of the internal
reference. The recommended range for an external reference is 2.55V to VDD. An external reference at 2.55V will
see a DC quiescent load of 0.75mA and as much as 3mA
during conversion.
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a unipolar voltage span that
equals the difference between the voltage at the reference
buffer output VREF (Pin 3) and the voltage at the Exposed
Pad ground. The differential input range of ADC is 0V to
2.5V when using the internal reference. The internal ADC
is referenced to these two nodes. This relationship also
holds true with an external reference.
DIFFERENTIAL INPUTS
The ADC will always convert the unipolar difference of
CH0+ minus CH0– or the unipolar difference of CH1+ minus CH1–, independent of the common mode voltage at
either set of inputs. The common mode rejection holds up
at high frequencies (see Figure 3.) The only requirement
is that both inputs not go below ground or exceed VDD.
0
10μF
11
VREF
LTC1407/
LTC1407A
GND
1407 F02
Figure 2
–20
–40
CMRR (dB)
3
3V REF
–60
CH0
CH1
–80
–100
–120
100
1k
10k 100k
1M
FREQUENCY (Hz)
10M
100M
1407 G08
Figure 3. CMRR vs Frequency
1407fb
13
LTC1407/LTC1407A
APPLICATIONS INFORMATION
Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are largely independent of the common
mode voltage. However, the offset error will vary. CMRR
is typically better than 60dB.
Figure 4 shows the ideal input/output characteristics for
the LTC1407/LTC1407A. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB,
1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is natural
binary with 1LSB = 2.5V/16384 = 153μV for the LTC1407A
and 1LSB = 2.5V/4096 = 610μV for the LTC1407. The
LTC1407A has 1LSB RMS of Gaussian white noise.
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best
performance from the LTC1407/LTC1407A, a printed circuit
board with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track. If optimum phase match between
the inputs is desired, the length of the four input wires of
the two input channels should be kept matched. But each
pair of input wires to the two input channels should be
kept separated by a ground trace to avoid high frequency
crosstalk between channels.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in the
Block Diagram on the first page of this data sheet. For
optimum performance, a 10μF surface mount tantalum
capacitor with a 0.1μF ceramic is recommended for the VDD
and VREF pins. Alternatively, 10μF ceramic chip capacitors
such as X5R or X7R may be used. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible. The
VDD bypass capacitor returns to GND (Pin 6) and the
VREF bypass capacitor returns to the Exposed Pad ground
(Pin 11). Care should be taken to place the 0.1μF VDD
bypass capacitor as close to Pins 6 and 7 as possible.
Figure 5 shows the recommended system ground connections. All analog circuitry grounds should be terminated at
the LTC1407/LTC1407A Exposed Pad. The ground return
from the LTC1407/LTC1407A Pin 6 to the power supply
should be low impedance for noise-free operation. The
Exposed Pad of the 10-lead MSE package is also tied to
Pin 6 and the LTC1407/LTC1407A GND. The Exposed Pad
should be soldered on the PC board to reduce ground
connection inductance. Digital circuitry grounds must be
connected to the digital supply common.
111...111
UNIPOLAR OUTPUT CODE
111...110
111...101
000...010
000...001
000...000
0
FS – 1LSB
INPUT VOLTAGE (V)
1407 F04
Figure 4. LTC1407/LTC1407A Transfer Characteristic
1407fb
14
LTC1407/LTC1407A
APPLICATIONS INFORMATION
Figure 5. Recommended Layout
POWER-DOWN MODES
Upon power-up, the LTC1407/LTC1407A are initialized to
the active state and are ready for conversion. The Nap and
Sleep mode waveforms show the power-down modes for
the LTC1407/LTC1407A. The SCK and CONV inputs control
the power-down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges
at SCK, put the LTC1407/LTC1407A in Nap mode and the
power drain drops from 14mW to 6mW. The internal reference remains powered in Nap mode. One or more rising
edges at SCK wake up the LTC1407/LTC1407A for service
very quickly and CONV can start an accurate conversion
within a clock cycle.
Four rising edges at CONV, without any intervening rising
edges at SCK, put the LTC1407/LTC1407A in Sleep mode
and the power drain drops from 14mW to 10μW. To bring
the part out of Sleep mode requires one or more rising SCK
edges followed by a Nap request. Then one or more rising
edges at SCK wake up the LTC1407/LTC1407A for operation.
When Nap mode is entered after Sleep mode, the reference
that was shut down in Sleep mode is reactivated.
The internal reference (VREF ) takes 2ms to slew and settle
with a 10μF load. Using Sleep mode more frequently compromises the settled accuracy of the internal reference.
Note that for slower conversion rates, the Nap and Sleep
modes can be used for substantial reductions in power
consumption.
1407fb
15
LTC1407/LTC1407A
APPLICATIONS INFORMATION
DIGITAL INTERFACE
The LTC1407/LTC1407A have a 3-wire SPI (Serial Protocol
Interface) interface. The SCK and CONV inputs and SDO
output implement this interface. The SCK and CONV inputs
accept swings from 3V logic and are TTL compatible, if the
logic swing does not exceed VDD. A detailed description
of the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subsequent rising edges at CONV are ignored by the LTC1407/
LTC1407A until the following 32 SCK rising edges have
occurred. The duty cycle of CONV can be arbitrarily chosen
to be used as a frame sync signal for the processor serial
port. A simple approach to generate CONV is to create a
pulse that is one SCK wide to drive the LTC1407/LTC1407A
and then buffer this signal to drive the frame sync input
of the processor serial port. It is good practice to drive
the LTC1407/LTC1407A CONV input first to avoid digital
noise interference during the sample-to-hold transition
triggered by CONV at the start of conversion. It is also good
practice to keep the width of the low portion of the CONV
signal greater than 15ns to avoid introducing glitches in
the front end of the ADC just before the sample-and-hold
goes into Hold mode at the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sinewaves
above 100kHz are sampled, the CONV signal must have
as little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement easily. The challenge is to generate a CONV
signal from this crystal clock without jitter corruption from
other digital circuits in the system. A clock divider and
any gates in the signal path from the crystal clock to the
CONV input should not share the same integrated circuit
with other parts of the system. As shown in the interface
circuit examples, the SCK and CONV inputs should be
driven first, with digital buffers used to drive the serial port
interface. Also note that the master clock in the DSP may
already be corrupted with jitter, even if it comes directly
from the DSP crystal. Another problem with high speed
processor clocks is that they often use a low cost, low
speed crystal (i.e., 10MHz) to generate a fast, but jittery,
phase-locked-loop system clock (i.e., 40MHz). The jitter
in these PLL-generated high speed clocks can be several
nanoseconds. Note that if you choose to use the frame
sync signal generated by the DSP port, this signal will
have the same jitter of the DSP’s master clock.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK sends out two
sets of 12/14 data bits, with the MSB sent first. A simple
approach is to generate SCK to drive the LTC1407/LTC1407A
first and then buffer this signal with the appropriate number
of inverters to drive the serial clock input of the processor
serial port. Use the falling edge of the clock to latch data
from the Serial Data Output (SDO) into your processor serial
port. The 14-bit Serial Data will be received right justified,
in two 16-bit words with 32 or more clocks per frame
sync. It is good practice to drive the LTC1407/LTC1407A
SCK input first to avoid digital noise interference during
the internal bit comparison decision by the internal high
speed comparator. Unlike the CONV input, the SCK input
is not sensitive to jitter because the input signal is already
sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out two sets of 12/14 bits in the output data stream after
the third rising edge of SCK after the start of conversion
with the rising edge of CONV. The two 12-/14-bit words
are separated by two clock cycles in high impedance
mode. Please note the delay specification from SCK to a
valid SDO. SDO is always guaranteed to be valid by the
next rising edge of SCK. The 32-bit output data stream is
compatible with the 16-bit or 32-bit serial port of most
processors.
1407fb
16
LTC1407/LTC1407A
APPLICATIONS INFORMATION
HARDWARE INTERFACE TO TMS320C54x
The LTC1407/LTC1407A are serial output ADCs whose interface has been designed for high speed buffered serial ports
in fast digital signal processors (DSPs). Figure 6 shows
an example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial data
can be collected in two alternating 1kB segments, in real
time, at the full 3Msps conversion rate of the LTC1407/
LTC1407A. The DSP assembly code sets frame sync mode
at the BFSR pin to accept an external positive going pulse
and the serial clock at the BCLKR pin to accept an external
positive edge clock. Buffers near the LTC1407/LTC1407A
may be added to drive long tracks to the DSP to prevent
corruption of the signal to LTC1407/LTC1407A. This configuration is adequate to traverse a typical system board,
but source resistors at the buffer outputs and termination
resistors at the DSP, may be needed to match the characteristic impedance of very long transmission lines. If
you need to terminate the SDO transmission line, buffer
it first with one or two 74ACxx gates. The TTL threshold
inputs of the DSP port respond properly to the 3V swing
used with the LTC1407/LTC1407A.
3V
VDD
5V
7
VCC
10
CONV
LTC1407/
LTC1407A
9
SCK
SDO
GND
BFSR
TMS320C54x
BCLKR
B13
8
B12
BDR
6
CONV
CLK
3-WIRE SERIAL
INTERFACELINK
1407 F06
0V TO 3V LOGIC SWING
Figure 6. DSP Serial Interface to TMS320C54x
1407fb
17
LTC1407/LTC1407A
APPLICATIONS INFORMATION
;
;
;
;
;
;
;
;
;
;
;
;
;
08-21-03 ******************************************************************
Files: 1407ASIAB.ASM -> 1407A Sine wave collection with Serial Port interface
both channels collected in sequence in the same 2k record
bvectors.asm
buffered mode.
s2k14ini.asm
2k buffer size.
unipolar mode
Works 16 or 64 clock frames.
negative edge BCLKR
negative BFSR pulse
-0 data shifted
1’ cable from counter to CONV at DUT
2’ cable from counter to CLK at DUT
***************************************************************************
.width
160
.length 110
.title “sineb0 BSP in auto buffer mode”
.mmregs
.setsect “.text”,
0x500,0
;Set address
.setsect “vectors”, 0x180,0
;Set address
.setsect “buffer”, 0x800,0
;Set address
.setsect “result”, 0x1800,0
;Set address
.text
;.text marks
of executable
of incoming 1407A data
of BSP buffer for clearing
of result for clearing
start of code
start:
;this label seems necessary
;Make sure /PWRDWN is low at J1-9
;to turn off AC01 adc
tim=#0fh
prd=#0fh
tcr = #10h
tspc = #0h
pmst = #01a0h
sp = #0700h
dp = #0
ar2 = #1800h
ar3 = #0800h
ar4 = #0h
call sineinit
sinepeek:
call sineinit
wait
;
goto
;
;
;
;
;
;
;
;
stop timer
stop TDM serial port to AC01
set up iptr. Processor Mode STatus register
init stack pointer.
data page
pointer to computed receive buffer.
pointer to Buffered Serial Port receive buffer
reset record counter
; Double clutch the initialization to insure a proper
; reset. The external frame sync must occur 2.5 clocks
; or more after the port comes out of reset.
wait
————————Buffered Receive Interrupt Routine -————————-
breceive:
ifr = #10h
; clear interrupt flags
TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer
if (NTC) goto bufull
; if this still the first half get next half
bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))
return_enable
1407fb
18
LTC1407/LTC1407A
APPLICATIONS INFORMATION
;
———————mask and shift input data ——————————————
bufull:
b = *ar3+ Vector Table for the ‘C54x DSKplus
10.Jul.96
BSP vectors and Debugger vectors
TDM vectors just return
***************************************************************************
The vectors in this table can be configured for processing external and
internal software interrupts. The DSKplus debugger uses four interrupt
vectors. These are RESET, TRAP2, INT2, and HPIINT.
* DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER *
All other vector locations are free to use. When programming always be sure
the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and
host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the
DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.
1407fb
19
LTC1407/LTC1407A
APPLICATIONS INFORMATION
.title “Vector Table”
.mmregs
reset
nmi
trap2
int0
int1
int2
tint
brint
bxint
trint
txint
int3
hpiint
goto #80h
nop
nop
return_enable
nop
nop
nop
goto #88h
nop
nop
.space 52*16
return_enable
nop
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
nop
goto breceive
nop
nop
nop
goto bsend
nop
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
return_enable
nop
nop
nop
dgoto #0e4h
nop
nop
;00; RESET
* DO NOT MODIFY IF USING DEBUGGER *
;04; non-maskable external interrupt
;08; trap2
* DO NOT MODIFY IF USING DEBUGGER *
;0C-3F: vectors for software interrupts 18-30
;40; external interrupt int0
;44; external interrupt int1
;48; external interrupt int2
;4C; internal timer interrupt
;50; BSP receive interrupt
;54; BSP transmit interrupt
;58; TDM receive interrupt
;5C; TDM transmit interrupt
;60; external interrupt int3
;64; HPIint
* DO NOT MODIFY IF USING DEBUGGER *
1407fb
20
LTC1407/LTC1407A
APPLICATIONS INFORMATION
.space
24*16
;68-7F; reserved area
**********************************************************************
*
(C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996
*
**********************************************************************
*
*
* File: BSPI1407A.ASM BSP initialization code for the ‘C54x DSKplus *
*
for use with 1407A in standard mode
*
*
BSPC and SPC seem interchangeable in the ‘C542
*
*
BSPCE and SPCE seem interchangeable in the ‘C542
*
**********************************************************************
.title “Buffered Serial Port Initialization Routine”
ON
.set 1
OFF
.set !ON
YES
.set 1
NO
.set !YES
BIT_8
.set 2
BIT_10
.set 1
BIT_12
.set 3
BIT_16
.set 0
GO
.set 0x80
**********************************************************************
* This is an example of how to initialize the Buffered Serial Port (BSP).
* The BSP is initialized to require an external CLK and FSX for
* operation. The data format is 16-bits, burst mode, with autobuffering
* enabled. Set the variables listed below to configure the BSP for
* your application.
*
*******************************************************************************************
*LTC1407A timing with 40MHz crystal.
*
*10MHz, divided from 40MHz, forced to CLKIN by 1407A board.
*
*Horizontal scale is 6.25ns/chr or 25ns period at BCLKR
*
*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/
~~~~~~~~~~~*
*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/
~\_/~\_/~*
*BDR
Pin J1-26 _—_—_——_—> 1)|((Format & 2)
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