LTC1417
Low Power 14-Bit, 400ksps
Sampling ADC Converter
with Serial I/O
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FEATURES
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DESCRIPTIO
The LTC ®1417 is a low power, 400ksps, 14-bit A/D converter. This versatile device can operate from a single 5V or
±5V supplies. An onboard high performance sample-andhold, a precision reference and internal trimming minimize
external circuitry requirements. The low 20mW power
dissipation is made even more attractive with two userselectable power shutdown modes.
16-Pin Narrow SSOP Package (SO-8 Footprint)
Sample Rate: 400ksps
±1.25LSB INL and ±1LSB DNL Max
Power Dissipation: 20mW (Typ)
Single Supply 5V or ±5V Operation
Serial Data Output
No Missing Codes Over Temperature
Power Shutdown: Nap and Sleep
External or Internal Reference
Differential High Impedance Analog Input
Input Range: 0V to 4.096V or ±2.048V
81dB S/(N + D) and – 95dB THD at Nyquist
The LTC1417 converts 0V to 4.096V unipolar inputs when
using a 5V supply and ±2.048V bipolar inputs when using
±5V supplies. DC specs include ±1.25LSB INL, ±1LSB
DNL and no missing codes over temperature. Outstanding
AC performance includes 81dB S/(N + D) and – 95dB THD
at a Nyquist input frequency of 200kHz.
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APPLICATIO S
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High Speed Data Acquisition
Digital Signal Processing
Isolated Data Acquisition Systems
Audio and Telecom Processing
Spectrum Instrumentation
, LTC and LT are registered trademarks of Linear Technology Corporation.
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The internal clock is trimmed for 2µs maximum conversion time. A separate convert start input and a data ready
signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
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EQUIVALE T BLOCK DIAGRA
A 400kHz, 14-Bit Sampling A/D Converter in a Narrow 16-Lead SSOP Package
5V
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
10µF
16
VDD
14
LTC1417
REFCOMP
2
4
S/H
14-BIT ADC
6
14
SERIAL
PORT
4.096V
7
8
9
EXTCLKIN
SCLK
CLKOUT
DOUT
BUFFER
10µF
VREF
12
3
8k
2.5V
REFERENCE
TIMING AND
LOGIC
1µF
14
BUSY
12
RD
13
CONVST
11
SHDN
1417 TA01
5
AGND
15
VSS
10
(0V OR – 5V)
DGND
74
68
10
62
8
6
S/(N + D) (dB)
AIN–
80
1
EFFECTIVE BITS
AIN+
86
4
2
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
1417 TA02
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LTC1417
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PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
Positive Supply Voltage (VDD) .................................. 6V
Negative Supply Voltage (VSS)
Bipolar Operation Only .......................... – 6V to GND
Total Supply Voltage (VDD to VSS)
Bipolar Operation Only ....................................... 12V
Analog Input Voltage (Note 3)
Unipolar Operation .................. – 0.3V to (VDD + 0.3V)
Bipolar Operation............ (VSS – 0.3) to (VDD + 0.3V)
Digital Input Voltage (Note 4)
Unipolar Operation ............................... – 0.3V to 10V
Bipolar Operation.........................(VSS – 0.3V) to 10V
Digital Output Voltage
Unipolar Operation ................... – 0.3 to (VDD + 0.3V)
Bipolar Operation........... (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1417AC/LTC1417C ........................... 0°C to 70°C
LTC1417AI/LTC1417I ......................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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ABSOLUTE
ORDER
PART NUMBER
TOP VIEW
AIN+
1
16 VDD
AIN–
2
15 VSS
VREF
3
14 BUSY
REFCOMP
4
13 CONVST
AGND
5
12 RD
EXTCLKIN
6
11 SHDN
SCLK
7
10 DGND
CLKOUT
8
9
LTC1417ACGN
LTC1417CGN
LTC1417AIGN
LTC1417IGN
GN PART MARKING
DOUT
1417A
1417
1417AI
1417I
GN PACKAGE
16-LEAD (NARROW) PLASTIC SSOP
TJMAX = 110°C, θJA = 95°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CO VERTER CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Specifications are measured while using the internal reference unless
otherwise noted. (Notes 5, 6)
PARAMETER
CONDITIONS
MIN
LTC1417
TYP MAX
LTC1417A
MIN TYP MAX
UNITS
Resolution
●
14
14
Bits
No Missing Codes
●
13
14
Bits
Integral Linearity Error
(Note 7)
Differential Linearity Error
Transition Noise
●
±0.8
±0.5 ±1.25
LSB
●
±0.7 ±1.5
±0.35
LSB
0.33
0.33
(Note 12)
±2
±1
LSBRMS
Offset Error
External Reference (Note 8)
±5
±20
±2
±10
LSB
Full-Scale Error
Internal Reference
External Reference = 2.5V
±15
±5
±60
±30
±15
±5
±60
±15
LSB
LSB
Full-Scale Tempco
IOUT(REF) = 0, Internal Reference, 0°C ≤ TA ≤ 70°C
IOUT(REF) = 0, Internal Reference, – 40°C ≤ TA ≤ 85°C
IOUT(REF) = 0, External Reference
±15
●
±10
±20
±1
±5
ppm/°C
ppm/°C
ppm/°C
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A ALOG I PUT
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
4.75V ≤ VDD ≤ 5.25V (Unipolar)
4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V (Bipolar)
●
●
IIN
Analog Input Leakage Current
CONVST = High
●
2
MIN
TYP
MAX
0 to 4.096
±2.048
UNITS
V
V
±1
µA
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LTC1417
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A ALOG I PUT
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
CIN
Analog Input Capacitance
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
tACQ
Sample-and-Hold Acquisition Time
tAP
Sample-and-Hold Aperture Time
tjitter
Sample-and-Hold Aperture Time Jitter
CMRR
Analog Input Common Mode Rejection Ratio
MIN
TYP
MAX
UNITS
14
3
150
●
pF
pF
500
ns
–1.5
0V < (AIN+ = AIN–) < 4.096V (Unipolar)
– 2.048V < (AIN+ = AIN–) < 2.048V (Bipolar)
ns
5
psRMS
65
65
dB
dB
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DY A IC ACCURACY The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
100kHz Input Signal
79
81
dB
THD
Total Harmonic Distortion
100kHz Input Signal, First Five Harmonics
– 85
– 95
dB
SFDR
Spurious Free Dynamic Range
200kHz Input Signal
– 98
dB
IMD
Intermodulation Distortion
fIN1 = 97.3kHz, fIN2 = 104.6kHz
– 97
Full Power Bandwidth
S/(N + D) ≥ 77dB
Full Linear Bandwidth
TYP
MAX
UNITS
dB
10
MHz
0.8
MHz
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I TER AL REFERE CE CHARACTERISTICS
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
IOUT = 0, 0°C ≤ TA ≤ 70°C
IOUT = 0, – 40°C ≤ TA ≤ 85°C
±10
±20
ppm/°C
ppm/°C
VREF Line Regulation
4.75V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.75V
0.05
0.05
LSB/V
LSB/V
VREF Output Resistance
0.1mA ≤ |IOUT| ≤ 0.1mA
8
●
MIN
TYP
MAX
UNITS
2.480
2.500
2.520
V
kΩ
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
●
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VDD = 4.75V, IO = – 10µA
VDD = 4.75V, IO = – 200µA
●
VDD = 4.75V, IO = 160µA
VDD = 4.75V, IO = – 1.6mA
●
2.4
V
1.4
pF
4.74
V
V
4.0
0.05
0.10
0.4
V
V
IOZ
High-Z Output Leakage DOUT, CLKOUT
VOUT = 0V to VDD, RD High
●
±10
µA
COZ
High-Z Output Capacitance DOUT, CLKOUT
RD High (Note 9)
●
15
pF
ISOURCE
Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
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LTC1417
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POWER REQUIRE E TS
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
UNITS
5.25
V
VDD
Positive Supply Voltage (Notes 10, 11)
VSS
Negative Supply Voltage (Note 10)
Bipolar Only (VSS = 0V for Unipolar)
IDD
Positive Supply Current
Unipolar, RD High (Note 5)
Bipolar, RD High (Note 5)
SHDN = 0V, RD = 0V
SHDN = 0V, RD = 5V
●
●
4.0
4.3
750
0.1
5.5
6.0
mA
mA
µA
µA
Nap Mode
Sleep Mode
4.75
MAX
– 4.75
– 5.25
V
ISS
Negative Supply Current
Nap Mode
Sleep Mode
Bipolar, RD High (Note 5)
SHDN = 0V, RD = 0V
SHDN = 0V, RD = 5V
●
2.0
0.7
1.5
2.8
mA
µA
nA
PDIS
Power Dissipation
Unipolar
Bipolar
●
●
20.0
31.5
27.5
44
mW
mW
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TI I G CHARACTERISTICS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
fSAMPLE(MAX)
Maximum Sampling Frequency
CONDITIONS
●
MIN
TYP
MAX
tCONV
Conversion Time
●
1.8
2.25
µs
tACQ
Acquisition Time
●
150
500
ns
tACQ + tCONV
Acquisition Plus Conversion Time
●
2.1
2.5
µs
t1
SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode
(Note 10)
t2
CONVST Low Time
(Notes 10, 11)
●
t3
CONVST to BUSY Delay
CL = 25pF
●
t4
Data Ready Before BUSY↑
CL = 25pF
●
7
t5
Delay Between Conversions
(Note 10)
●
250
ns
t6
Wait Time RD↓ After BUSY↑
●
–5
ns
t7
Data Access Time After RD↓
400
kHz
500
ns
40
ns
35
CL = 25pF
UNITS
70
12
ns
ns
15
30
40
ns
ns
20
●
40
55
ns
ns
35
ns
●
CL = 100pF
t8
Bus Relinquish Time
●
t9
RD Low Time
●
t7
ns
t10
CONVST High Time
●
40
ns
t11
Delay Time, SCLK↓ to DOUT Valid
CL = 25pF
●
t12
Time from Previous Data Remain Valid After SCLK↓
CL = 25pF
●
5
fSCLK
Shift Clock Frequency
(Note 13)
●
0
fEXTCLKIN
External Conversion Clock Frequency
●
0.05
tdEXTCLKIN
Delay Time, CONVST↓ to External Conversion Clock Input (Note 9)
●
15
40
10
ns
ns
20
MHz
9
MHz
20
µs
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LTC1417
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TI I G CHARACTERISTICS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
tH SCLK
SCLK High Time
(Note 9)
●
10
ns
tL SCLK
SCLK Low Time
(Note 9)
●
10
ns
tH EXTCLKIN
EXTCLKIN High Time
●
0.04
tL EXTCLKIN
EXTCLKIN Low Time
●
0.04
fCLKOUT
Conversion Clock Output Frequency
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA without latchup if the pin is driven below VSS (ground
for unipolar mode) or above VDD.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN– grounded.
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SIGNAL/(NOISE + DISTORTION) (dB)
DNL ERROR (LSBs)
INL (LSBs)
0
– 0.5
–1.0
–1.0
0
4096
8192
12288
16384
OUTPUT CODE
1417 G01
MHz
fEXTCLKIN
MHz
90
0.5
–0.5
µs
20
9.4
S/(N + D) vs Input Frequency
and Amplitude
1.0
0.5
µs
(TA = 25°C, unless otherwise specified)
Differential Nonlinearity
vs Output Code
1.0
UNITS
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 625ns after
conversion start or after BUSY rises.
Note 12: Typical RMS noise at the code transitions. See Figure 2 for
histogram.
Note 13: t11 of 40ns maximum allows fSCLK up to 10MHz for rising
capture with 50% duty cycle. fSCLK up to 20MHz for falling capture with
5ns setup time.
TYPICAL PERFOR A CE CHARACTERISTICS
Typical INL Curve
MAX
20
Internal Conversion
Clock Mode (EXTCLKIN = 5V)
External Conversion Clock Mode
(EXTCLKIN is Driven by an External
Conversion Clock Input)
0
TYP
80
VIN = 0dB
70
60
VIN = –20dB
50
40
30
VIN = –60dB
20
10
0
0
4096
12288
8192
OUTPUT CODE
16384
1417 G02
1k
100k
10k
INPUT FREQUENCY (Hz)
1M
1417 G03
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LTC1417
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TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C, unless otherwise specified)
Signal-to-Noise Ratio
vs Input Frequency
70
60
50
40
30
20
10
0
10k
100k
INPUT FREQUENCY (Hz)
– 20
– 40
– 60
– 80
THD
–100
3RD
–120
1M
2ND
1
–80
–100
1k
200
Intermodulation Distortion Plot
0
–40
– 40
–60
–80
–120
–100
–120
0
50
VDD
DGND
120
Input Offset Voltage Shift
vs Source Resistance
10
60
50
40
30
20
10
10M
1417 G10
9
8
7
6
5
4
3
2
1
0
0
10k
100k
1M
RIPPLE FREQUENCY (Hz)
20 40 60 80 100 120 140 160 180 200
FREQUENCY (kHz)
1417 G09
CHANGE IN OFFSET VOTLAGE (LSB)
COMMON MODE REJECTION (dB)
80
1k
0
200
100
150
FREQUENCY (kHz)
70
60
100
– 80
1417 G08
0
VSS
– 60
Input Common Mode Rejection
vs Input Frequency
40
1M
1417 G06
fSAMPLE = 400kHz
fIN1 = 97.303466kHz
– 20 fIN2 = 104.632568kHz
VIN = 4.096VP-P
Power Supply Feedthrough
vs Ripple Frequency
VRIPPLE = 60mV
fSAMPLE = 400kHz
20 fIN = 200kHz
10k
100k
INPUT FREQUENCY (Hz)
fSAMPLE = 400kHz
fIN = 197.949188kHz
–20 SFDR = –98dB
SINAD = 81.1dB
1417 G07
FEEDTHROUGH (dB)
–120
–100
100
150
FREQUENCY (kHz)
–100
AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
–60
50
–80
0
fSAMPLE = 400kHz
fIN = 10.05859375kHz
SFDR = –97.44dB
SINAD = 81.71dB
0
–60
Nonaveraged, 4096 Point FFT,
Input Frequency = 200kHz
–40
–120
–40
1417 G05
Nonaveraged, 4096 Point FFT,
Input Frequency = 10kHz
–20
–20
1000
10
100
INPUT FREQUENCY (kHz)
1417 G04
0
SPURIOUS FREE DYNAMIC RANGE (dB)
SIGNAL-TO-NOISE RATIO (dB)
80
0
0
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
90
1k
Spurious-Free Dynamic Range
vs Input Frequency
Distortion vs Input Frequency
1
100
10
INPUT FREQUENCY (kHz)
1000
1417 G11
1
100
1k
10k 100k
10
INPUT SOURCE RESISTANCE (Ω)
1M
1417 G12
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LTC1417
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TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C, unless otherwise specified)
VDD Supply Current vs
Temperature (Bipolar Mode)
3.0
5
5
2.5
4
3
2
1
VSS SUPPLY CURRENT (mA)
6
0
–75 –50 –25
4
3
2
1
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
4.0
4.0
2.0
1.5
1.0
0 25 50 75 100 125 150
TEMPERATURE (°C)
VSS Supply Current vs Sampling
Frequency (Bipolar Mode)
2.5
3.5
3.0
2.5
2.0
1.5
1.0
2.0
1.5
1.0
0.5
0.5
0.5
0
0.5
1417 G15
VSS SUPPLY CURRENT (mA)
4.5
VDD SUPPLY CURRENT (mA)
5.0
4.5
2.5
1.0
VDD Supply Current vs Sampling
Frequency (Bipolar Mode)
5.0
3.0
1.5
1417 G14
VDD Supply Current vs Sampling
Frequency (Unipolar Mode)
3.5
2.0
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
1417 G13
VDD SUPPLY CURRENT (mA)
VSS Supply Current vs
Temperature (Bipolar Mode)
6
VDD SUPPLY CURRENT (mA)
VDD SUPPLY CURRENT (mA)
VDD Supply Current vs
Temperature (Unipolar Mode)
0
0
50 100 150 200 250 300 350 400 450 500
SAMPLING FREQUENCY (kHz)
0
50 100 150 200 250 300 350 400 450 500
SAMPLING FREQUENCY (kHz)
1417 G16
1417 G17
0
0
50 100 150 200 250 300 350 400 450 500
SAMPLING FREQUENCY (kHz)
1417 G18
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PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input.
AIN– (Pin 2): Negative Analog Input.
VREF (Pin 3): 2.50V Reference Output. Bypass to AGND
with 1µF.
REFCOMP (Pin 4): 4.096V Reference Output. Bypass to
AGND using 10µF tantalum in parallel with 0.1µF ceramic.
AGND (Pin 5): Analog Ground.
EXTCLKIN (Pin 6): External Conversion Clock Input. A 5V
input will enable the internal conversion clock.
SCLK (Pin 7): Data Clock Input.
CLKOUT (Pin 8): Conversion Clock Output.
DOUT (Pin 9): Serial Data Output.
DGND (Pin 10): Digital Ground.
SHDN (Pin 11): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by RD. RD = 0V for
Nap mode and RD = 5V for Sleep mode.
RD (Pin 12): Read Input. This enables the output drivers.
RD also sets the shutdown mode when SHDN goes low.
RD and SHDN low selects the quick wake-up Nap mode,
RD high and SHDN low selects Sleep mode.
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LTC1417
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PIN FUNCTIONS
CONVST (Pin 13): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
BUSY (Pin 14): The BUSY output shows the converter
status. It is low when a conversion is in progress.
VSS (Pin 15): Negative Supply, –5V for Bipolar Operation.
Bypass to AGND using 10µF tantalum in parallel with
0.1µF ceramic. Analog ground for unipolar operation.
VDD (Pin 16): 5V Positive Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF ceramic.
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
1k
DOUT
DOUT
DOUT
1k
CL
DOUT
DGND
30pF
1k
CL
30pF
DGND
A) HI-Z TO VOH AND VOL TO VOH
A) VOH TO HI-Z
B) HI-Z TO VOL AND VOH TO VOL
B) VOL TO HI-Z
1417 TC02
1417 TC01
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FUNCTIONAL BLOCK DIAGRA
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CSAMPLE
AIN+
1
16
CSAMPLE
AIN–
VREF
15
2
3
8k
ZEROING SWITCHES
2.5V REF
VDD
VSS
(0V FOR UNIPOLAR MODE
–5V FOR BIPOLAR MODE)
+
REF AMP
COMP
14-BIT CAPACITIVE DAC
–
REFCOMP
(4.096V)
AGND
DGND
4
5
10
14
SUCCESSIVE APPROXIMATION
REGISTER
9
SHIFT REGISTER
7
INTERNAL
CLOCK
MUX
6
EXTCLKIN
DOUT
SCLK
CONTROL LOGIC
11
SHDN
13
CONVST
12
RD
8
14
1417 BD
CLKOUT BUSY
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LTC1417
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APPLICATIONS INFORMATION
The LTC1417 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit serial output. The ADC is complete with a precision reference and an internal clock. The
control logic provides easy interface to microprocessors
and DSPs (please refer to Digital Interface section for the
data format).
Conversion start is controlled by the CONVST input. At the
start of the conversion, the successive approximation
register (SAR) is reset. Once a conversion cycle has
begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the AIN+ and AIN– inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 500ns will provide enough time for the sampleand-hold capacitors to acquire the analog signal. During
the convert phase, the comparator zeroing switches open,
placing the comparator in compare mode. The input
switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively
compared with the binary weighted charges supplied by
the differential capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 14-bit data word) that
represent the difference of AIN+ and AIN– are output
through the serial pin DOUT.
DC Performance
One way of measuring the transition noise associated with
a high resolution ADC is to use a technique where a DC
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conversions. For example in Figure 2, the distribution of output
code is shown for a DC input that has been digitized 4096
times. The distribution is Gaussian and the RMS code
transition is about 0.33LSB.
4000
3500
3000
2500
COUNTS
CONVERSION DETAILS
2000
1500
1000
500
AIN+
AIN–
CSAMPLE
SAMPLE
+
0
–1
0
1
2
1417 F02
CSAMPLE–
SAMPLE
–2
CODE
ZEROING SWITCHES
HOLD
HOLD
Figure 2. Histogram for 4096 Conversions
HOLD
HOLD
DYNAMIC PERFORMANCE
CDAC+
+
CDAC–
VDAC+
COMP
–
VDAC–
14
SAR
SHIFT
REGISTER
DOUT
1417 F01
Figure 1. Simplified Block Diagram
The LTC1417 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and
noise performance at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADC’s spectral content can be
examined for frequencies beyond the fundamental.
Figure 3 shows a typical LTC1417 FFT plot.
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APPLICATIONS INFORMATION
0
fSAMPLE = 400kHz
fIN = 10.05859375kHz
SFDR = –97.44dB
SINAD = 81.71dB
AMPLITUDE (dB)
–20
–40
–60
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
ENOB (N) = [S/(N + D) – 1.76]/6.02
–80
–100
–120
Effective Number of Bits
0
50
100
150
FREQUENCY (kHz)
200
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 400kHz, the LTC1417 maintains near ideal ENOBs
up to the Nyquist input frequency of 200kHz (refer to
Figure 4).
1417 G07
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Figure 3a. LTC1417 Nonaveraged, 4096 Point FFT,
Input Frequency = 10kHz
86
80
12
74
68
EFFECTIVE BITS
AMPLITUDE (dB)
fSAMPLE = 400kHz
fIN = 197.949188kHz
–20 SFDR = –98dB
SINAD = 81.1dB
–40
10
62
8
6
–60
4
–80
2
1k
–100
–120
10k
100k
INPUT FREQUENCY (Hz)
S/(N + D) (dB)
0
1M
1417 TA02
0
50
100
150
FREQUENCY (kHz)
200
Figure 4. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
1417 G08
Figure 3b. LTC1417 Nonaveraged, 4096 Point FFT,
Input Frequency = 200kHz
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 3b shows a typical spectral content with
a 400kHz sampling rate and a 200kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 200kHz.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
V22 + V32 + V42 + ...Vn2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is
shown in Figure 5. The LTC1417 has good distortion
performance up to the Nyquist frequency and beyond.
THD = 20Log
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AMPLITUDE (dB BELOW THE FUNDAMENTAL)
APPLICATIONS INFORMATION
(
0
– 20
– 40
)
Amplitude at fa
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
– 80
THD
–100
3RD
2ND
1
10
100
INPUT FREQUENCY (kHz)
1000
1417 G05
Figure 5. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, 2nd order IMD terms include (fa ± fb). If
the two input sine waves are equal in magnitude, the value
(in decibels) of the 2nd-order IMD products can be
expressed by the following formula:
0
fSAMPLE = 400kHz
fIN1 = 97.303466kHz
– 20 fIN2 = 104.632568kHz
VIN = 4.096VP-P
AMPLITUDE (dB)
(
Amplitude at fa ± fb
Peak Harmonic or Spurious Noise
– 60
–120
)
IMD fa + fb = 20Log
– 40
– 60
– 80
–100
–120
0
20 40 60 80 100 120 140 160 180 200
FREQUENCY (kHz)
1417 G09
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is the input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB from a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits).
The LTC1417 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with
frequencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1417 are easy to
drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and
AIN– inputs are sampled at the same instant. Any
unwanted signal that is common to both inputs will be
reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1417
inputs can be driven directly. As source impedance
increases, so will acquisition time (see Figure 7). For
minimum acquisition time, with high source impedance, a
buffer amplifier must be used. The only requirement is that
the amplifier driving the analog input(s) must settle after
the small current spike before the next conversion starts —
500ns for full throughput rate.
Figure 6. Intermodulation Distortion Plot
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APPLICATIONS INFORMATION
LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current, ±2.5V to ±15V supplies. High AVOL, 1mV
offset and 80ns settling to 1mV (4V step, inverting and
noninverting configurations) make it suitable for fast DC
applications. Excellent AC specifications. Dual and quad
versions are available as LT1361 and LT1362.
ACQUISITION TIME (µs)
100
10
1
LT1468: 90MHz Voltage Feedback Amplifier. ±5V to ±15V
supplies. Lower distortion and noise. Settles to 0.01% in
770ns. Distortion is –115dB to 20kHz.
0.1
0.01
1
10
100
1k
10k
SOURCE RESISTANCE (Ω)
100k
1417 F07
Figure 7. tACQ vs Source Resistance
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, choose an amplifier that
has a low output impedance (
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