LTC2241-12
12-Bit, 210Msps ADC
Features
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Description
Sample Rate: 210Msps
65.5dB SNR
78dB SFDR
1.2GHz Full Power Bandwidth S/H
Single 2.5V Supply
Low Power Dissipation: 585mW
LVDS, CMOS, or Demultiplexed CMOS Outputs
Selectable Input Ranges: ±0.5V or ±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit)
210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit)
170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit)
185Msps: LTC2220-1 (12-Bit)*
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)*
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*
64-Pin 9mm × 9mm QFN Package
Applications
n
n
n
n
The LTC®2241-12 is a 210Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic
range signals. The LTC2241-12 is perfect for demanding
communications applications with AC performance that
includes 65.5dB SNR and 78dB SFDR. Ultralow jitter of
95fsRMS allows IF undersampling with excellent noise
performance.
DC specs include ±0.7LSB INL (typ), ±0.4LSB DNL (typ)
and no missing codes over temperature.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data
rate or two demultiplexed buses running at half data rate
with either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 2.625V.
The ENC+ and ENC – inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance over a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
*LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.
Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
Typical Application
2.5V
SFDR vs Input Frequency
VDD
REFL
ANALOG
INPUT
FLEXIBLE
REFERENCE
+
–
INPUT
S/H
80
OVDD
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
D11
•
•
•
D0
OUTPUT
DRIVERS
CMOS
OR
LVDS
OGND
CLOCK/DUTY
CYCLE
CONTROL
75
70
65
60
55
50
45
40
224112 TA01
ENCODE
INPUT
85
SFDR (dBFS)
REFH
0.5V
TO 2.625V
1V RANGE
2V RANGE
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
224112 G11
224112fc
1
LTC2241-12
Absolute Maximum Ratings
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD)................................................2.8V
Digital Output Ground Voltage (OGND)......... –0.3V to 1V
Analog Input Voltage (Note 3)....... –0.3V to (VDD + 0.3V)
Digital Input Voltage..................... –0.3V to (VDD + 0.3V)
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Power Dissipation..............................................1500mW
Operating Temperature Range
LTC2241C-12............................................. 0°C to 70°C
LTC2241I-12..........................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Pin Configuration
64 GND
63 VDD
62 VDD
61 GND
60 VCM
59 SENSE
58 MODE
57 LVDS
56 OF+/OFA
55 OF–/DA11
54 D11+/DA10
53 D11–/DA9
52 D10+/DA8
51 D10–/DA7
50 OGND
49 OVDD
TOP VIEW
AIN+ 1
AIN+ 2
AIN– 3
AIN– 4
REFHA 5
REFHA 6
REFLB 7
REFLB 8
REFHB 9
REFHB 10
REFLA 11
REFLA 12
VDD 13
VDD 14
VDD 15
GND 16
48 D9+/DA6
47 D9–/DA5
46 D8+/DA4
45 D8–/DA3
44 D7+/DA2
43 D7–/DA1
42 OVDD
41 OGND
40 D6+/DA0
39 D6–/CLKOUTA
38 D5+/CLKOUTB
37 D5–/OFB
36 CLKOUT+/DB11
35 CLKOUT–/DB10
34 OVDD
33 OGND
ENC+ 17
ENC– 18
SHDN 19
OE 20
DO–/DB0 21
DO+/DB1 22
D1–/DB2 23
D1+/DB3 24
OGND 25
OVDD 26
D2–/DB4 27
D2+/DB5 28
D3–/DB6 29
D3+/DB7 30
D4–/DB8 31
D4+/DB9 32
65
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 20°C/W
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2241CUP-12#PBF
LTC2241CUP-12#TRPBF
LTC2241UP-12
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2241IUP-12#PBF
LTC2241IUP-12#TRPBF
LTC2241UP-12
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2241CUP-12
LTC2241CUP-12#TR
LTC2241UP-12
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2241IUP-12
LTC2241IUP-12#TR
LTC2241UP-12
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
224112fc
2
LTC2241-12
Converter Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
●
12
TYP
MAX
UNITS
Bits
Integral Linearity Error
Differential Analog Input (Note 5)
●
–2.3
±0.7
2.3
LSB
Differential Linearity Error
Differential Analog Input
●
–1
±0.4
1
LSB
Offset Error
(Note 6)
●
–15
±5
15
mV
Gain Error
External Reference
●
–3.4
±0.7
3.4
%FS
Offset Drift
±10
µV/C
Full-Scale Drift
Internal Reference
External Reference
±60
±45
ppm/C
ppm/C
Transition Noise
SENSE = 1V
0.74
LSBRMS
Analog Input The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ – AIN–)
2.375V < VDD < 2.625V (Note 7)
VIN, CM
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Input (Note 7)
●
1.2
1.3
V
IIN
Analog Input Leakage Current
0 < AIN+, AIN– < VDD
●
–1
1
µA
ISENSE
SENSE Input Leakage
0V < SENSE < 1V
●
–1
1
µA
IMODE
MODE Pin Pull-Down Current to GND
7
µA
ILVDS
LVDS Pin Pull-Down Current to GND
7
µA
tAP
Sample and Hold Acquisition Delay Time
0.4
ns
tJITTER
Sample and Hold Acquisition Delay Time Jitter
95
fsRMS
1200
MHz
Full Power Bandwidth
MIN
TYP
MAX
UNITS
±0.5 to ±1
●
Figure 8 Test Circuit
1.25
V
Dynamic Accuracy
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
SNR
Signal-to-Noise Ratio (Note 10)
10MHz Input
65.5
dB
64
65.4
dB
140MHz Input
65.4
dB
240MHz Input
65.2
dB
10MHz Input
78
dB
74
dB
140MHz Input
73
dB
240MHz Input
72
dB
70MHz Input
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic
(Note 11)
Spurious Free Dynamic Range
4th Harmonic or Higher
(Note 11)
S/(N+D)
IMD
Signal-to-Noise Plus
Distortion Ratio
(Note 12)
Intermodulation Distortion
70MHz Input
l
l
65
10MHz Input
MAX
UNITS
87
dB
87
dB
87
dB
240MHz Input
87
dB
10MHz Input
65.4
dB
70MHz Input
l
74
140MHz Input
65.2
dB
140MHz Input
65.1
dB
240MHz Input
64.9
dB
70MHz Input
fIN1 = 135MHz, fIN2 = 140MHz
l
62.1
81
dBc
224112fc
3
LTC2241-12
Internal Reference Characteristics
(Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM Output Voltage
IOUT = 0
1.225
1.25
1.275
V
VCM Output Tempco
±35
ppm/°C
VCM Line Regulation
2.375V < VDD < 2.625V
3
mV/V
VCM Output Resistance
–1mA < IOUT < 1mA
2
Ω
Digital Inputs and Digital Outputs
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC +, ENC –)
VID
Differential Input Voltage
(Note 7)
●
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 7)
●
1.2
RIN
Input Resistance
CIN
Input Capacitance
(Note 7)
V
1.5
1.5
2.0
V
V
4.8
kΩ
2
pF
LOGIC INPUTS (OE, SHDN)
VIH
High Level Input Voltage
VDD = 2.5V
●
VIL
Low Level Input Voltage
VDD = 2.5V
●
IIN
Input Current
VIN = 0V to VDD
●
CIN
Input Capacitance
(Note 7)
1.7
V
–10
0.7
V
10
µA
3
pF
LOGIC OUTPUTS (CMOS MODE)
OVDD = 2.5V
COZ
Hi-Z Output Capacitance
OE = High (Note 7)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
37
mA
ISINK
Output Sink Current
VOUT = 2.5V
23
mA
VOH
High Level Output Voltage
IO = –10µA
IO = –500µA
2.495
2.45
V
V
VOL
Low Level Output Voltage
IO = 10µA
IO = 500µA
0.005
0.07
V
V
VOH
High Level Output Voltage
IO = –500µA
1.75
V
VOL
Low Level Output Voltage
IO = 500µA
0.07
V
OVDD = 1.8V
LOGIC OUTPUTS (LVDS MODE)
VOD
Differential Output Voltage
100Ω Differential Load
●
247
350
454
VOS
Output Common Mode Voltage
100Ω Differential Load
●
1.125
1.250
1.375
mV
V
224112fc
4
LTC2241-12
Power Requirements
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
VDD
Analog Supply Voltage
(Note 8)
PSLEEP
Sleep Mode Power
SHDN = High, OE = High, No CLK
1
mW
PNAP
Nap Mode Power
SHDN = High, OE = Low, No CLK
28
mW
●
MIN
TYP
MAX
UNITS
2.375
2.5
2.625
V
LVDS OUTPUT MODE
OVDD
Output Supply Voltage
IVDD
Analog Supply Current
(Note 8)
●
IOVDD
Output Supply Current
●
58
70
mA
PDISS
Power Dissipation
●
710
805
mW
2.5
2.625
226
252
●
2.375
2.5
2.625
226
252
V
mA
CMOS OUTPUT MODE
OVDD
Output Supply Voltage
(Note 8)
●
IVDD
Analog Supply Current
(Note 7)
●
PDISS
Power Dissipation
0.5
585
V
mA
mW
Timing Characteristics
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
fS
Sampling Frequency
(Note 8)
●
MIN
1
tL
ENC Low Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
●
2.26
1.5
tH
ENC High Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
●
2.26
1.5
tAP
Sample-and-Hold Aperture Delay
tOE
Output Enable Delay
TYP
MAX
UNITS
210
MHz
2.38
2.38
500
500
ns
ns
2.38
2.38
500
500
ns
ns
0.4
(Note 7)
●
ns
5
10
ns
LVDS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
●
1
1.7
2.8
ns
tC
ENC to CLKOUT Delay
(Note 7)
●
1
1.7
2.8
ns
DATA to CLKOUT Skew
(tC – tD) (Note 7)
●
–0.6
0
0.6
ns
Rise Time
0.5
ns
Fall Time
0.5
ns
Pipeline Latency
5
Cycles
CMOS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
●
1
1.7
2.8
ns
tC
ENC to CLKOUT Delay
(Note 7)
●
1
1.7
2.8
ns
DATA to CLKOUT Skew
(tC – tD) (Note 7)
●
–0.6
0
0.6
ns
Pipeline
Latency
Full Rate CMOS
Demuxed Interleaved
Demuxed Simultaneous
5
Cycles
5
Cycles
5 and 6
Cycles
224112fc
5
LTC2241-12
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 2.5V, fSAMPLE = 210MHz, LVDS outputs, differential
ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from
a “best straight line” fit to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
Note 9: VDD = 2.5V, fSAMPLE = 210MHz, differential ENC+/ENC– = 2VP-P
sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF.
Note 10: SNR minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.3dB lower.
Note 11: SFDR minimum values are for LVDS mode. Typical values are for
both LVDS and CMOS modes.
Note 12: SINAD minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.3dB lower.
Typical Performance Characteristics
8192 Point FFT, fIN = 5MHz,
–1dB, 2V Range, LVDS Mode
Differential Nonlinearity
1.0
0
0.8
0.8
–10
0.6
0.6
–20
0.4
0.4
–30
0.2
0.2
0
–0.2
AMPLITUDE (dB)
1.0
DNL (LSB)
INL (LSB)
Integral Nonlinearity
(TA = 25°C unless otherwise noted, Note 4)
0
–0.2
–40
–50
–60
–70
–0.4
–0.4
–0.6
–0.6
–90
–0.8
–0.8
–100
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
224112 G01
–1.0
–80
0
1024
2048
3072
OUTPUT CODE
4096
224112 G02
–110
0
20
40
60
80
FREQUENCY (MHz)
100
224112 G03
224112fc
6
LTC2241-12
Typical Performance Characteristics
8192 Point FFT, fIN = 140MHz,
–1dB, 2V Range, LVDS Mode
8192 Point FFT, fIN = 240MHz,
–1dB, 2V Range, LVDS Mode
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
AMPLITUDE (dB)
0
–10
AMPLITUDE (dB)
AMPLITUDE (dB)
8192 Point FFT, fIN = 70MHz,
–1dB, 2V Range, LVDS Mode
(TA = 25°C unless otherwise noted, Note 4)
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–90
–90
–100
–100
–100
–110
0
20
–110
100
40
60
80
FREQUENCY (MHz)
–80
0
20
–110
8192 Point FFT, fIN = 500MHz,
–1dB, 1V Range, LVDS Mode
0
–10
–20
–20
–20
–30
–30
–30
–70
AMPLITUDE (dB)
0
–10
AMPLITUDE (dB)
0
–60
–40
–50
–60
–70
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
20
–110
100
40
60
80
FREQUENCY (MHz)
–80
0
20
SNR vs Input Frequency, –1dB,
LVDS Mode
85
66
80
65
75
SFDR (dBFS)
SNR (dBFS)
2V RANGE
62
61
60
59
58
224112 G10
40
60
80
FREQUENCY (MHz)
60
55
40
100
SFDR (HD4+) vs Input Frequency,
–1dB, LVDS Mode
90
2V RANGE
85
65
45
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
20
95
70
50
1V RANGE
0
224112 G09
SFDR (HD2 and HD3) vs Input
Frequency, –1dB, LVDS Mode
67
63
–110
224112 G08
224112 G07
64
100
40
60
80
FREQUENCY (MHz)
1V RANGE
SFDR (dBFS)
0
100
–40
–80
–110
40
60
80
FREQUENCY (MHz)
224112 G06
–10
–50
20
8192 Point 2-Tone FFT,
fIN = 135MHz and 140MHz,
–1dB, 2V Range, LVDS Mode
8192 Point FFT, fIN = 1GHz,
–1dB, 1V Range, LVDS Mode
–40
0
224112 G05
224112 G04
AMPLITUDE (dB)
100
40
60
80
FREQUENCY (MHz)
1V RANGE
80
75
70
2V RANGE
65
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
224112 G11
60
0 100 200 300 400 500 600 700 800 9001000
INPUT FREQUENCY (MHz)
224112 G12
224112fc
7
LTC2241-12
Typical Performance Characteristics
SFDR and SNR vs Sample Rate,
2V Range, fIN = 30MHz, –1dB,
LVDS Mode
SFDR vs Input Level, fIN = 70MHz,
2V Range
80
SFDR
80
75
70
SNR
65
40
30
55
10
200
150
100
SAMPLE RATE (Msps)
250
dBc
50
20
50
64
60
60
0
65
dBFS
70
SFDR (dBc AND dFBS)
85
66
SNR (dBFS)
90
SFDR AND SNR (dBFS)
SNR vs SENSE, fIN = 5MHz, –1dB
90
95
50
(TA = 25°C unless otherwise noted, Note 4)
0
–50
60
–40
–20
–30
–10
INPUT LEVEL (dBFS)
240
60
230
50
1V RANGE
200
0.8
0.9
1
224112 G15
LVDS OUTPUTS
OVDD = 2.5V
30
CMOS OUTPUTS
OVDD = 1.8V
10
180
100
0.7
SENSE PIN (V)
20
190
50
0.6
40
2V RANGE
210
0
59
0.5
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
IOVDD (mA)
IVDD (mA)
0
224112 G14
IVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
170
62
61
224112 G13
220
63
200
150
SAMPLE RATE (Msps)
250
224112 G16
0
0
50
100
150
200
SAMPLE RATE (Msps)
250
224112 G17
224112fc
8
LTC2241-12
Pin Functions
(CMOS Mode)
AIN+ (Pins 1, 2): Positive Differential Analog Input.
AIN – (Pins 3, 4): Negative Differential Analog Input.
REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins
7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins
5, 6 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins
11, 12 with 0.1µF ceramic chip capacitor. Do not connect
to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5,
6 with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC+ (Pin 17): Encode Input. Conversion starts on the
positive edge.
ENC – (Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended encode signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation with the outputs at
high impedance. Connecting SHDN to VDD and OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin function.
DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31,
32, 35, 36): Digital Outputs, B Bus. DB11 is the MSB. At
high impedance in full rate CMOS mode.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip
capacitor.
OFB (Pin 37): Over/Under Flow Output for B Bus. High
when an over or under flow has occurred. At high impedance in full rate CMOS mode.
CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux
mode with interleaved update, latch B bus data on the falling edge of CLKOUTB. In demux mode with simultaneous
update, latch B bus data on the rising edge of CLKOUTB.
This pin does not become high impedance in full rate
CMOS mode.
CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A
bus data on the falling edge of CLKOUTA.
DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53,
54, 55): Digital Outputs, A Bus. DA11 is the MSB.
OFA (Pin 56): Over/Under Flow Output for A Bus. High
when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demux CMOS mode with simultaneous
update. Connecting LVDS to 2/3VDD selects demux CMOS
mode with interleaved update. Connecting LVDS to VDD
selects LVDS mode.
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3VDD selects offset
binary output format and turns the clock duty cycle stabilizer
on. Connecting MODE to 2/3VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer on.
Connecting MODE to VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. Connecting SENSE to VDD selects the internal
reference and a ±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of ±VSENSE. ±1V is the largest valid
input range.
VCM (Pin 60): 1.25V Output and Input Common Mode
Bias. Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
224112fc
9
LTC2241-12
pin functions
(LVDS Mode)
AIN+ (Pins 1, 2): Positive Differential Analog Input.
AIN– (Pins 3, 4): Negative Differential Analog Input.
REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins
7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins
5, 6 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins
11, 12 with 0.1µF ceramic chip capacitor. Do not connect
to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5,
6 with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC+ (Pin 17): Encode Input. Conversion starts on the
positive edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended encode signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation with the outputs at
high impedance. Connecting SHDN to VDD and OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin function.
D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29,
30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51,
52, 53, 54): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS
receiver. D11–/D11+ is the MSB.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip
capacitor.
CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid
Output. Latch data on rising edge of CLKOUT–, falling
edge of CLKOUT+.
OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output.
High when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demux CMOS mode with simultaneous
update. Connecting LVDS to 2/3VDD selects demux CMOS
mode with interleaved update. Connecting LVDS to VDD
selects LVDS mode.
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3VDD selects offset
binary output format and turns the clock duty cycle stabilizer
on. Connecting MODE to 2/3VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer on.
Connecting MODE to VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. Connecting SENSE to VDD selects the internal
reference and a ±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of ±VSENSE. ±1V is the largest valid
input range.
VCM (Pin 60): 1.25V Output and Input Common Mode
Bias. Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
224112fc
10
LTC2241-12
Functional Block Diagram
AIN+
AIN–
VCM
2.2μF
VDD
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
GND
1.25V
REFERENCE
SHIFT REGISTER
AND CORRECTION
RANGE
SELECT
SENSE
FIFTH PIPELINED
ADC STAGE
REFH
REF
BUF
REFL
INTERNAL CLOCK SIGNALS
OVDD
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DIFF
REF
AMP
REFLB REFHA
2.2μF
0.1μF
ENC
+
ENC–
OGND
M0DE LVDS SHDN
•
•
•
OUTPUT
DRIVERS
REFLA REFHB
0.1μF
1μF
CONTROL
LOGIC
+ OF
–+
– D11
+
–+
–
D0
CLKOUT
224112 F01
OE
1μF
Figure 1. Functional Block Diagram
224112fc
11
LTC2241-12
Timing Diagrams
LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+1
tL
ENC–
ENC+
tD
N–5
D0-D11, OF
N–4
N–3
N–2
N–1
tC
CLKOUT–
CLKOUT+
224112 TD01
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
tL
N+1
ENC–
ENC+
tD
N–5
DA0-DA11, OFA
CLKOUTB
N–4
N–3
N–2
N–1
tC
CLKOUTA
DB0-DB11, OFB
HIGH IMPEDANCE
224112 TD02
224112fc
12
LTC2241-12
timing diagrams
Demultiplexed CMOS Outputs with Interleaved Update
All Outputs Are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
tL
N+1
ENC–
ENC+
tD
N–5
DA0-DA11, OFA
N–3
N–1
tD
N–6
DB0-DB11, OFB
N–4
tC
CLKOUTB
N–2
tC
CLKOUTA
224112 TD03
Demultiplexed CMOS Outputs with Simultaneous Update
All Outputs Are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
tL
N+1
ENC–
ENC+
tD
DA0-DA11, OFA
N–6
N–4
N–2
N–5
N–3
N–1
tD
DB0-DB11, OFB
CLKOUTB
CLKOUTA
tC
224112 TD04
224112fc
13
LTC2241-12
Applications Information
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
Signal-to-Noise Ratio
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of
either input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding
the input signal and DC. This value is expressed in decibels
relative to the RMS value of a full scale input signal.
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Full Power Bandwidth
Total Harmonic Distortion
Aperture Delay Time
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
The time from when a rising ENC+ equals the ENC– voltage
to the instant that the input signal is held by the sample
and hold circuit.
THD = 20Log
( V2 + V3 + V4 + ...Vn )/ V1
2
2
2
2
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second
through nth harmonics. The THD calculated in this data
sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n = 0,
1, 2, 3, etc. The 3rd order intermodulation products are
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
CONVERTER OPERATION
As shown in Figure 1, the LTC2241-12 is a CMOS pipelined
multi-step converter. The converter has five pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section). For
optimal performance the analog inputs should be driven
differentially. The encode input is differential for improved
common mode noise immunity. The LTC2241‑12 has two
phases of operation, determined by the state of the differential ENC+/ENC– input pins. For brevity, the text will
refer to ENC+ greater than ENC– as ENC high and ENC+
less than ENC– as ENC low.
224112fc
14
LTC2241-12
Applications Information
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input is
held. While ENC is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the
first stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When ENC goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third and fourth stages, resulting in a fourth stage residue
that is sent to the fifth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2241-12
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (CSAMPLE) through
NMOS transistors. The capacitors shown attached to
each input (CPARASITIC) are the summation of all other
capacitance associated with each input.
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
When ENC transitions from low to high, the sampled input
LTC2241-12
VDD
AIN+
RON
14Ω
10Ω
CPARASITIC
1.8pF
VDD
AIN–
CSAMPLE
2pF
RON
14Ω
10Ω
CSAMPLE
2pF
CPARASITIC
1.8pF
VDD
1.5V
6k
ENC+
ENC–
6k
1.5V
224112 F02
Figure 2. Equivalent Input Circuit
voltage is held on the sampling capacitors. During the
hold phase when ENC is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such
as the change seen with input frequencies near Nyquist,
then a larger charging glitch will be seen.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for the
2V range or ±0.25V for the 1V range, around a common
mode voltage of 1.25V. The VCM output pin (Pin 60) may
be used to provide the common mode bias level. VCM can
be tied directly to the center tap of a transformer to set
the DC input level or as a reference level to an op amp
224112fc
15
LTC2241-12
applications information
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
bandwidth of most op amps will limit the SFDR at high
input frequencies.
Input Drive Impedance
Figure 5 shows a capacitively-coupled input circuit. The
impedance seen by the analog inputs should be matched.
As with all high performance, high speed ADCs, the dynamic performance of the LTC2241-12 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR. At the falling edge of ENC, the sampleand-hold circuit will connect the 2pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when ENC rises, holding the sampled input on
the sampling capacitor. Ideally the input circuitry should be
fast enough to fully charge the sampling capacitor during
the sampling period 1/(2fS); however, this is not always
possible and the incomplete settling may degrade the SFDR.
The sampling glitch has been designed to be as linear as
possible to minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2241-12 being driven by an RF
transformer with a center tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen
by the ADC does not exceed 100Ω for each ADC input.
A disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from
10Ω
VCM
2.2μF
0.1μF
T1
1:1
ANALOG
INPUT
25Ω
25Ω
AIN+
0.1μF
AIN+
LTC2241-12
12pF
25Ω
AIN–
25Ω
AIN–
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
224112 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
50Ω
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
ANALOG
INPUT
+
0.1μF
–
CM
+
–
VCM
2.2μF
25Ω
AIN+
3pF
AIN+
LTC2241-12
12pF
AIN–
25Ω
AIN–
3pF
224112 F04
Figure 4. Differential Drive with an Amplifier
VCM
0.1μF
100Ω
100Ω
2.2μF
25Ω
AIN+
AIN+
ANALOG
INPUT
12pF
0.1μF
25Ω
LTC2241-12
AIN–
AIN–
224112 F05
Figure 5. Capacitively-Coupled Drive
224112fc
16
LTC2241-12
Applications Information
the sample-and-hold charging glitches and limiting the
wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be
decreased to prevent excessive signal loss.
The AIN+ and AIN– inputs each have two pins to reduce
package inductance. The two AIN+ and the two AIN– pins
should be shorted together.
For input frequencies above 100MHz the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer
gives better high frequency response than a flux coupled
center-tapped transformer. The coupling capacitors allow
the analog inputs to be DC biased at 1.25V. In Figure 8 the
series inductors are impedance matching elements that
maximize the ADC bandwidth.
10Ω
2.2μF
0.1μF
ANALOG
INPUT
25Ω
12Ω
AIN+
0.1μF
AIN+
T1
0.1μF
The 1.25V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required
for the 1.25V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifier generates the high and low
reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has four pins: two each of REFHA
and REFHB for the high reference and two each of REFLA
and REFLB for the low reference. The multiple output pins
are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9.
LTC2241-12
8pF
25Ω
12Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
AIN–
224112 F06
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 100MHz and 250MHz
10Ω
Reference Operation
Figure 9 shows the LTC2241-12 reference circuitry consisting of a 1.25V bandgap reference, a difference amplifier
and switching and control circuit. The internal voltage
reference can be configured for two pin selectable input
ranges of 2V (±1V differential) or 1V (±0.5V differential).
Tying the SENSE pin to VDD selects the 2V range; typing
the SENSE pin to VCM selects the 1V range.
VCM
VCM
2.2μF
0.1μF
AIN+
ANALOG
INPUT
25Ω
0.1μF
AIN+
LTC2241-12
T1
0.1μF
AIN–
25Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
224112 F07
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 250MHz and 500MHz
10Ω
VCM
2.2μF
0.1μF
2.7nH
ANALOG
INPUT
25Ω
0.1μF
AIN+
AIN+
LTC2241-12
T1
0.1μF
25Ω
2.7nH
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
AIN–
224112 F08
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 500MHz
224112fc
17
LTC2241-12
applications information
Input Range
LTC2241-12
2Ω
VCM
1.25V
2.2μF
The input range can be set based on the application.
The 2V input range will provide the best signal-to-noise
performance while maintaining excellent SFDR. The 1V
input range will have better SFDR performance, but the
SNR will degrade by 5dB. See the Typical Performance
Characteristics section.
1.25V BANDGAP
REFERENCE
1V
0.5V
RANGE
DETECT
AND
CONTROL
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
SENSE
REFLB
BUFFER
0.1μF
REFHA
1μF
2.2μF
1μF
Driving the Encode Inputs
INTERNAL ADC
HIGH REFERENCE
DIFF AMP
REFLA
0.1μF
INTERNAL ADC
LOW REFERENCE
REFHB
224112 F09
Figure 9. Equivalent Reference Circuit
1.25V
8k
2.2μF
SENSE
12k
1μF
Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequencies) take the following into consideration:
VCM
0.75V
The noise performance of the LTC2241-12 can depend
on the encode signal quality as much as on the analog
input. The ENC+/ENC– inputs are intended to be driven
differentially, primarily for noise immunity from common
mode noise sources. Each input is biased through a 4.8k
resistor to a 1.5V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and
can set the logic threshold for single-ended drive circuits.
LTC2241-12
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the amplitude.
224112 F10
Figure 10. 1.5V Range ADC
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to
SENSE. It is not recommended to drive the SENSE pin
with a logic device. The SENSE pin should be tied to the
appropriate level as close to the converter as possible. If
the SENSE pin is driven externally, it should be bypassed
to ground as close to the device as possible with a 1µF
ceramic capacitor.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at
both inputs as common mode noise. The encode inputs
have a common mode range of 1.2V to 2.0V. Each input
may be driven from ground to VDD for single-ended drive.
224112fc
18
LTC2241-12
Applications Information
VDD
LTC2241-12
TO INTERNAL
ADC CIRCUITS
CLOCK
INPUT
VDD
T1
MA/COM
0.1μF ETC1-1-13
•
4.8k
ENC+
•
1.5V BIAS
50Ω
8.2pF
100Ω
50Ω
0.1μF
ENC–
VDD
1.5V BIAS
4.8k
0.1μF
224112 F11
Figure 11. Transformer Driven ENC+/ENC–
0.1μF
ENC+
VTHRESHOLD = 1.5V
1.5V ENC– LTC2241-12
LVDS
CLOCK
0.1μF
224112 F12a
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2241-12 is 210Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 2.26ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise
50% duty cycle is easy with differential sinusoidal drive
using a transformer or using symmetric differential logic
such as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used if
the input clock has a non 50% duty cycle. This circuit uses
the rising edge of the ENC+ pin to sample the analog input.
The falling edge of ENC+ is ignored and the internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 40% to 60% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
100Ω 0.1μF
ENC+
ENC–
LTC2241-12
224112 F12b
Figure 12b. ENC Drive Using LVDS
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2241-12 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTC2241-12 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
224112fc
19
LTC2241-12
applications information
Digital Output Buffers (CMOS Modes)
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D11 – D0
(Offset Binary)
D11 – D0
(2’s Complement)
>+1.000000V
+0.999512V
+0.999024V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
工商网监
湘ICP备2023018690号
