LTC2261CUJ-14#PBF

Product Folder Order Now Technical Documents Support & Community Tools & Software ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 ADS41xx 14-, 12-Bit, 65-, 125-MSPS, Ultra-Low-Power ADC 1 Features 3 Description • The ADS412x and ADS414x devices are lowersampling speed variants in the ADS41xx family of analog-to-digital converters (ADCs). These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8-V supply. The devices are wellsuited for multi-carrier, wide bandwidth communications applications. 1 • • • • • • • Ultra-Low Power With 1.8-V Single Supply: – 103-mW Total Power at 65 MSPS – 153-mW Total Power at 125 MSPS High Dynamic Performance: – SNR: 72.2 dBFS at 170 MHz – SFDR: 81 dBc at 170 MHz Dynamic Power Scaling With Sample Rate Idle Channel SNR 74.8 dBFS (ADS414x) Output Interface: – Double Data Rate (DDR) LVDS With Programmable Swing and Strength: – Standard Swing: 350 mV – Low Swing: 200 mV – Default Strength: 100-Ω Termination – 2x Strength: 50-Ω Termination – 1.8-V Parallel CMOS Interface Also Supported Programmable Gain up to 6 dB for SNR, SFDR Trade-Off DC Offset Correction Supports Low Input Clock Amplitude Down to 200 mVPP The ADS412x and ADS414x devices have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance. The ADS412x and ADS414x devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C). Device Information(1) PART NUMBER ADS4125 ADS4142 BODY SIZE (NOM) VQFN (48) 7.00 mm × 7.00 mm ADS4145 2 Applications • • • • PACKAGE ADS4122 (1) For all available packages, see the orderable addendum at the end of the data sheet. Wireless Communications Infrastructure Software-Defined Radios Power Amplifier Linearization Imaging Systems ADS41xx Block Diagram ADS41xx VCM Reference LVDS/CMOS buffers D0_D1P (LVDS) / D0(CMOS) D0_D1M (LVDS) / D1 (CMOS) INP Sampling Circuit 14-bit ADC INM D12_D13P (LVDS) / D12(CMOS) D12_D13M (LVDS) / D13(CMOS) CLKP CLK Gen CLKM CLKOUTP CLKOUTM (LVDS) / NC (CMOS) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Family Comparison................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 8 Thermal Information .................................................. 8 Electrical Characteristics: ADS412x ......................... 9 Electrical Characteristics: ADS414x ....................... 11 Electrical Characteristics: General .......................... 13 Digital Characteristics ............................................. 14 Timing Requirements: LVDS and CMOS Modes.... 14 Serial Interface Timing Characteristics ................. 15 Reset Timing Requirements ................................. 16 Timing Characteristics at Lower Sampling Frequencies ............................................................. 16 7.13 Typical Characteristics: ADS4122 ........................ 19 7.14 Typical Characteristics: ADS4125 ........................ 22 7.15 Typical Characteristics: ADS4142 ........................ 25 7.16 Typical Characteristics: ADS4145 ........................ 29 7.17 Typical Characteristics: Common ......................... 33 7.18 Typical Characteristics: Contour ........................... 34 8 Detailed Description ............................................ 35 8.1 8.2 8.3 8.4 8.5 8.6 9 Overview ................................................................. Functional Block Diagrams .................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 35 36 38 40 46 49 Application and Implementation ........................ 57 9.1 Application Information............................................ 57 9.2 Typical Application .................................................. 72 10 Power Supply Recommendations ..................... 74 10.1 Sharing DRVDD and AVDD Supplies ................... 74 10.2 Using DC-DC Power Supplies .............................. 74 10.3 Power Supply Bypassing ...................................... 74 11 Layout................................................................... 74 11.1 Layout Guidelines ................................................. 74 11.2 Layout Example .................................................... 75 12 Device and Documentation Support ................. 76 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 76 78 78 78 78 78 78 79 13 Mechanical, Packaging, and Orderable Information ........................................................... 79 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2016) to Revision C Page • Added a new feature Idle Channel SNR 74.8 dBFS (ADS414x) to the Features section...................................................... 1 • Added a new application Imaging Systems in Applications section....................................................................................... 1 • Changed ADS412x/4x to ADS412x and ADS414x in Description section ............................................................................. 1 • Changed ADS41xx Block Diagram in the first page............................................................................................................... 1 • Changed input clock sample rate minimum for the ADS4122/ADS4142, low-speed mode enabled by default from: 20 MSPS to: 3 MSPS ............................................................................................................................................................ 8 • Changed input clock sample rate minimum for the ADS4122/ADS4142, low-speed mode enabled from: 20 MSPS to: 3 MSPS ................................................................................................................................................................................. 8 • Deleted High Performance Modes section from Recommended Operating Conditions table, moved to Programming section .................................................................................................................................................................................... 8 • Added order to HD2 and HD3 parameter names in Electrical Characteristics tables.......................................................... 10 • Added test conditions header to Electrical Characteristics: General table .......................................................................... 13 • Added Using the ADS41xx at Low Sampling Rates subsection in Application and Implementation section....................... 62 • Added Figure 114 to Figure 124 in ADS412x (12-Bit Device) section ................................................................................. 62 • Changed the order of figures in ADS412x (12-Bit Device) section. .................................................................................... 62 • Added the device name ADS412x to the conditions of ADS412x (12-Bit Device) section. ................................................. 62 • Changed the unit of fS from MHz to MSPS in the specifications of Figure 115 ................................................................... 62 • Added new subsection ADS412x (12-Bit Device) in Application Information section. ........................................................ 62 2 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Revision History (continued) • Changed the unit of fS from MHz to MSPS in the specifications of Figure 116 ................................................................... 62 • Changed the unit of fS from MHz to MSPS in the specifications of Figure 119 .................................................................. 63 • Changed the unit of fS from MHz to MSPS in the specifications of Figure 120 .................................................................. 63 • Changed the unit of fS from MHz to MSPS in the specifications of Figure 121 .................................................................. 63 • Changed the unit of fS from MHz to MSPS in the specifications of Figure 122 .................................................................. 63 • Added Figure 125 through Figure 128 in typical performance at lower sampling rate for ADS412x (12-bit devices) in CMOS interface mode. ........................................................................................................................................................ 64 • Added Figure 129 through Figure 130 in typical performance at lower sampling rate for ADS412x (12-bit devices) in CMOS interface mode. ........................................................................................................................................................ 64 • Added Figure 131 through Figure 132 in typical performance at lower sampling rate for ADS412x (12-bit devices) in CMOS interface mode. ........................................................................................................................................................ 65 • Added Figure 136 to Figure 146 in ADS414x (14-Bit Device) section ................................................................................. 66 • Changed the order of figures in ADS414x (14-Bit Device) section. ..................................................................................... 66 • Added the device name ADS414x to the conditions of ADS414x (14-Bit Device) section. ................................................ 66 • Changed the unit of fS from MHz to MSPS in the specifications of Figure 137 and Figure 138 .......................................... 66 • Added new subsection ADS414x (14-Bit Device) in Application Information section. ......................................................... 66 • Changed the SNR and SINAD values of Figure 138 . ......................................................................................................... 66 • Changed the unit of fS from MHz to MSPS in the specifications of Figure 141 through Figure 144.................................... 66 • Added Figure 147 through Figure 157 in typical performance at lower sampling rate for ADS414x (14-bit devices) in CMOS interface mode. ........................................................................................................................................................ 67 • Added Figure 151 through Figure 158 in typical performance at lower sampling rate for ADS414x (14-bit devices) in CMOS interface mode. ........................................................................................................................................................ 68 • Added Figure 153 through Figure 155 in typical performance at lower sampling rate for ADS414x (14-bit devices) in CMOS interface mode. ........................................................................................................................................................ 68 • Added Output Timing at Low Sampling Rates subsection in Application and Implementation section ............................... 71 • Changed the name of the header from ADS4128 CAPABILITY to ADS4125 CAPABILITY in the last column of Table 25 ............................................................................................................................................................................... 72 • Added Receiving Notification of Documentation Updates section ...................................................................................... 78 Changes from Revision A (March 2011) to Revision B • Page Added Pin Configuration and Functions section, Handling Rating table, Feature Descriptionsection, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Supportsection, and Mechanical, Packaging, and Orderable Information section ...... 1 Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 3 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 5 Device Family Comparison FAMILY 65 MSPS 125 MSPS 160 MSPS 250 MSPS ADS412x, 12-bit family ADS4122 ADS4125 ADS4126 ADS414x, 14-bit family ADS4142 ADS4145 9-Bit — 11-Bit — WITH ANALOG INPUT BUFFERS 200 MSPS 250 MSPS ADS4129 — ADS41B29 ADS4146 ADS4149 — ADS41B49 — — — — ADS58B19 — — — ADS58B18 — 6 Pin Configuration and Functions DRGND DRVDD OVR_SDOUT 1 2 3 37 D2_D3_M 38 D2_D3_P 39 D4_D5_M 40 D4_D5_P 41 D6_D7_M 42 D6_D7_P 43 D8_D9_M 44 D8_D9_P 45 D10_D11_M 46 D10_D11_P 48 D12_D13_P 47 D12_D13_M ADS414x RGZ Package 48-Pin VQFN With Exposed Thermal Pad LVDS Mode - Top View 37 D0_D1_M 38 D0_D1_P 39 D2_D3_M 40 D2_D3_P 41 D4_D5_M 42 D4_D5_P 43 D6_D7_M 44 D6_D7_P 45 D8_D9_M 46 D8_D9_P 47 D10_D11_M 48 D10_D11_P ADS412x RGZ Package 48-Pin VQFN With Exposed Thermal Pad LVDS Mode - Top View 36 DRGND DRGND 1 36 DRGND 35 DRVDD DRVDD 2 35 DRVDD 34 NC OVR_SDOUT 3 34 D0_D1_P 4 33 D0_D1_M 32 NC CLKOUTM 4 33 NC CLKOUTM CLKOUTP 5 32 NC CLKOUTP 5 DFS 6 31 NC DFS 6 OE 7 OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA AVDD 24 25 AGND AVDD 24 AVDD 22 RESERVED 23 NC 21 AVDD 20 AGND 19 AVDD 18 AGND 17 INM 16 INP 15 VCM 13 AGND 14 25 AGND RESERVED 23 AGND 12 26 AVDD AGND 12 AVDD 22 26 AVDD NC 21 CLKM 11 27 SEN CLKM 11 AVDD 20 27 SEN AGND 19 CLKP 10 CLKP 10 AVDD 18 28 SDATA AGND 17 9 INM 16 29 SCLK INP 15 8 VCM 13 AGND 30 RESET AGND 14 AVDD 31 NC Thermal Pad Thermal Pad The thermal pad is connected to DRGND. Pin Functions: LVDS Mode PIN I/O DESCRIPTION NAME ADS412x ADS414x AGND 9, 12, 14, 17, 19, 25 9, 12, 14, 17, 19, 25 I Analog ground AVDD 8, 18, 20, 22, 24, 26 8, 18, 20, 22, 24, 26 I 1.8-V analog power supply CLKM 11 11 I Differential clock input, complement CLKP 10 10 I Differential clock input, true CLKOUTM 4 4 O Differential output clock, complement CLKOUTP 5 5 O Differential output clock, true D0_D1_M 37 33 O Differential output data D0 and D1 multiplexed, complement D0_D1_P 38 34 O Differential output data D0 and D1 multiplexed, true D2_D3_M 39 37 O Differential output data D2 and D3 multiplexed, complement D2_D3_P 40 38 O Differential output data D2 and D3 multiplexed, true D4_D5_M 41 39 O Differential output data D4 and D5 multiplexed, complement D4_D5_P 42 40 O Differential output data D4 and D5 multiplexed, true 4 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Pin Functions: LVDS Mode (continued) PIN NAME I/O DESCRIPTION ADS412x ADS414x D6_D7_M 43 41 O Differential output data D6 and D7 multiplexed, complement D6_D7_P 44 42 O Differential output data D6 and D7 multiplexed, true D8_D9_M 45 43 O Differential output data D8 and D9 multiplexed, complement D8_D9_P 46 44 O Differential output data D8 and D9 multiplexed, true D10_D11_M 47 45 O Differential output data D10 and D11 multiplexed, complement D10_D11_P 48 46 O Differential output data D10 and D11 multiplexed, true D12_D13_M — 47 O Differential output data D12 and D13 multiplexed, complement D12_D13_P — 48 O Differential output data D12 and D13 multiplexed, true DFS 6 6 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS, CMOS output interface type. See Table 5 for detailed information. DRGND 1, 36, PAD 1, 36, PAD I Digital and output buffer ground DRVDD 2, 35 2, 35 I 1.8-V digital and output buffer supply INM 16 16 I Differential analog input, negative INP 15 15 I Differential analog input, positive NC 21, 31, 32, 33, 34 21, 31, 32 – Do not connect OE 7 7 I Output buffer enable input, active high; this pin has an internal 180-kΩ pullup resistor to DRVDD. OVR_SDOUT 3 3 O This pin functions as an out-of-range indicator after reset, when register bit READOUT = 0, and functions as a serial register readout pin when READOUT = 1. RESERVED 23 23 I Digital control pin, reserved for future use RESET 30 30 I Serial interface RESET input. When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface section. When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as an analog control pin. RESET has an internal 180-kΩ pulldown resistor. SCLK 29 29 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and should be tied to ground. This pin has an internal 180-kΩ pulldown resistor. SDATA 28 28 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 7). This pin has an internal 180-kΩ pulldown resistor. SEN 27 27 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and must be tied to AVDD. This pin has an internal 180-kΩ pullup resistor to AVDD. VCM 13 13 O Outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins. Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 5 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 37 D2 38 D3 39 D4 40 D5 41 D6 42 D7 43 D8 44 D9 45 D10 46 D11 47 D12 48 D13 ADS414x RGZ Package 48-PIN VQFN With Exposed Thermal Pad CMOS Mode - Top View 37 D0 38 D1 39 D2 40 D3 41 D4 42 D5 43 D6 44 D7 45 D8 46 D9 47 D10 48 D11 ADS412x RGZ Package 48-PIN VQFN With Exposed Thermal Pad CMOS Mode - Top View DRGND 1 36 DRGND DRGND 1 36 DRGND DRVDD 2 35 DRVDD DRVDD 2 35 DRVDD OVR_SDOUT 3 34 NC OVR_SDOUT 3 34 D1 UNUSED 4 33 NC UNUSED 4 33 D0 CLKOUT 5 32 NC CLKOUT 5 32 NC DFS 6 31 NC DFS 6 OE 7 30 RESET OE 7 30 RESET AVDD 8 29 SCLK AVDD 8 29 SCLK AGND 9 28 SDATA AGND 9 28 SDATA 31 NC Thermal Pad Thermal Pad AVDD 24 AVDD 22 RESERVED 23 NC 21 AVDD 20 AGND 19 AVDD 18 AGND 17 INM 16 INP 15 VCM 13 AGND 14 AVDD 24 AVDD 22 RESERVED 23 NC 21 AVDD 20 25 AGND AGND 19 AGND 12 AVDD 18 25 AGND AGND 17 26 AVDD AGND 12 INM 16 27 SEN CLKM 11 INP 15 CLKP 10 26 AVDD VCM 13 27 SEN AGND 14 CLKP 10 CLKM 11 The thermal pad is connected to DRGND. Pin Functions: CMOS Mode PIN I/O DESCRIPTION NAME ADS412x ADS414x AVDD 8, 18, 20, 22, 24, 26 8, 18, 20, 22, 24, 26 I 1.8-V analog power supply AGND 9, 12, 14, 17, 19, 25 9, 12, 14, 17, 19, 25 I Analog ground CLKM 11 11 I Differential clock input, complement CLKP 10 10 I Differential clock input, true CLKOUT 5 5 O CMOS output clock D0 37 33 O 12-bit, 14-bit CMOS output data D1 38 34 O 12-bit, 14-bit CMOS output data D2 39 37 O 12-bit, 14-bit CMOS output data D3 40 38 O 12-bit, 14-bit CMOS output data D4 41 39 O 12-bit, 14-bit CMOS output data D5 42 40 O 12-bit, 14-bit CMOS output data D6 43 41 O 12-bit, 14-bit CMOS output data D7 44 42 O 12-bit, 14-bit CMOS output data D8 45 43 O 12-bit, 14-bit CMOS output data D9 46 44 O 12-bit, 14-bit CMOS output data D10 47 45 O 12-bit, 14-bit CMOS output data D11 48 46 O 12-bit, 14-bit CMOS output data D12 — 47 O 12-bit, 14-bit CMOS output data D13 — 48 O 12-bit, 14-bit CMOS output data DFS 6 6 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS, CMOS output interface type. See Table 5 for detailed information. DRGND 1, 36, PAD 1, 36, PAD I Digital and output buffer ground DRVDD 2, 35 2, 35 I 1.8-V digital and output buffer supply INM 16 16 I Differential analog input, negative INP 15 15 I Differential analog input, positive NC 21, 31, 32, 33, 34 21, 31, 32 – Do not connect 6 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Pin Functions: CMOS Mode (continued) PIN NAME I/O DESCRIPTION ADS412x ADS414x OE 7 7 I Output buffer enable input, active high; this pin has an internal 180-kΩ pullup resistor to DRVDD. OVR_SDOUT 3 3 O This pin functions as an out-of-range indicator after reset, when register bit READOUT = 0, and functions as a serial register readout pin when READOUT = 1. RESERVED 23 23 I Digital control pin, reserved for future use RESET 30 30 I Serial interface RESET input. When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface section. When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as an analog control pin. RESET has an internal 180-kΩ pulldown resistor. SCLK 29 29 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and must be tied to ground. This pin has an internal 180-kΩ pulldown resistor. SDATA 28 28 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 7). This pin has an internal 180-kΩ pulldown resistor. SEN 27 27 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and must be tied to AVDD. This pin has an internal 180-kΩ pullup resistor to AVDD. UNUSED 4 4 – Unused pin in CMOS mode VCM 13 13 O Outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins. 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range, unless otherwise noted. (1) MIN MAX UNIT Supply voltage, AVDD –0.3 2.1 V Supply voltage, DRVDD –0.3 2.1 V Voltage between AGND and DRGND –0.3 0.3 V Voltage between AVDD to DRVDD (when AVDD leads DRVDD) 0 2.1 V Voltage between DRVDD to AVDD (when DRVDD leads AVDD) 0 2.1 V INP, INM –0.3 minimum (1.9, AVDD + 0.3) CLKP, CLKM (2), DFS, OE –0.3 AVDD + 0.3 RESET, SCLK, SDATA, SEN –0.3 3.9 Voltage applied to input pins Operating free-air temperature, TA –40 Operating junction temperature, TJ Storage temperature, Tstg (1) (2) –65 V 85 °C 125 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3 V|. This prevents the ESD protection diodes at the clock input pins from turning on. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 7 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 7.3 Recommended Operating Conditions Over operating free-air temperature range, unless otherwise noted. MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage 1.7 1.8 1.9 V DRVDD Digital supply voltage 1.7 1.8 1.9 V ANALOG INPUTS Differential input voltage (1) 2 Input common-mode voltage VPP VCM ± 0.05 V Maximum analog input frequency with 2-VPP input amplitude (2) 400 MHz Maximum analog input frequency with 1-VPP input amplitude (2) 800 MHz CLOCK INPUT Input clock sample rate ADS4122, ADS4142, low-speed mode enabled by default 3 65 ADS4125, ADS4145, low-speed mode enabled 3 80 ADS4125, ADS4145, low-speed mode disabled > 80 Sine wave, ac-coupled Input clock amplitude differential (VCLKP – VCLKM) Input clock duty cycle MSPS 125 0.2 1.5 LVPECL, ac-coupled 1.6 LVDS, ac-coupled 0.7 LVCMOS, single-ended, ac-coupled 1.8 VPP V Low-speed enabled 40% 50% 60% Low-speed disabled 35% 50% 65% DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to DRGND RLOAD Differential load resistance between the LVDS output pairs (LVDS mode) TA Operating free-air temperature (1) (2) 5 pF 100 –40 Ω 85 °C With 0-dB gain. See the Gain for SFDR, SNR Trade-Off section in the Application Information for the relationship between input voltage range and gain. See the Application Information section. 7.4 Thermal Information THERMAL METRIC ADS412x, ADS414x (1) RGZ (VQFN) UNIT 48 PIN RθJA Junction-to-ambient thermal resistance 29 °C/W RθJCtop Junction-to-case (top) thermal resistance N/A °C/W RθJB Junction-to-board thermal resistance 10 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 9 °C/W RθJCbot Junction-to-case (bottom) thermal resistance 1.1 °C/W (1) 8 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 7.5 Electrical Characteristics: ADS412x Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V. PARAMETER TEST CONDITIONS MIN TYP Resolution 12 fIN = 10 MHz fIN = 70 MHz SNR Signal-to-noise ratio, LVDS fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz fIN = 10 MHz fIN = 70 MHz SINAD Signal-to-noise and distortion ratio, LVDS fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz fIN = 10 MHz ADS4122 (65 MSPS) Spurious-free dynamic range fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz fIN = 10 MHz fIN = 70 MHz THD Total harmonic distortion fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz Copyright © 2011–2017, Texas Instruments Incorporated UNIT Bits 71.1 ADS4125 (125 MSPS) 71 ADS4122 (65 MSPS) 70.9 ADS4125 (125 MSPS) 70.8 ADS4122 (65 MSPS) 70.7 ADS4125 (125 MSPS) 70.6 ADS4122 (65 MSPS) 67 70.2 ADS4125 (125 MSPS) 68 70.1 ADS4122 (65 MSPS) 68.8 ADS4125 (125 MSPS) 69.6 ADS4122 (65 MSPS) 70.8 ADS4125 (125 MSPS) 70.7 ADS4122 (65 MSPS) 70.8 ADS4125 (125 MSPS) 70.7 ADS4122 (65 MSPS) 70.6 ADS4125 (125 MSPS) 70.3 ADS4122 (65 MSPS) 66 70.1 ADS4125 (125 MSPS) 67 69.8 ADS4122 (65 MSPS) dBFS dBFS 68 ADS4125 (125 MSPS) 69 ADS4122 (65 MSPS) 86.5 ADS4125 (125 MSPS) 86 fIN = 70 MHz SFDR MAX 86 ADS4122 (65 MSPS) 87 ADS4125 (125 MSPS) 82 ADS4122 (65 MSPS) 70 ADS4125 (125 MSPS) 71 ADS4122 (65 MSPS) dBc 85 81 72.5 ADS4125 (125 MSPS) 77 ADS4122 (65 MSPS) 82.5 ADS4125 (125 MSPS) 82 ADS4122 (65 MSPS) 84 ADS4125 (125 MSPS) 83.5 ADS4122 (65 MSPS) 84 ADS4125 (125 MSPS) 80.5 ADS4122 (65 MSPS) 69.5 81 ADS4125 (125 MSPS) 69.5 79.5 ADS4122 (65 MSPS) dBc 72 ADS4125 (125 MSPS) 75.5 Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 9 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Electrical Characteristics: ADS412x (continued) Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V. PARAMETER TEST CONDITIONS MIN fIN = 10 MHz fIN = 70 MHz HD2 Second-order harmonic distortion fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz fIN = 10 MHz fIN = 70 MHz HD3 Third-order harmonic distortion fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz fIN = 10 MHz fIN = 70 MHz Worst spur (other than second and third harmonics) fIN = 100 MHz fIN = 170 MHz TYP MAX UNIT 87 ADS4122 (65 MSPS) 88 ADS4125 (125 MSPS) 86 ADS4122 (65 MSPS) 88 ADS4125 (125 MSPS) 82 ADS4122 (65 MSPS) 70 ADS4125 (125 MSPS) 71 ADS4122 (65 MSPS) dBc 86 83 72.5 ADS4125 (125 MSPS) 77 ADS4122 (65 MSPS) 86.5 ADS4125 (125 MSPS) 86 ADS4122 (65 MSPS) 86 ADS4125 (125 MSPS) 88 ADS4122 (65 MSPS) 87 ADS4125 (125 MSPS) 85 ADS4122 (65 MSPS) 70 85 ADS4125 (125 MSPS) 71 81 ADS4122 (65 MSPS) 85 ADS4125 (125 MSPS) 82 ADS4122 (65 MSPS) 96 ADS4125 (125 MSPS) 95 ADS4122 (65 MSPS) 96 ADS4125 (125 MSPS) 95 ADS4122 (65 MSPS) 94 ADS4125 (125 MSPS) 95 ADS4122 (65 MSPS) 76.5 92 ADS4125 (125 MSPS) 76.5 91 fIN = 300 MHz dBc dBc 88 ADS4122 (65 MSPS) 90 Two-tone intermodulation distortion f1 = 100 MHz, f2 = 105 MHz, each tone at –7 dBFS Input overload recovery Recovery to within 1% (of final value) for 6-dB overload with sine-wave input PSRR AC power-supply rejection ratio For 100-mVPP signal on AVDD supply, up to 10 MHz > 30 dB ENOB Effective number of bits fIN = 170 MHz 11.2 LSBs DNL Differential nonlinearity fIN = 170 MHz IMD INL 10 Integrated nonlinearity fIN = 170 MHz Submit Documentation Feedback ADS4125 (125 MSPS) dBFS 87.5 Clock cycles 1 ±0.2 1.5 ADS4122 (65 MSPS) –0.85 ±0.3 3.5 ADS4125 (125 MSPS) ±0.35 3.5 LSBs LSBs Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 7.6 Electrical Characteristics: ADS414x Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V. PARAMETER TEST CONDITIONS MIN TYP Resolution 14 fIN = 10 MHz fIN = 70 MHz SNR Signal-to-noise ratio, LVDS fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz fIN = 10 MHz fIN = 70 MHz SINAD Signal-to-noise and distortion ratio, LVDS fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz fIN = 10 MHz fIN = 70 MHz SFDR Spurious-free dynamic range fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz fIN = 10 MHz fIN = 70 MHz THD Total harmonic distortion MAX fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz Copyright © 2011–2017, Texas Instruments Incorporated ADS4142 (65 MSPS) 73.9 ADS4145 (125 MSPS) 73.7 ADS4142 (65 MSPS) 73.5 ADS4145 (125 MSPS) 73.4 ADS4142 (65 MSPS) 73.2 ADS4145 (125 MSPS) 73.1 ADS4142 (65 MSPS) 69 72.4 ADS4145 (125 MSPS) 70 72.2 ADS4142 (65 MSPS) 70.5 ADS4145 (125 MSPS) 71.3 ADS4142 (65 MSPS) 73.5 ADS4145 (125 MSPS) 73.2 ADS4142 (65 MSPS) 73.3 ADS4145 (125 MSPS) UNIT Bits dBFS 73 ADS4142 (65 MSPS) 73 ADS4145 (125 MSPS) 72.6 ADS4142 (65 MSPS) 68 72.3 ADS4145 (125 MSPS) 69 71.8 ADS4142 (65 MSPS) 69.2 ADS4145 (125 MSPS) 70.6 ADS4142 (65 MSPS) dBFS 87 ADS4145 (125 MSPS) 86 ADS4142 (65 MSPS) 86.5 ADS4145 (125 MSPS) 85.5 ADS4142 (65 MSPS) 87 ADS4145 (125 MSPS) 82 ADS4142 (65 MSPS) ADS4145 (125 MSPS) 71 85 72.5 81.5 ADS4142 (65 MSPS) dBc 72.5 ADS4145 (125 MSPS) 77 ADS4142 (65 MSPS) 84 ADS4145 (125 MSPS) 83 ADS4142 (65 MSPS) 84 ADS4145 (125 MSPS) 83.5 ADS4142 (65 MSPS) 84 ADS4145 (125 MSPS) 81 ADS4142 (65 MSPS) 69.5 ADS4145 (125 MSPS) 70.5 82.5 80 ADS4142 (65 MSPS) 72.5 ADS4145 (125 MSPS) 75.5 Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 dBc 11 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Electrical Characteristics: ADS414x (continued) Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V. PARAMETER TEST CONDITIONS fIN = 10 MHz fIN = 70 MHz HD2 Second-order harmonic distortion fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz fIN = 10 MHz fIN = 70 MHz HD3 Third-order harmonic distortion fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz fIN = 10 MHz MIN 88 ADS4145 (125 MSPS) 87 ADS4142 (65 MSPS) fIN = 100 MHz fIN = 170 MHz fIN = 300 MHz IMD PSRR 88 ADS4145 (125 MSPS) 82 ADS4142 (65 MSPS) 71 ADS4145 (125 MSPS) 72.5 ADS4142 (65 MSPS) 77 87 ADS4145 (125 MSPS) 86 ADS4142 (65 MSPS) 86.5 ADS4145 (125 MSPS) 87 ADS4142 (65 MSPS) 87 ADS4145 (125 MSPS) 85 ADS4142 (65 MSPS) ADS4145 (125 MSPS) 71 85 72.5 81.5 ADS4142 (65 MSPS) 85 ADS4145 (125 MSPS) 84 ADS4142 (65 MSPS) 96 ADS4145 (125 MSPS) 95 fIN = 170 MHz Integrated nonlinearity fIN = 170 MHz 12 Submit Documentation Feedback 95 ADS4142 (65 MSPS) 77.5 92 ADS4145 (125 MSPS) 78.5 91 ADS4142 (65 MSPS) dBc 87 ADS4145 (125 MSPS) 88 ADS4142 (65 MSPS) 88.5 ADS4145 (125 MSPS) 87.5 For 100-mVPP signal on AVDD supply, up to 10 MHz Differential nonlinearity 94 ADS4145 (125 MSPS) AC power-supply rejection ratio INL dBc 95 ADS4142 (65 MSPS) Recovery to within 1% (of final value) for 6-dB overload with sine-wave input DNL 84 72.5 ADS4142 (65 MSPS) Input overload recovery fIN = 170 MHz dBc 87 ADS4145 (125 MSPS) f1 = 100 MHz, f2 = 105 MHz, each tone at –7 dBFS Effective number of bits UNIT 85.5 ADS4142 (65 MSPS) Two-tone intermodulation distortion ENOB MAX 87 ADS4145 (125 MSPS) fIN = 70 MHz Worst spur (other than second and third harmonics) TYP ADS4142 (65 MSPS) dBFS Clock cycles 1 > 30 ADS4142 (65 MSPS) 11.5 ADS4145 (125 MSPS) 11.3 –0.95 dB LSBs ±0.5 1.7 LSBs ±1.5 ±4.5 LSBs Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 7.7 Electrical Characteristics: General Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Differential input voltage VCM Differential input resistance At dc, see Figure 106 Differential input capacitance See Figure 107 2 VPP >1 MΩ 4 pF Analog input bandwidth 550 MHz Analog input common-mode current (per input pin) 0.6 µA/MSPS Common-mode output voltage 0.95 VCM output current capability V 4 mA DC ACCURACY Offset error –15 Temperature coefficient of offset error EGREF Gain error as a result of internal reference inaccuracy alone EGCHAN Gain error of channel alone 2.5 15 0.003 –2 Temperature coefficient of EGCHAN mV mV/°C 2 %FS –0.2 %FS 0.001 Δ%/°C POWER SUPPLY IAVDD IDRVDD (1) Analog supply current ADS4122, ADS4142 (65 MSPS) 42 55 ADS4125, ADS4145 (125 MSPS) 62 75 Output buffer supply current, LVDS interface with 100-Ω external termination, low LVDS swing (200 mV) ADS4122, ADS4142 (65 MSPS) 28.5 ADS4125, ADS4145 (125 MSPS) 35.5 Output buffer supply current, LVDS interface with 100-Ω external termination, standard LVDS swing (350 mV) ADS4122, ADS4142 (65 MSPS) 40 53 ADS4125, ADS4145 (125 MSPS) 48 57 Output buffer supply current (1) (2), CMOS interface (2), 8-pF external load capacitance, fIN = 2.5 MHz ADS4122, ADS4142 (65 MSPS) 15 ADS4125, ADS4145 (125 MSPS) 23 Analog power ADS4122, ADS4142 (65 MSPS) 76 ADS4122, ADS4142 (125 MSPS) 112 Digital power, LVDS interface, low LVDS swing ADS4122, ADS4142 (65 MSPS) Digital power, CMOS interface (2), 8-pF external load capacitance, fIN = 2.5 MHz ADS4122, ADS4142 (65 MSPS) 27 41.5 ADS4122, ADS4142 (65 MSPS) 105 ADS4122, ADS4142 (125 MSPS) 130 Global power-down 10 Standby (1) (2) mW 66.5 ADS4122, ADS4142 (125 MSPS) mA mW 52 ADS4122, ADS4142 (125 MSPS) mA mW 15 mW mW The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance on each digital output line is 10 pF. In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation section in the Application Information). Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 13 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 7.8 Digital Characteristics Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, and 50% clock duty cycle for the ADS4122, ADS4125, ADS4142, and ADS4145, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESET, SCLK, SDATA, and SEN support 1.8-V and 3.3-V CMOS logic levels 1.3 OE only supports 1.8-V CMOS logic levels 1.3 Low-level input voltage High-level input current: SDATA, SCLK (1) VHIGH = 1.8 V 10 µA High-level input current: SEN VHIGH = 1.8 V 0 µA Low-level input current: SDATA, SCLK VLOW = 0 V 0 µA Low-level input current: SEN VLOW = 0 V –10 µA DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE) High-level input voltage Low-level input voltage High-level input voltage V 0.4 V V 0.4 V DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT) High-level output voltage DRVDD – 0.1 DRVDD Low-level output voltage V 0 0.1 V DIGITAL OUTPUTS (LVDS INTERFACE: DA0P/M TO DA13P/M, DB0P/M TO DB13P/M, CLKOUTP/M) High-level output voltage (2) VODH Standard swing LVDS 270 350 430 mV Low-level output voltage (2) VODL Standard swing LVDS –430 –350 –270 mV High-level output voltage (2) VODH Low swing LVDS 200 Low-level output voltage (2) VODL Low swing LVDS –200 Output common-mode voltage VOCM (1) (2) 0.85 mV mV 1.05 1.25 V SDATA and SCLK have an internal 180-kΩ pull-down resistor. With an external 100-Ω termination. 7.9 Timing Requirements: LVDS and CMOS Modes (1) Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 125 MSPS, sine wave input clock, CLOAD = 5 pF (2), and RLOAD = 100 Ω (3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V. MIN TYP MAX 0.6 0.8 1.2 UNIT GENERAL tA Aperture delay Variation of aperture delay between two devices at the same temperature and DRVDD supply tJ Aperture jitter Time to valid data after coming out of STANDBY mode Wakeup time: ADC latency (4): (1) (2) (3) (4) 14 Time to valid data after coming out of PDN GLOBAL mode ns ±100 ps 100 fS rms 5 25 µs 100 500 µs Low-latency mode (default after reset) 10 Clock cycles Low-latency mode disabled (gain enabled, offset correction disabled) 16 Clock cycles Low-latency mode disabled (gain and offset correction enabled) 17 Clock cycles Timing parameters are ensured by design and characterization but are not production tested. CLOAD is the effective external single-ended load capacitance between each output pin and ground. RLOAD is the differential load resistance between the LVDS output pair. At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Timing Requirements: LVDS and CMOS Modes(1) (continued) Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 125 MSPS, sine wave input clock, CLOAD = 5 pF(2), and RLOAD = 100 Ω(3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V. MIN TYP MAX UNIT 2.3 3 ns 0.35 0.6 ns 3 4.2 DDR LVDS MODE (5) (6) Data setup time (3): data valid (7) to zero-crossing of CLKOUTP tSU (3) : zero-crossing of CLKOUTP to data becoming invalid (7) tH Data hold time tPDI Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over, sampling frequency ≤ 125 MSPS 5.4 ns Variation of tPDI between two devices at the same temperature and DRVDD supply ±0.6 LVDS bit clock duty cycle of differential clock, (CLKOUTP – CLKOUTM), sampling frequency ≤ 125 MSPS 48% tRISE, tFALL Data rise time, data fall time: rise time measured from –100 mV to 100 mV, fall time measured from 100 mV to –100 mV, sampling frequency ≤ 125 MSPS 0.14 ns tCLKRISE, tCLKFALL Output clock rise time, output clock fall time rise time measured from –100 mV to 100 mV, fall time measured from 100 mV to –100 mV, sampling frequency ≤ 125 MSPS 0.14 ns tOE Output enable (OE) to data delay: time to valid data after OE becomes active ns 50 100 ns PARALLEL CMOS MODE (8) tSETUP Data setup time: data valid (9) to 50% of CLKOUT rising edge 3.1 3.7 ns tHOLD Data hold time: 50% of of CLKOUT rising edge to data becoming invalid (9) 3.2 4 ns tPDI Clock propagation delay: input clock rising edge cross-over to 50% of output clock rising edge, sampling frequency ≤ 125 MSPS 4 5.5 7 ns Output clock duty cycle of output clock, CLKOUT, sampling frequency ≤ 125 MSPS 47% tRISE, tFALL Data rise time, data fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, sampling frequency ≤ 125 MSPS 0.35 ns tCLKRISE, tCLKFALL Output clock rise time, output clock fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, sampling frequency ≤ 125 MSPS 0.35 ns tOE Output enable (OE) to data delay: time to valid data after OE becomes active (5) (6) (7) (8) (9) 20 40 ns Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. The LVDS timings are unchanged for low latency disabled and enabled. Data valid refers to a logic high of 100 mV and a logic low of –100 mV. Low latency mode enabled. Data valid refers to a logic high of 1.25 V and a logic low of 0.54 V. 7.10 Serial Interface Timing Characteristics Typical values at 25°C, minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V, unless otherwise noted. PARAMETER MIN TYP UNIT 20 MHz fSCLK SCLK frequency (equal to 1/tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDATA setup time 25 ns tDH SDATA hold time 25 ns Copyright © 2011–2017, Texas Instruments Incorporated > dc MAX Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 15 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 7.11 Reset Timing Requirements Typical values at 25°C and minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = 85°C, unless otherwise noted. MIN t1 Power-on delay from power-up of AVDD and DRVDD to RESET pulse active t2 Reset pulse duration of active RESET signal that resets the serial registers t3 Delay from RESET disable to SEN active (1) TYP MAX 1 UNIT ms 10 ns 1 (1) 100 µs ns The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1µs, the device could enter the parallel configuration mode briefly and then return back to serial interface mode. 7.12 Timing Characteristics at Lower Sampling Frequencies SAMPLING FREQUENCY (MSPS) tsu, SETUP TIME MIN TYP tPDI, CLOCK PROPAGATION DELAY th, HOLD TIME MAX MIN TYP MAX MIN TYP UNIT MAX DDR LVDS ns 65 5.5 6.5 0.35 0.6 ns 80 4.5 5.2 0.35 0.6 ns CMOS (LOW LATENCY ENABLED) (1) ns 65 6.5 7.5 6.5 7.5 4 5.5 7 ns 80 5.4 6 5.4 6 4 5.5 7 ns CMOS (LOW LATENCY DISABLED) (1) (1) ns 65 6 7 7 8 4 5.5 7 ns 80 4.8 5.5 5.7 6.5 4 5.5 7 ns 125 2.5 3.2 3.5 4.3 4 5.5 7 ns Timing specified with respect to output clock Dn_Dn + 1_P Logic 0 VODL Logic 1 VODH Dn_Dn + 1_M VOCM GND With external 100-Ω termination. Figure 1. LVDS Output Voltage Levels 16 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 N+3 N+2 N+1 Sample N N+4 N + 12 N + 11 N + 10 Input Signal tA CLKP Input Clock CLKM CLKOUTM CLKOUTP tPDI tH 10 Clock Cycles DDR LVDS (1) tSU (2) Output Data (DXP, DXM) E O O E N - 10 N-9 E O N-8 E O O E N-7 O E O E N-6 E O N+1 N E O E O N+2 tPDI CLKOUT tSU Parallel CMOS 10 Clock Cycles Output Data N - 10 N-9 N-8 (1) tH N-7 N-1 N N+1 ADC latency in low-latency mode. At higher sampling frequencies, tDPI is greater than one clock cycle which then makes the overall latency = ADC latency + 1. E = Even bits (D0, D2, D4, and so forth). O = Odd bits (D1, D3, D5, and so forth). Figure 2. Latency Diagram CLKM Input Clock CLKP tPDI CLKOUTP Output Clock CLKOUTM tSU Output Dn_Dn + 1_P Data Pair Dn_Dn + 1_M tH Dn (1) tSU Dn + 1 tH (1) Dn = bits D0, D2, D4, and so forth. Dn + 1 = Bits D1, D3, D5, and so forth. Figure 3. LVDS Mode Timing Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 17 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com CLKM Input Clock CLKP tPDI Output Clock CLKOUT tSU Output Data tH Dn Dn (1) CLKM Input Clock CLKP tSTART tDV Output Data Dn Dn (1) Dn = bits D0, D1, D2, and so forth. Figure 4. CMOS Mode Timing Register Address SDATA A6 A7 A5 A4 A3 Register Data A2 A0 A1 D7 D6 D5 tSCLK D3 D4 D2 D1 D0 tDH tDSU SCLK tSLOADS tSLOADH SEN RESET Figure 5. Serial Interface Timing Power Supply AVDD, DRVDD t1 RESET t3 t2 SEN A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET must be permanently tied high. Figure 6. Reset Timing Diagram 18 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 7.13 Typical Characteristics: ADS4122 At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 0 0 SFDR = 85.1dBc SNR = 71.3dBFS SINAD = 71.1dBFS THD = 83dBc −20 −20 −40 Amplitude (dB) Amplitude (dB) −40 −60 −60 −80 −80 −100 −100 −120 SFDR = 84.3dBc SNR = 70.5dBFS SINAD = 70.3dBFS THD = 82.7dBc 0 5 10 15 20 25 −120 30 32.5 0 5 10 Frequency (MHz) Figure 7. FFT for 20-MHz Input Signal SFDR = 71.9dBc SNR = 69.3dBFS SINAD = 67.7dBFS THD = 71.7dBc −40 Amplitude (dB) Amplitude (dB) 30 32.5 Each Tone at −7dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two−Tone IMD = 90.1dBFS SFDR = 97.3dBFS −20 −40 −60 −60 −80 −80 −100 −100 0 5 10 15 20 25 −120 30 32.5 0 5 10 15 20 25 30 32.5 Frequency (MHz) Frequency (MHz) Figure 9. FFT for 300-MHz Input Signal Figure 10. FFT for Two-Tone Input Signal 0 88 Each Tone at −36dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two−Tone IMD = 99.5dBFS SFDR = 106.9dBFS −20 83 78 SFDR (dBc) −40 Amplitude (dB) 25 0 −20 −60 73 −80 68 −100 63 −120 20 Figure 8. FFT for 170-MHz Input Signal 0 −120 15 Frequency (MHz) 0 5 10 15 20 25 30 32.5 58 0 50 100 150 200 250 300 350 400 Frequency (MHz) Input Frequency (MHz) Figure 11. FFT for Two-Tone Input Signal Figure 12. SFDR vs Input Frequency Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 19 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Typical Characteristics: ADS4122 (continued) At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 71.5 98 High Perf MODE1 Enabled Default 170MHz 220MHz 94 71 300MHz 400MHz 90 70.5 86 82 SFDR (dBc) SNR (dBFS) 70 69.5 78 74 69 70 68.5 66 68 0 50 100 150 200 250 300 350 58 400 0 0.5 1 1.5 2 2.5 3 3.5 4.5 5 5.5 6 Gain (dB) Figure 13. SNR vs Input Frequency Figure 14. SFDR Across Gain and Input Frequency 72 74 120 170MHz 220MHz 71 300MHz 400MHz Input Frequency = 40MHz SFDR (dBFS) SFDR (dBc) SNR 110 70 73.5 73 100 69 SFDR (dBc, dBFS) 68 67 SINAD (dBFS) 4 Input Frequency (MHz) 66 65 64 63 62 90 72.5 80 72 70 71.5 60 71 50 70.5 40 70 30 69.5 SNR (dBFS) 67.5 62 61 60 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 20 −45 6 −40 −35 Gain (dB) SFDR (dBFS) SFDR (dBc) SNR 70 71.5 60 71 50 70.5 40 70 30 69.5 −25 −20 −15 −10 −5 0 69 Amplitude (dBFS) Figure 17. Performance Across Input Amplitude (Single Tone) 20 Submit Documentation Feedback SFDR (dBc) 72 SNR (dBFS) SFDR (dBc, dBFS) 72.5 80 −30 −5 0 69 71.5 Input Frequency = 150MHz 90 −35 −10 94 73 −40 −15 SFDR SNR 73.5 100 20 −45 −20 Figure 16. Performance Across Input Amplitude (Single Tone) 74 120 Input Frequency = 150MHz −25 Amplitude (dBFS) Figure 15. SINAD Across Gain and Input Frequency 110 −30 90 71 86 70.5 82 70 78 69.5 74 0.8 0.85 0.9 0.95 1 1.05 SNR (dBFS) 59 69 1.1 Input Common−Mode Voltage (V) Figure 18. Performance vs Input Common-Mode Voltage Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Typical Characteristics: ADS4122 (continued) At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 73 100 Input Frequency = 150MHz 1.65 1.7 1.75 1.8 96 92 1.85 1.9 1.95 Input Frequency = 150MHz 72 88 1.85 1.9 1.95 71 SNR (dBFS) 84 SFDR (dBc) 1.65 1.7 1.75 1.8 80 76 70 69 72 68 68 64 10 35 60 67 −40 85 −15 10 Temperature (°C) Figure 19. SFDR Across Temperature vs AVDD Supply Input Frequency =150MHz SFDR (dBc) SFDR (dBc) 70.5 88 SNR (dBFS) 71 90 70 86 69.5 84 1.8 1.85 1.9 73 Input Frequency = 40MHz 69 1.95 71 86 70 85 69 84 68 83 67 82 66 81 65 80 64 0 DRVDD Supply (V) 89 69 87 67 85 65 83 63 81 61 79 59 77 57 2.5 3 55 3.5 Differential Clock Amplitude (VPP) Figure 23. Performance Across Input Clock Amplitude Copyright © 2011–2017, Texas Instruments Incorporated THD (dBc) SFDR (dBc) 2.5 3 63 3.5 72 THD SNR 73 71 2 2 Input Frequency = 10MHz 91 1.5 1.5 94 SNR (dBFS) SFDR SNR 93 1 1 Figure 22. Performance Across Input Clock Amplitude 75 Input Frequency = 150MHz 0.5 0.5 Differential Clock Amplitude (VPP) 95 0 72 87 79 Figure 21. Performance Across DRVDD Supply Voltage 75 SFDR SNR 88 71.5 1.75 85 89 SNR SFDR 92 1.7 60 Figure 20. SNR Across Temperature vs AVDD Supply 72 94 82 1.65 35 Temperature (°C) SNR (dBFS) −15 90 71.5 86 71 82 70.5 78 40 45 50 55 60 SNR (dBFS) 60 −40 70 Input Clock Duty Cycle (%) Figure 24. Performance Across Input Clock Duty Cycle Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 21 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 7.14 Typical Characteristics: ADS4125 At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 0 0 SFDR = 86.9dBc SNR = 71.2dBFS SINAD = 71dBFS THD = 83.9dBc −20 −20 −40 Amplitude (dB) Amplitude (dB) −40 −60 −60 −80 −80 −100 −100 −120 SFDR = 82.4dBc SNR = 70.5dBFS SINAD = 70.1dBFS THD = 80.5dBc 0 10 20 30 40 50 −120 60 0 10 20 Frequency (MHz) Figure 25. FFT for 20-MHz Input Signal SFDR = 79.7dBc SNR = 70dBFS SINAD = 69.5dBFS THD = 78.3dBc −40 Amplitude (dB) Amplitude (dB) 60 Each Tone at −7dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two−Tone IMD = 87.7dBFS SFDR = 96.7dBFS −20 −40 −60 −60 −80 −80 −100 −100 0 10 20 30 40 50 −120 60 0 10 20 30 40 50 60 Frequency (MHz) Frequency (MHz) Figure 27. FFT for 300-MHz Input Signal Figure 28. FFT for Two-Tone Input Signal 0 90 Each Tone at −36dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two−Tone IMD = 99.4dBFS SFDR = 106.3dBFS −20 85 80 SFDR (dBc) −40 Amplitude (dB) 50 0 −20 −60 75 −80 70 −100 65 −120 22 40 Figure 26. FFT for 170-MHz Input Signal 0 −120 30 Frequency (MHz) 0 10 20 30 40 50 60 60 0 50 100 150 200 250 300 350 400 Frequency (MHz) Input Frequency (MHz) Figure 29. FFT for Two-Tone Input Signal Figure 30. SFDR vs Input Frequency Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Typical Characteristics: ADS4125 (continued) At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 71.5 96 High Perf MODE1 Enabled Default 170MHz 220MHz 300MHz 400MHz 92 71 88 70.5 SFDR (dBc) SNR (dBFS) 84 70 80 76 69.5 72 69 68 68.5 0 50 100 150 200 250 300 350 64 400 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Input Frequency (MHz) Gain (dB) Figure 31. SNR vs Input Frequency Figure 32. SFDR Across Gain and Input Frequency 72 74 120 170MHz 220MHz 71 300MHz 400MHz Input Frequency = 40MHz SFDR (dBFS) SFDR (dBc) SNR 110 73.5 73 100 SFDR (dBc, dBFS) SINAD (dBFS) 69 68 67 66 90 72.5 80 72 70 71.5 60 71 50 70.5 40 70 30 69.5 20 69 SNR (dBFS) 70 65 64 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 10 −45 6 −40 −35 Gain (dB) SFDR (dBFS) SFDR (dBc) SNR 70 71.5 60 71 50 70.5 40 70 30 69.5 −25 −20 −15 −10 −5 0 69 Amplitude (dBFS) Figure 35. Performance Across Input Amplitude (Single Tone) Copyright © 2011–2017, Texas Instruments Incorporated SFDR (dBc) 72 SNR (dBFS) SFDR (dBc, dBFS) 72.5 80 −30 −5 0 68.5 71 Input Frequency = 150MHz 90 −35 −10 90 73 −40 −15 SFDR SNR 73.5 100 20 −45 −20 Figure 34. Performance Across Input Amplitude (Single Tone) 74 120 Input Frequency = 150MHz −25 Amplitude (dBFS) Figure 33. SINAD Across Gain and Input Frequency 110 −30 86 70.5 82 70 78 69.5 74 69 70 0.8 0.85 0.9 0.95 1 1.05 SNR (dBFS) 63 68.5 1.1 Input Common−Mode Voltage (V) Figure 36. Performance vs Input Common-Mode Voltage Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 23 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Typical Characteristics: ADS4125 (continued) At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 73 100 Input Frequency = 150MHz 1.65 1.7 1.75 1.8 96 92 1.85 1.9 1.95 Input Frequency = 150MHz 72 88 1.85 1.9 1.95 71 SNR (dBFS) 84 SFDR (dBc) 1.65 1.7 1.75 1.8 80 76 70 69 72 68 68 64 −15 10 35 60 67 −40 85 −15 10 Temperature (°C) Figure 37. SFDR Across Temperature vs AVDD Supply Input Frequency =150MHz SFDR (dBc) SFDR (dBc) 70.5 82 SNR (dBFS) 71 84 70 80 69.5 78 1.8 1.85 69 1.95 1.9 74 Input Frequency = 40MHz 73 87 72 86 71 85 70 84 69 83 68 82 67 81 66 80 65 79 0 0.5 1 DRVDD Supply (V) 1.5 2 2.5 64 3.5 3 Differential Clock Amplitude (VPP) Figure 39. Performance Across DRVDD Supply Voltage Figure 40. Performance Across Input Clock Amplitude 73 73 72 72 91 71 71 89 70 87 69 85 68 83 67 81 66 79 65 77 64 65 75 63 64 62 63 SFDR SNR 93 Default Low−Speed Mode Enabled 70 SNR (dBFS) Input Frequency = 150MHz SNR (dBFS) 95 SFDR (dBc) SFDR SNR 88 71.5 1.75 85 89 SNR SFDR 86 1.7 60 Figure 38. SNR Across Temperature vs AVDD Supply 72 88 76 1.65 35 Temperature (°C) SNR (dBFS) 60 −40 69 68 67 66 Input Frequency = 10MHz 73 0 0.5 1 1.5 2 2.5 3 3.5 4 Differential Clock Amplitude (VPP) Figure 41. Performance Across Input Clock Amplitude 24 Submit Documentation Feedback 30 35 40 45 50 55 60 65 70 Input Clock Duty Cycle (%) Figure 42. SNR Across Input Clock Duty Cycle Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 7.15 Typical Characteristics: ADS4142 At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 0 0 SFDR = 83.4dBc SNR = 74.3dBFS SINAD = 73.7dBFS THD = 82dBc −20 −20 −40 Amplitude (dB) Amplitude (dB) −40 −60 −60 −80 −80 −100 −100 −120 SFDR = 83dBc SNR = 72.8dBFS SINAD = 72.4dBFS THD = 81.6dBc 0 5 10 15 20 25 −120 30 32.5 0 5 10 Frequency (MHz) Figure 43. FFT for 20-MHz Input Signal 25 30 32.5 0 SFDR = 70.7dBc SNR = 68.4dBFS SINAD = 66.3dBFS THD = 69.3dBc −20 Each Tone at −7dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two−Tone IMD = 88.7dBFS SFDR = 96.6dBFS −20 −40 Amplitude (dB) −40 Amplitude (dB) 20 Figure 44. FFT for 170-MHz Input Signal 0 −60 −60 −80 −80 −100 −100 −120 15 Frequency (MHz) 0 5 10 15 20 25 −120 30 32.5 0 5 10 15 20 25 30 32.5 Frequency (MHz) Frequency (MHz) Figure 45. FFT for 300-MHz Input Signal Figure 46. FFT for Two-Tone Input Signal 0 93 Each Tone at −36dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two−Tone IMD = 99dBFS SFDR = 105.3dBFS −20 88 83 SFDR (dBc) Amplitude (dB) −40 −60 78 73 −80 68 −100 −120 63 0 5 10 15 20 25 30 32.5 58 0 50 100 150 200 250 300 350 400 Frequency (MHz) Input Frequency (MHz) Figure 47. FFT for Two-Tone Input Signal Figure 48. SFDR vs Input Frequency Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 25 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Typical Characteristics: ADS4142 (continued) At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 74 98 High Perf MODE1 Enabled Default 73 90 72.5 86 72 82 71.5 71 74 70 70 66 69.5 62 0 50 100 150 200 250 300 350 58 400 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Input Frequency (MHz) Gain (dB) Figure 49. SNR vs Input Frequency Figure 50. SFDR Across Gain and Input Frequency 77 120 170MHz 220MHz 72 300MHz 400MHz Input Frequency = 40MHz SFDR (dBFS) SFDR (dBc) SNR 110 71 76.5 76 70 100 69 90 75.5 80 75 70 74.5 60 74 63 50 73.5 62 40 73 30 72.5 SFDR (dBc, dBFS) 68 67 66 65 64 SNR (dBFS) 73 SINAD (dBFS) 300MHz 400MHz 78 70.5 69 170MHz 220MHz 94 SFDR (dBc) SNR (dBFS) 73.5 61 60 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 20 −70 6 −60 Gain (dB) Input Frequency = 150MHz SFDR (dBFS) SFDR (dBc) SNR 110 70 74.5 60 74 50 73.5 40 73 30 72.5 −20 −10 0 72 Figure 53. Performance Across Input Amplitude (Single Tone) Submit Documentation Feedback SFDR (dBc) 75 SNR (dBFS) SFDR (dBc, dBFS) 75.5 80 Amplitude (dBFS) 26 0 72 74 Input Frequency = 150MHz 90 −30 −10 90 76 −40 −20 SFDR SNR 76.5 100 −50 −30 Figure 52. Performance Across Input Amplitude (Single Tone) 77 120 −60 −40 Amplitude (dBFS) Figure 51. SINAD Across Gain and Input Frequency 20 −70 −50 86 73.5 82 73 78 72.5 74 72 70 0.8 0.85 0.9 0.95 1 1.05 SNR (dBFS) 59 71.5 1.1 Input Common−Mode Voltage (V) Figure 54. Performance vs Input Common-Mode Voltage Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Typical Characteristics: ADS4142 (continued) At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 75 100 Input Frequency = 150MHz 1.65 1.7 1.75 1.8 96 1.85 1.9 1.95 Input Frequency = 150MHz 1.65 1.7 1.75 1.8 74 1.85 1.9 1.95 92 73 SNR (dBFS) SFDR (dBc) 88 84 80 72 76 71 72 70 68 10 35 60 69 −40 85 −15 10 Temperature (°C) Figure 55. SFDR Across Temperature vs AVDD Supply 76 73.5 90 73 88 72.5 86 72 84 71.5 1.8 1.85 1.9 SFDR (dBc) Input Frequency = 40MHz 92 1.75 71 1.95 75 88 74 87 73 86 72 85 71 84 70 83 69 0 DRVDD Supply (V) 85 70 83 68 81 66 79 64 77 62 75 60 2.5 3 58 3.5 Differential Clock Amplitude (VPP) Figure 59. Performance Across Input Clock Amplitude Copyright © 2011–2017, Texas Instruments Incorporated THD (dBc) SFDR (dBc) 2.5 3 68 3.5 74.5 THD SNR 74 72 2 2 Input Frequency = 10MHz 87 1.5 1.5 94 SNR (dBFS) SFDR SNR 89 1 1 Figure 58. Performance Across Input Clock Amplitude 76 Input Frequency = 150MHz 0.5 0.5 Differential Clock Amplitude (VPP) 91 0 SFDR SNR 89 82 Figure 57. Performance Across DRVDD Supply Voltage 73 85 90 SNR SFDR SNR (dBFS) SFDR (dBc) Input Frequency =150MHz 1.7 60 Figure 56. SNR Across Temperature vs AVDD Supply 74 94 82 1.65 35 Temperature (°C) SNR (dBFS) −15 90 74 86 73.5 82 73 78 40 45 50 55 60 SNR (dBFS) 64 −40 72.5 Input Clock Duty Cycle (%) Figure 60. Performance Across Input Clock Duty Cycle Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 27 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Typical Characteristics: ADS4142 (continued) At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 50 1.5 45 1 40 Code Occurrence (%) 35 INL (LSB) 0.5 0 −0.5 30 25 20 15 10 −1 5 −1.5 0 2048 4096 6144 8192 10240 12288 14336 16384 Output Code (LSB) Figure 61. Integral Nonlinearity 28 Submit Documentation Feedback 0 8168 8169 8170 8171 8172 8173 8174 8175 8176 Output Code (LSB) Figure 62. Output Noise Histogram (With Inputs Shorted to VCM) Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 7.16 Typical Characteristics: ADS4145 At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 0 0 SFDR = 86dBc SNR = 74dBFS SINAD =73.7dBFS THD = 83.5dBc −20 −20 −40 Amplitude (dB) Amplitude (dB) −40 −60 −60 −80 −80 −100 −100 −120 SFDR = 82.5dBc SNR = 72.8dBFS SINAD = 72.2dBFS THD = 80.1dBc 0 10 20 30 40 50 −120 60 0 10 20 Frequency (MHz) Figure 63. FFT for 20-MHz Input Signal SFDR = 80dBc SNR = 72dBFS SINAD = 71.3dBFS THD = 78.5dBc 60 Each Tone at −7dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two−Tone IMD = 87.7dBFS SFDR = 97.5dBFS −20 −40 Amplitude (dB) −40 Amplitude (dB) 50 0 −20 −60 −60 −80 −80 −100 −100 0 10 20 30 40 50 −120 60 0 10 20 30 40 50 60 Frequency (MHz) Frequency (MHz) Figure 65. FFT for 300-MHz Input Signal Figure 66. FFT for Two-Tone Input Signal 0 90 Each Tone at −36dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two−Tone IMD = 99.2dBFS SFDR = 106.6dBFS −20 85 80 SFDR (dBc) −40 Amplitude (dB) 40 Figure 64. FFT for 170-MHz Input Signal 0 −120 30 Frequency (MHz) −60 75 −80 70 −100 65 −120 0 10 20 30 40 50 60 60 0 50 100 150 200 250 300 350 400 Frequency (MHz) Input Frequency (MHz) Figure 67. FFT for Two-Tone Input Signal Figure 68. SFDR vs Input Frequency Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 29 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Typical Characteristics: ADS4145 (continued) At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 74 96 170MHz 220MHz 73.5 92 73 88 72.5 84 SFDR (dBc) 72 80 71.5 76 71 72 70.5 68 70 0 50 100 150 200 250 300 350 64 400 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Input Frequency (MHz) Gain (dB) Figure 69. SNR vs Input Frequency Figure 70. SFDR Across Gain and Input Frequency 74 76.5 120 170MHz 220MHz 73 300MHz 400MHz Input Frequency = 40MHz SFDR (dBFS) SFDR (dBc) SNR 110 72 76 75.5 100 71 SFDR (dBc, dBFS) 70 SINAD (dBFS) 300MHz 400MHz 69 68 67 66 65 90 75 80 74.5 70 74 60 73.5 50 73 40 72.5 SNR (dBFS) SNR (dBFS) High Perf MODE1 Enabled Default 64 63 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 30 −70 6 −60 Gain (dB) Input Frequency = 150MHz SFDR (dBFS) SFDR (dBc) SNR 110 70 74 60 73.5 50 73 40 72.5 30 72 −20 −10 0 71.5 Figure 73. Performance Across Input Amplitude (Single Tone) Submit Documentation Feedback SFDR (dBc) 74.5 SNR (dBFS) SFDR (dBc, dBFS) 75 80 Amplitude (dBFS) 30 0 72 74 Input Frequency = 150MHz 90 −30 −10 90 75.5 −40 −20 SFDR SNR 76 100 −50 −30 Figure 72. Performance Across Input Amplitude (Single Tone) 76.5 120 −60 −40 Amplitude (dBFS) Figure 71. SINAD Across Gain and Input Frequency 20 −70 −50 86 73.5 82 73 78 72.5 74 72 70 0.8 0.85 0.9 0.95 1 1.05 SNR (dBFS) 62 71.5 1.1 Input Common−Mode Voltage (V) Figure 74. Performance vs Input Common-Mode Voltage Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Typical Characteristics: ADS4145 (continued) At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 75 100 Input Frequency = 150MHz 1.65 1.7 1.75 1.8 96 92 1.85 1.9 1.95 Input Frequency = 150MHz 74 88 1.85 1.9 1.95 73 SNR (dBFS) 84 SFDR (dBc) 1.65 1.7 1.75 1.8 80 76 72 71 72 68 70 64 −15 10 35 60 69 −40 85 −15 10 Temperature (°C) Figure 75. SFDR Across Temperature vs AVDD Supply Input Frequency =150MHz SFDR (dBc) SFDR (dBc) 71.5 84 SNR (dBFS) 72 86 71 82 70.5 80 1.8 1.85 70 1.95 1.9 76 Input Frequency = 40MHz SFDR SNR 89 72.5 1.75 85 90 SNR SFDR 88 1.7 60 Figure 76. SNR Across Temperature vs AVDD Supply 73 90 78 1.65 35 Temperature (°C) 75 88 74 87 73 86 72 85 71 84 70 83 69 82 68 81 67 80 0 0.5 1 DRVDD Supply (V) 1.5 2 2.5 3 3.5 4 SNR (dBFS) 60 −40 66 Differential Clock Amplitude (VPP) Figure 77. Performance Across DRVDD Supply Voltage Figure 78. Performance Across Input Clock Amplitude 76 75 89 74 74 86 72 83 70 80 68 77 66 74 64 71 62 67 60 66 92 Input Frequency = 150MHz SFDR SNR Default Low−Speed Mode Enabled 73 SNR (dBFS) SNR (dBFS) SFDR (dBc) 72 71 70 69 68 Input Frequency = 10MHz 68 0 0.5 1 1.5 2 2.5 3 3.5 4 Differential Clock Amplitude (VPP) Figure 79. Performance Across Input Clock Amplitude Copyright © 2011–2017, Texas Instruments Incorporated 30 35 40 45 50 55 60 65 70 Input Clock Duty Cycle (%) Figure 80. SNR Across Input Clock Duty Cycle Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 31 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Typical Characteristics: ADS4145 (continued) At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 35 1.5 30 1 Code Occurrence (%) 25 INL (LSB) 0.5 0 −0.5 20 15 10 −1 −1.5 5 0 2048 4096 6144 8192 10240 12288 14336 16384 Output Code (LSB) Figure 81. Integral Nonlinearity 32 Submit Documentation Feedback 0 8170 8171 8172 8173 8174 8175 8176 8177 8178 8179 Output Code (LSB) Figure 82. Output Noise Histogram (With Inputs Shorted to VCM) Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 7.17 Typical Characteristics: Common At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 0 0 PSRR on AVDD Supply 50mVPP −10 −10 −20 −20 PSRR (dB) CMRR (dB) Input Frequency = 70MHz 50mVPP Signal Superimposed on Input Common−Mode Voltage (0.95V) −30 −30 −40 −40 −50 −50 −60 0 50 100 150 200 250 −60 300 0 10 20 Frequency of Input Common−Mode Signal (MHz) Figure 83. CMRR vs Frequency 40 50 60 70 80 90 100 Figure 84. PSRR vs Frequency 70 130 AVDD Power DRVDD Power 200mV Swing DRVDD Power 350mV Swing 120 LVDS, 200mV Swing LVDS, 350mV Swing CMOS, 6pF Load Capacitance CMOS, 8pF Load Capacitance 65 60 110 55 100 50 DRVDD Current (mA) Power (mW) 30 Frequency of Signal on Supply (MHz) 90 80 70 45 40 35 30 25 60 20 50 15 10 40 30 5 5 25 45 65 85 Sampling Frequency (MSPS) 105 Figure 85. Power vs Sample Rate Copyright © 2011–2017, Texas Instruments Incorporated 125 0 5 25 45 65 85 Sampling Frequency (MSPS) 105 125 Figure 86. DRVDD Current vs Sample Rate Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 33 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 7.18 Typical Characteristics: Contour At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 125 120 125 120 84 75 81 87 67 71 63 90 84 80 87 84 87 70 60 81 75 67 71 78 84 63 84 50 87 84 40 75 84 87 71 87 90 69 90 84 70 77 87 60 87 87 69 81 50 73 81 55 77 65 69 84 87 50 100 150 200 250 300 350 400 20 50 100 150 61 200 Input Frequency (MHz) 60 55 65 250 300 350 400 Input Frequency (MHz) 70 75 80 60 85 65 70 75 SFDR (dBc) 80 85 90 SFDR (dBc) Figure 87. SFDR Across Input and Sampling Frequencies (0dB Gain) Figure 88. SFDR Across Input and Sampling Frequencies (6dB Gain) 125 120 125 120 72.5 73 73.5 110 72 100 90 80 72 72.5 73 70 73.5 60 71 69 70 50 40 69 72 30 72.5 73.5 69 73 66 20 20 50 100 150 200 250 300 90 80 67 68 70 67.5 66.5 60 50 67 350 66.5 67 68 69 65.5 66 65 20 400 20 50 100 150 200 Input Frequency (MHz) 66 66 66.5 67 67.5 68 30 67 68 67 100 40 68 70 71 67.5 110 70 71 Sampling Frequency (MSPS) Sampling Frequency (MSPS) 73 20 20 250 300 350 400 67.5 68 Input Frequency (MHz) 70 71 64 73 72 64.5 65 65.5 66 SNR (dBFS) 66.5 67 SNR (dBFS) Figure 89. ADS414x: SNR ACROSS Input and Sampling Frequencies (0-dB Gain) Figure 90. ADS414x: SNR Across Input and Sampling Frequencies (6-dB Gain) 125 120 125 120 70.5 71 110 70 110 69.5 100 Sampling Frequency (MSPS) Sampling Frequency (MSPS) 73 80 30 59 63 67 20 69 90 80 70 69.5 70.5 71 70 60 68 50 69 40 69.5 30 70.5 70 100 150 71 69 90 80 67 70 66 66.5 60 50 65.5 66 30 66 67 66.5 67 100 40 67 68 20 67 66 66.5 65 65.5 64.5 20 20 50 200 250 300 350 400 20 50 100 150 200 Input Frequency (MHz) 65 66 67 68 69 70 71 64 64.5 65 SNR (dBFS) Submit Documentation Feedback 250 300 350 64 400 Input Frequency (MHz) Figure 91. ADS412x SNR Across Input and Sampling Frequencies (0-dB Gain) 34 77 81 87 75 84 84 100 40 78 81 30 87 90 78 100 87 87 87 110 Sampling Frequency (MSPS) Sampling Frequency (MSPS) 110 84 65.5 66 66.5 67 SNR (dBFS) Figure 92. ADS412x SNR Across Input and Sampling Frequencies (6-dB Gain) Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 8 Detailed Description 8.1 Overview The ADS412x and ADS414x devices are high-performance, low-power, 12-bit and 14-bit analog-to-digital converters (ADCs) with maximum sampling rates up to 65 MSPS and 125 MSPS. The conversion process is initiated by a rising edge of the external input clock when the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge, the sample propagates through the pipeline, resulting in a data latency of 10 clock cycles. The output is available as 12-bit and 14-bit data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary twos complement format. The ADS412x and ADS414x family is pin-compatible to the previous generation ADS6149 family; this architecture enables easy migration. However, there are some important differences between the generations, summarized in Table 1. Table 1. Migrating from the ADS6149 Family ADS6149 FAMILY ADS4145 FAMILY PINS Pin 21 is NC (not connected) Pin 21 is NC (not connected) Pin 23 is MODE Pin 23 is RESERVED in the ADS4145 family. It is reserved as a digital control pin for an (as yet) undefined function in the next-generation ADC series. SUPPLY AVDD is 3.3 V AVDD is 1.8 V DRVDD is 1.8 V No change INPUT COMMON-MODE VOLTAGE VCM is 1.5 V VCM is 0.95 V SERIAL INTERFACE Protocol: 8-bit register address and 8-bit register data No change in protocol New serial register map EXTERNAL REFERENCE MODE Supported Not supported ADS61B49 FAMILY ADS41B29, ADS41B49, ADS58B18 FAMILY PINS Pin 21 is NC (not connected) Pin 21 is 3.3 V AVDD_BUF (supply for the analog input buffers) Pin 23 is MODE Pin 23 is a digital control pin for the RESERVED function. Pin 23 functions as SNR Boost enable (B18 only). SUPPLY AVDD is 3.3 V AVDD is 1.8 V, AVDD_BUF is 3.3 V DRVDD is 1.8 V No change INPUT COMMON-MODE VOLTAGE VCM is 1.5 V VCM is 1.7 V SERIAL INTERFACE Protocol: 8-bit register address and 8-bit register data No change in protocol New serial register map EXTERNAL REFERENCE MODE Supported Not supported Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 35 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 8.2 Functional Block Diagrams AVDD AGND DRVDD DDR LVDS Interface DRGND CLKP CLKOUTP CLOCKGEN CLKOUTM CLKM D0_D1_P D0_D1_M D2_D3_P D2_D3_M Low-Latency Mode (Default After Reset) INP INM 12-Bit ADC Sampling Circuit Common Digital Functions D4_D5_P DDR Serializer D4_D5_M D6_D7_P D6_D7_M D8_D9_P D8_D9_M Control Interface Reference VCM D10_D11_P D10_D11_M OVR_SDOUT DFS SEN SDATA SCLK RESET ADS412x OE Figure 93. ADS412x Block Diagram 36 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Functional Block Diagrams (continued) AVDD AGND DRVDD DDR LVDS Interface DRGND CLKOUTP CLKP CLOCKGEN CLKOUTM CLKM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M Low-Latency Mode (Default After Reset) INP INM 14-Bit ADC Sampling Circuit Common Digital Functions D6_D7_P DDR Serializer D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M Control Interface Reference VCM D12_D13_P D12_D13_M OVR_SDOUT DFS SEN SDATA SCLK RESET ADS414x OE Figure 94. ADS414x Block Diagram Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 37 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 8.3 Feature Description 8.3.1 Digital Functions and Low-Latency Mode The device has several useful digital functions such as test patterns, gain, and offset correction. All of these functions require extra clock cycles for operation and increase the overall latency and power of the device. Alternately, the device has a low-latency mode in which the raw ADC output is routed to the output data pins with a latency of 10 clock cycles. In this mode, the digital functions are bypassed. Figure 95 shows more details of the processing after the ADC. The device is in low-latency mode after reset. In order to use any of the digital functions, the low-latency mode must first be disabled by setting the DIS LOW LATENCY register bit to 1. After this process, the respective register bits must be programmed as described in the following sections and in the Serial Register Map section. Output Interface 14-Bit ADC 14b 14b Digital Functions (Gain, Offset Correction, Test Patterns) DDR LVDS or CMOS DIS LOW LATENCY Pin Figure 95. Digital Processing Block Diagram 8.3.2 Gain for SFDR, SNR Trade-Off The ADS412x and ADS414x include gain settings that can be used to improve SFDR performance. The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps) using the GAIN register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 2. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.5 dB and 1 dB. The SNR degradation is reduced at high input frequencies. As a result, the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR. After a reset, the device is in low-latency mode and gain function is disabled. To use gain: • First, disable the low-latency mode (DIS LOW LATENCY = 1). • This setting enables the gain and puts the device in a 0-dB gain mode. • For other gain settings, program the GAIN bits. Table 2. Full-Scale Range Across Gains GAIN (dB) TYPE FULL-SCALE (VPP) 0 Default after reset 2 1 Programmable 1.78 2 Programmable 1.59 3 Programmable 1.42 4 Programmable 1.26 5 Programmable 1.12 6 Programmable 1 38 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 8.3.3 Offset Correction The ADS412x and ADS414x have an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The correction can be enabled using the EN OFFSET CORR serial register bit. When enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR TIME CONSTANT register bits, as described in Table 3. Table 3. Time Constant of Offset Correction Loop OFFSET CORR TIME CONSTANT TIME CONSTANT, TCCLK (Number of Clock Cycles) TIME CONSTANT, TCCLK × 1/fS (sec) (1) 0000 1M 8 ms 0001 2M 16 ms 0010 4M 33.4 ms 0011 8M 67 ms 0100 16M 134 ms 0101 32M 268 ms 0110 64M 537 ms 0111 128M 1.08 s 1000 256M 2.15 s 1001 512M 4.3 s 1010 1G 8.6 s 1011 2G 17.2 s 1100 Reserved — 1101 Reserved — 1110 Reserved — 1111 Reserved — (1) Sampling frequency, fS = 125 MSPS. After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. When frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabled by a default after reset. After a reset, the device is in low-latency mode and offset correction is disabled. To use offset correction: • First, disable the low-latency mode (DIS LOW LATENCY = 1). • Then set EN OFFSET CORR to 1 and program the required time constant. Figure 96 shows the time response of the offset correction algorithm after being enabled. Output Code (LSB) OFFSET CORRECTION Time Response 8200 8190 8180 8170 8160 8150 8140 8130 8120 8110 8100 8090 8080 8070 8060 8050 8181 Offset of 10 LSBs 8192 Final converged value Offset correction converges to output code of 8192 Offset correction begins -5 5 15 25 35 45 55 65 75 85 95 105 Time (ms) Figure 96. Time Response of Offset Correction Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 39 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 8.3.4 Power-Down The ADS412x and ADS414x have three power-down modes: power-down global, standby, and output buffer disable. 8.3.4.1 Power-Down Global In this mode, the entire device (including the ADC, internal reference, and the output buffers) is powered down, resulting in reduced total power dissipation of approximately 10 mW. The output buffers are in a high-impedance state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100 µs. To enter the global power-down mode, set the PDN GLOBAL register bit. 8.3.4.2 Standby In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up time of 5 µs. The total power dissipation in standby mode is approximately 130 mW at 125 MSPS. To enter the standby mode, set the STBY register bit. 8.3.4.3 Output Buffer Disable The output buffers can be disabled and put in a high-impedance state; wake-up time from this mode is fast, approximately 100 ns. Disabling the output buffers can be controlled using the PDN OBUF register bit or using the OE pin. 8.3.4.4 Input Clock Stop In addition, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The power dissipation is approximately 80 mW. 8.3.5 Output Data Format Two output data formats are supported: twos complement and offset binary. Each mode can be selected using the DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. 8.4 Device Functional Modes 8.4.1 Digital Output Information The ADS412x and ADS414x provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the data. 8.4.1.1 Output Interface Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. These options can be selected using the LVDS CMOS serial interface register bit or using the DFS pin. 40 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Device Functional Modes (continued) 8.4.1.2 DDR LVDS Outputs In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 97 and Figure 98. Pins Pins CLKOUTP CLKOUTP Output Clock Output Clock CLKOUTM CLKOUTM D0_D1_P D0_D1_P Data Bits D0, D1 Data Bits D0, D1 D0_D1_M LVDS Buffers LVDS Buffers D0_D1_M D2_D3_P Data Bits D2, D3 D2_D3_M D2_D3_P Data Bits D2, D3 D2_D3_M D4_D5_P D4_D5_P 12-Bit ADC Data Data Bits D4, D5 D4_D5_M Data Bits D4, D5 14-Bit ADC Data D4_D5_M D6_D7_P D6_D7_P Data Bits D6, D7 Data Bits D6, D7 D6_D7_M D6_D7_M D8_D9_P D8_D9_P Data Bits D8, D9 Data Bits D8, D9 D8_D9_M D8_D9_M D10_D11_P D10_D11_P Data Bits D10, D11 Data Bits D10, D11 D10_D11_M D10_D11_M ADS412x D12_D13_P Data Bits D12, D13 Figure 97. ADS412x LVDS Data Outputs D12_D13_M ADS414x Figure 98. ADS414x LVDS Data Outputs Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 41 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Device Functional Modes (continued) Even data bits (D0, D2, D4, and so forth) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5, and so forth) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all 14 data bits, as shown in Figure 99. CLKOUTP CLKOUTM D0_D1_P, D0_D1_M D0 D1 D0 D1 D2_D3_P, D2_D3_M D2 D3 D2 D3 D4_D5_P, D4_D5_M D4 D5 D4 D5 D6_D7_P, D6_D7_M D6 D7 D6 D7 D8_D9_P, D8_D9_M D8 D9 D8 D9 D10_D11_P, D10_D11_M D10 D11 D10 D11 D12_D13_P, D12_D13_M D12 D13 D12 D13 Sample N Sample N + 1 Figure 99. DDR LVDS Interface 42 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Device Functional Modes (continued) 8.4.1.3 LVDS Output Data and Clock Buffers The equivalent circuit of each LVDS output buffer is shown in Figure 100. After reset, the buffer presents an output impedance of 100 Ω to match with the external 100-Ω termination. The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The VDIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV. Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively. The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, the output impedance of buffer helps improve signal integrity. VDIFF High Low OUTP External 100W Load OUTM 1.1V ROUT VDIFF Low High Use the default buffer strength to match 100-Ω external termination (ROUT = 100 Ω). To match with a 50-Ω external termination, set the LVDS STRENGTH bit (ROUT = 50 Ω). Figure 100. LVDS Buffer Equivalent Circuit Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 43 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Device Functional Modes (continued) 8.4.1.4 Parallel CMOS Interface In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 101 depicts the CMOS output interface. Pins OVR CLKOUT CMOS Output Buffers D0 D1 D2 D3 ¼ ¼ 14-Bit ADC Data D11 D12 D13 ADS414x Figure 101. CMOS Output Interface 44 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Device Functional Modes (continued) Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures a wide data stable window. TI recommends using short traces (one to two inches or 2.54 cm to 5.08 cm) terminated with less than 5-pF load capacitance, as shown in Figure 102. Use External Clock Buffer (> 200MSPS) Input Clock Receiver (FPGA, ASIC, etc.) Flip-Flops CLKOUT CMOS Output Buffers D0 D1 D2 CLKIN D0_In D1_In D2_In 14-Bit ADC Data D12 D13 D12_In D13_In ADS414x Use short traces between ADC output and receiver pins (1 to 2 inches). Figure 102. Using the CMOS Data Outputs 8.4.1.5 CMOS Interface Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current is determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital Current as a Result of CMOS Output Switching = CL × DRVDD × (N × fAVG) where: CL = load capacitance, N × FAVG = average number of output bits switching. (1) Figure 86 details the current across sampling frequencies at 2-MHz analog input frequency. Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 45 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 8.5 Programming The performance of the ADS41xx can be enhanced by writing certain SPI registers bits with minimal impact (less than 10 mW) on power consumption. Table 4 lists the device high-performance modes. Table 4. High-Performance Modes (1) (2) (3) PARAMETER DESCRIPTION Mode 1 Set the MODE 1 register bits to get best performance across sample clock and input signal frequencies. Register address = 03h, register data = 03h Mode 2 Set the MODE 2 register bit to get best performance at high input signal frequencies greater than 230 MHz. Register address = 4Ah, register data = 01h (1) (2) (3) TI recommends using these modes to obtain best performance. These modes can be set using the serial interface only. See the Serial Interface section for details on register programming. Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Device Configuration section. 8.5.1 Device Configuration The ADS412x and ADS414x have several modes that can be configured using a serial programming interface, as described in Table 5, Table 6, and Table 7. In addition, the devices have two dedicated parallel pins for quickly configuring commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors). Table 5. DFS: Analog Control Pin DESCRIPTION (Data Format, Output Interface) VOLTAGE APPLIED ON DFS 0, 100 mV, –0 mV Twos complement, DDR LVDS (3/8) AVDD ± 100 mV Twos complement, parallel CMOS (5/8) AVDD ± 100 mV Offset binary, parallel CMOS AVDD, 0 mV, –100 mV Offset binary, DDR LVDS Table 6. OE: Digital Control Pin VOLTAGE APPLIED ON OE DESCRIPTION 0 Output data buffers disabled AVDD Output data buffers enabled When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device in standby mode. To enable this functionality, the RESET pin must be tied high. In this mode, SEN and SCLK do not have any alternative functions. Keep SEN tied high and SCLK tied low on the board. Table 7. SDATA: Digital Control Pin VOLTAGE APPLIED ON SDATA DESCRIPTION 0 Normal operation Logic high Device enters standby 46 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 AVDD (5/8) AVDD 3R (5/8) AVDD GND AVDD 2R (3/8) AVDD 3R (3/8) AVDD To Parallel Pin Figure 103. Simplified Diagram to Configure the DFS Pin 8.5.2 Serial Interface The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequency from 20 MHz down to very low speeds (a few hertz) and also with a non-50% SCLK duty cycle. 8.5.2.1 Register Initialization After power-up, the internal registers must be initialized to the default values. This initialization can be accomplished in one of two ways: 1. Either through hardware reset by applying a high pulse on RESET pin (of durations greater than 10 ns), as shown in Figure 5; or 2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. 8.5.3 Serial Register Readout The serial register readout function allows the contents of the internal registers to be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially: 1. Set the READOUT register bit to 1. This setting puts the device in serial readout mode and disables any further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of the register at address 0 cannot be read in the register readout mode. 2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content must be read. 3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin. 4. The external controller can latch the contents at the falling edge of SCLK. 5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin. Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 47 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Register Address A[7:0] = 0x00 SDATA 0 0 0 0 0 Register Data D[7:0] = 0x01 0 0 0 0 0 0 0 0 0 0 1 SCLK SEN OVR_SDOUT (1) a) Enable Serial Readout (READOUT = 1) Register Address A[7:0] = 0x43 SDATA A7 A6 A5 A4 A3 A2 Register Data D[7:0] = XX (don’t care) A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 0 SCLK SEN OVR_SDOUT (2) b) Read Contents of Register 0x43. This Register Has Been Initialized with 0x40 (device is put into global power-down mode). The OVR_SDOUT pin functions as OVR (READOUT = 0). The OVR_SDOUT pin functions as a serial readout (READOUT = 1). Figure 104. Serial Readout Timing Diagram 48 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 8.6 Register Maps 8.6.1 Serial Register Map Table 8 summarizes the functions supported by the serial interface. Table 8. Serial Interface Register Map (1) REGISTER ADDRESS DEFAULT VALUE AFTER RESET REGISTER DATA A[7:0] (Hex) D[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0 00 00 0 0 0 0 0 0 RESET READOUT 01 00 LVDS SWING 0 0 03 00 0 0 0 0 0 0 25 00 GAIN DISABLE GAIN TEST PATTERNS 26 00 0 3D 00 DATA FORMAT 3F 00 CUSTOM PATTERN HIGH D[13:6] 40 00 CUSTOM PATTERN D[5:0] 0 HIGH PERF MODE 1 0 0 0 0 LVDS LVDS DATA CLKOUT STRENGTH STRENGTH EN OFFSET CORR 0 0 0 0 0 0 0 41 00 LVDS CMOS CMOS CLKOUT STRENGTH EN CLKOUT RISE 42 00 CLKOUT FALL POSN 0 0 DIS LOW LATENCY STBY 0 43 00 0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING 4A 00 0 0 0 0 0 0 0 HIGH PERF MODE 2 BF 00 OFFSET PEDESTAL 0 0 CF 00 FREEZE OFFSET CORR 0 OFFSET CORR TIME CONSTANT 0 0 DF 00 0 0 LOW SPEED 0 0 (1) 0 CLKOUT RISE POSN EN CLKOUT FALL 0 0 Multiple functions in a register can be programmed in a single write operation. 8.6.2 Description of Serial Registers For best performance, two special mode register bits must be enabled: HI PERF MODE 1 and HI PERF MODE 2. Table 9. Register Address 00h (Default = 00h) 7 0 6 0 5 0 Bits[7:2] Always write 0 Bit 1 RESET: Software reset applied 4 0 3 0 2 0 1 RESET 0 READOUT This bit resets all internal registers to the default values and self-clears to 0 (default = 1). Bit 0 READOUT: Serial readout This bit sets the serial readout of the registers. 0 = Serial readout of registers disabled; the OVR_SDOUT pin functions as an overvoltage indicator. 1 = Serial readout enabled; the OVR_SDOUT pin functions as a serial data readout. Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 49 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Table 10. Register Address 01h (Default = 00h) 7 6 5 4 3 2 1 0 LVDS SWING Bits[7:2] LVDS SWING: LVDS swing programmability (1) 000000 = 011011 = 110010 = 010100 = 111110 = 001111 = Bits[1:0] (1) 0 0 Default LVDS swing; ±350 mV with external 100-Ω termination LVDS swing increases to ±410 mV LVDS swing increases to ±465 mV LVDS swing increases to ±570 mV LVDS swing decreases to ±200 mV LVDS swing decreases to ±125 mV Always write 0 The EN LVDS SWING register bits must be set to enable LVDS swing control. Table 11. Register Address 03h (Default = 00h) 7 0 6 0 5 0 4 0 3 0 Bits[7:2] Always write 0 Bits[1:0] HI PERF MODE 1: High performance mode 1 2 0 1 0 HI PERF MODE 1 00 = Default performance after reset 01 = Do not use 10 = Do not use 11 = For best performance across sampling clock and input signal frequencies, set the HIGH PERF MODE 1 bits Table 12. Register Address 25h (Default = 00h) 7 6 5 4 GAIN Bits[7:4] 3 DISABLE GAIN 2 1 TEST PATTERNS 0 GAIN: Gain programmability These bits set the gain programmability in 0.5-dB steps. 0000 0001 0010 0011 0100 0101 0110 Bit 3 = = = = = = = 0-dB gain (default after reset) 0.5-dB gain 1.0-dB gain 1.5-dB gain 2.0-dB gain 2.5-dB gain 3.0-dB gain 0111 1000 1001 1010 1011 1100 = = = = = = 3.5-dB gain 4.0-dB gain 4.5-dB gain 5.0-dB gain 5.5-dB gain 6-dB gain DISABLE GAIN: Gain setting This bit sets the gain. 0 = Gain enabled; gain is set by the GAIN bits only if low-latency mode is disabled 1 = Gain disabled Bits[2:0] TEST PATTERNS: Data capture These bits verify data capture. 000 = Normal operation 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern 50 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 In the ADS4122/25, output data D[11:0] is an alternating sequence of 010101010101 and 101010101010. In the ADS4142/45, output data D[13:0] is an alternating sequence of 01010101010101 and 10101010101010. 100 = Outputs digital ramp In ADS4122/25, output data increments by one LSB (12-bit) every fourth clock cycle from code 0 to code 4095 In ADS4142/45, output data increments by one LSB (14-bit) every clock cycle from code 0 to code 16383 101 = Output custom pattern (use registers 3Fh and 40h for setting the custom pattern) 110 = Unused 111 = Unused Table 13. Register Address 26h (Default = 00h) 7 6 5 4 3 2 0 0 0 0 0 0 Bits[7:2] Always write 0 Bit 1 LVDS CLKOUT STRENGTH: LVDS output clock buffer strength 1 LVDS CLKOUT STRENGTH 0 LVDS DATA STRENGTH This bit determines the external termination to be used with the LVDS output clock buffer. 0 = 100-Ω external termination (default strength) 1 = 50-Ω external termination (2x strength) Bit 0 LVDS DATA STRENGTH: LVDS data buffer strength This bit determines the external termination to be used with all of the LVDS data buffers. 0 = 100-Ω external termination (default strength) 1 = 50-Ω external termination (2x strength) Table 14. Register Address 3Dh (Default = 00h) 7 6 DATA FORMAT Bits[7:6] 5 EN OFFSET CORR 4 3 2 1 0 0 0 0 0 0 DATA FORMAT: Data format selection These bits selects the data format. 00 = The DFS pin controls data format selection 10 = Twos complement 11 = Offset binary Bit 5 ENABLE OFFSET CORR: Offset correction setting This bit sets the offset correction. 0 = Offset correction disabled 1 = Offset correction enabled Bits[4:0] Always write 0 Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 51 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Table 15. Register Address 3Fh (Default = 00h) 7 CUSTOM PATTERN D13 6 CUSTOM PATTERN D12 5 CUSTOM PATTERN D11 4 CUSTOM PATTERN D10 3 CUSTOM PATTERN D9 2 CUSTOM PATTERN D8 1 CUSTOM PATTERN D7 0 CUSTOM PATTERN D6 CUSTOM PATTERN (1) Bits[7:0] These bits set the custom pattern. (1) For the ADS414x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS412x, output data bits 11 to 0 are CUSTOM PATTERN D[13:2]. Table 16. Register Address 40h (Default = 00h) 7 CUSTOM PATTERN D5 Bits[7:2] 6 CUSTOM PATTERN D4 5 CUSTOM PATTERN D3 4 CUSTOM PATTERN D2 3 CUSTOM PATTERN D1 2 CUSTOM PATTERN D0 1 0 0 0 CUSTOM PATTERN (1) These bits set the custom pattern. Bits[1:0] (1) Always write 0 For the ADS414x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS412x, output data bits 11 to 0 are CUSTOM PATTERN D[13:2]. Table 17. Register Address 41h (Default = 00h) 7 6 LVDS CMOS Bits[7:6] 5 4 CMOS CLKOUT STRENGTH 3 EN CLKOUT RISE 2 1 CLKOUT RISE POSN 0 EN CLKOUT FALL LVDS CMOS: Interface selection These bits select the interface. 00 = The DFS pin controls the selection of either LVDS or CMOS interface 10 = The DFS pin controls the selection of either LVDS or CMOS interface 01 = DDR LVDS interface 11 = Parallel CMOS interface Bits[5:4] CMOS CLKOUT STRENGTH Controls strength of CMOS output clock only. 00 = Maximum strength (recommended and used for specified timings) 01 = Medium strength 10 = Low strength 11 = Very low strength Bit 3 ENABLE CLKOUT RISE 0 = Disables control of output clock rising edge 1 = Enables control of output clock rising edge Bits[2:1] CLKOUT RISE POSN: CLKOUT rise control Controls position of output clock rising edge LVDS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 500 ps, hold increases by 500 ps 10 = Data transition is aligned with rising edge 11 = Setup reduces by 200 ps, hold increases by 200 ps 52 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 CMOS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 100 ps, hold increases by 100 ps 10 = Setup reduces by 200 ps, hold increases by 200 ps 11 = Setup reduces by 1.5 ns, hold increases by 1.5 ns Bit 0 ENABLE CLKOUT FALL 0 = Disables control of output clock fall edge 1 = Enables control of output clock fall edge Table 18. Register Address 42h (Default = 00h) 7 6 CLKOUT FALL CTRL Bits[7:6] 5 4 0 0 3 DIS LOW LATENCY 2 1 0 STBY 0 0 CLKOUT FALL CTRL Controls position of output clock falling edge LVDS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 400 ps, hold increases by 400 ps 10 = Data transition is aligned with rising edge 11 = Setup reduces by 200 ps, hold increases by 200 ps CMOS interface: 00 = Default position (timings are specified in this condition) 01 = Falling edge is advanced by 100 ps 10 = Falling edge is advanced by 200 ps 11 = Falling edge is advanced by 1.5 ns Bits[5:4] Always write 0 Bit 3 DIS LOW LATENCY: Disable low latency This bit disables low-latency mode, 0 = Low-latency mode is enabled. Digital functions such as gain, test patterns and offset correction are disabled 1 = Low-latency mode is disabled. This setting enables the digital functions. See the Digital Functions and Low Latency Mode section. Bit 2 STBY: Standby mode This bit sets the standby mode. 0 = Normal operation 1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time from standby is fast Bits[1:0] Always write 0 Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 53 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Table 19. Register Address 43h (Default = 00h) 7 0 6 PDN GLOBAL 5 0 Bit 0 Always write 0 Bit 6 PDN GLOBAL: Power-down 4 PDN OBUF 3 0 2 0 1 0 EN LVDS SWING This bit sets the state of operation. 0 = Normal operation 1 = Total power down; the ADC, internal references, and output buffers are powered down; slow wake-up time. Bit 5 Always write 0 Bit 4 PDN OBUF: Power-down output buffer This bit set the output data and clock pins. 0 = Output data and clock pins enabled 1 = Output data and clock pins powered down and put in high- impedance state Bits[3:2] Always write 0 Bits[1:0] EN LVDS SWING: LVDS swing control 00 01 10 11 = = = = LVDS swing control using LVDS SWING register bits is disabled Do not use Do not use LVDS swing control using LVDS SWING register bits is enabled Table 20. Register Address 4Ah (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Bits[7:1] Always write 0 Bit[0] HI PERF MODE 2: High performance mode 2 0 HI PERF MODE 2 This bit is recommended for high input signal frequencies greater than 230 MHz. 0 = Default performance after reset 1 = For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit Table 21. Register Address BFh (Default = 00h) 7 Bits[7:2] 6 5 4 OFFSET PEDESTAL 3 2 1 0 0 0 OFFSET PEDESTAL These bits set the offset pedestal. When the offset correction is enabled, the final converged value after the offset is corrected is the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits. 54 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com Bits[1:0] SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 ADS414x VALUE PEDESTAL 011111 011110 011101 — 000000 — 111111 111110 — 100000 31 LSB 30 LSB 29 LSB — 0 LSB — –1 LSB –2 LSB — –32 LSB Always write 0 Table 22. Register Address CFh (Default = 00h) 7 FREEZE OFFSET CORR Bit 7 6 5 0 4 3 2 OFFSET CORR TIME CONSTANT 1 0 0 0 FREEZE OFFSET CORR This bit sets the freeze offset correction. 0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set) 1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the last estimated value is used for offset correction every clock cycle. See the Offset Correction section. Bit 6 Always write 0 Bits[5:2] OFFSET CORR TIME CONSTANT These bits set the offset correction time constant for the correction loop time constant in number of clock cycles. Bits[1:0] VALUE TIME CONSTANT (Number of Clock Cycles) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1M 2M 4M 8M 16M 32M 64M 128M 256M 512M 1G 2G Always write 0 Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 55 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Table 23. Register Address DFh (Default = 00h) 7 0 6 0 5 4 LOW SPEED Bits[7:6] Always write 0 Bits[5:4] LOW SPEED: Low-speed mode 3 0 2 0 1 0 0 0 For the ADS4122/42, the low-speed mode is enabled by default after reset. 00, 01, 10, 11 = Do not use For the ADS4125/55 only: 00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for sampling rates greater than 80 MSPS. 11 = Low-speed mode enabled; this setting is recommended for sampling rates less than or equal to 80 MSPS. Bits[3:0] 56 Always write 0 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The ADS412x and ADS414x are lower sampling speed members of the ADS41xx family of ultra-low-power analog-to-digital converters (ADCs). The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 10 clock cycles. The output is available as 14-bit data or 12-bit data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary twos complement format. 9.1.1 Analog Input The analog input consists of a switched-capacitor-based, differential, sample-and-hold architecture. This differential topology results in very good ac performance even for high input frequencies at high sampling rates. The INP and INM pins must be externally biased around a common-mode voltage of 0.95 V, available on the VCM pin. For a full-scale differential input, each input INP and INM pin must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP differential input swing. The input sampling circuit has a high 3-dB bandwidth that extends up to 550 MHz (measured from the input pins to the sampled voltage). Figure 105 shows an equivalent circuit for the analog input. Sampling Switch LPKG 2nH INP 10W CBOND 1pF RESR 200W 100W INM CPAR2 1pF RESR 200W CSAMP 2pF CPAR1 0.5pF RON 15W 100W CBOND 1pF RON 15W 3pF 3pF LPKG 2nH Sampling Capacitor RCR Filter RON 15W CPAR2 1pF CSAMP 2pF Sampling Capacitor Sampling Switch Figure 105. Analog Input Equivalent Circuit 9.1.1.1 Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each input pin is recommended to damp out ringing caused by package parasitics. Low impedance (less than 50 Ω) must be present for the common-mode switching currents. This impedance can be achieved by using two resistors from each input terminated to the common-mode voltage (VCM). Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 57 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Application Information (continued) Note that the device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the glitches caused by the opening and closing of the sampling capacitors. The cutoff frequency of the RC filter involves a trade-off. A lower cutoff frequency (larger C) absorbs glitches better, but also reduces the input bandwidth and the maximum input frequency that can be supported. On the other hand, with no internal R-C filter, high input frequency can be supported but now the sampling glitches must be supplied by the external driving circuit. The inductance of the package bond wires limits the ability of the external driving circuit to support the sampling glitches. In the ADS412x and ADS414x, the R-C component values are optimized when supporting high input bandwidth (550 MHz). However, in applications where very high input frequency support is not required, filtering of the glitches can be improved further with an external R-C-R filter; see Figure 108 and Figure 109). In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. When designing the drive circuit, the ADC impedance must be considered. Figure 106 and Figure 107 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins. 5.0 Differential Input Capacitance (pF) Differential Input Resistance (kW) 100.00 10.00 1.00 0.10 0.01 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Input Frequency (GHz) Figure 106. ADC Analog Input Resistance (RIN) Across Frequency 58 4.5 Submit Documentation Feedback 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Input Frequency (GHz) Figure 107. ADC Analog Input Capacitance (CIN) Across Frequency Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Application Information (continued) 9.1.1.2 Driving Circuit Two example driving circuit configurations are shown in Figure 108 and Figure 109—one optimized for low bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies. In Figure 108, an external R-C-R filter with 3.3 pF is used to help absorb sampling glitches. The R-C-R filter limits the bandwidth of the drive circuit, making the drive circuit suitable for low input frequencies (up to 250 MHz). Transformers such as ADT1-1WT or WBC1-1 can be used up to 250 MHz. For higher input frequencies, the R-C-R filter can be dropped. Together with the lower series resistors (5 Ω to 10 Ω), this drive circuit provides higher bandwidth to support frequencies up to 500 MHz (as shown in Figure 109). A transmission line transformer such as ADTL2-18 can be used. Note that both the drive circuits have been terminated by 50 Ω near the ADC side. The termination is accomplished by a 25-Ω resistor from each input to the 0.95-V common-mode (VCM) from the device. This termination allows the analog inputs to be biased around the required common-mode voltage. 10W to 15W T2 3.6nH INP T1 0.1mF 0.1mF 25W 50W RIN 3.3pF 25W CIN 50W INM 1:1 1:1 10W to 15W 3.6nH VCM ADS41xx Figure 108. Drive Circuit With Low Bandwidth (for Low Input Frequencies) 5W to 10W T2 T1 INP 0.1mF 0.1mF 25W RIN CIN 25W INM 1:1 1:1 5W to 10W VCM ADS41xx Figure 109. Drive Circuit With High Bandwidth (for High Input Frequencies) The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 108 and Figure 109. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω source impedance). Figure 108 and Figure 109 use 1:1 transformers with a 50-Ω source. As explained in the Drive Circuit Requirements section, this architecture helps to present a low source impedance to absorb sampling glitches. With a 1:4 transformer, the source impedance is 200 Ω. The higher source impedance is unable to absorb the sampling glitches effectively and can lead to degradation in performance (compared to using 1:1 transformers). Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 59 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Application Information (continued) In almost all cases, either a band-pass or low-pass filter is needed to obtain the desired dynamic performance, as shown in Figure 110. Such a filter presents low source impedance at the high frequencies corresponding to the sampling glitch and helps avoid the performance loss with the high source impedance. 10W Bandpass or Low-Pass Filter Differential Input Signal 0.1mF INP 100W ADS41xx 100W INM 10W VCM Figure 110. Drive Circuit With 1:4 Transformer 9.1.1.3 Input Common-Mode To ensure a low-noise, common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. Each ADC input pin sinks a common-mode current of approximately 0.6 µA per MSPS of clock frequency. 9.1.2 Clock Input The ADS412x and ADS414x clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources. Figure 111 shows an equivalent circuit for the input clock. Clock Buffer LPKG 1nH 20W CLKP CBOND 1pF RESR 100W LPKG 1nH 5kW 2pF 20W CEQ CEQ VCM 5kW CLKM CBOND 1pF RESR 100W NOTE: CEQ is 1 pF to 3 pF, and is the equivalent input capacitance of the clock buffer. Figure 111. Input Clock Equivalent Circuit 60 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Application Information (continued) A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 112. For best performance, the clock inputs must be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure 113 shows a differential circuit. CMOS Clock Input 0.1mF CLKP VCM 0.1mF CLKM Figure 112. Single-Ended Clock Driving Circuit 0.1mF CLKP Differential Sine-Wave, PECL, or LVDS Clock Input 0.1mF CLKM Figure 113. Differential Clock Driving Circuit 9.1.3 Input Overvoltage Indication (OVR Pin) The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off DRVDD supply), independent of the type of output data interface (DDR, LVDS, or CMOS). For a positive overload, the D[13:0] output data bits are 3FFFh in offset binary output format and 1FFFh in twos complement output format. For a negative input overload, the output code is 0000h in offset binary output format and 2000h in twos complement output format. Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 61 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Application Information (continued) 9.1.4 Using the ADS41xx at Low Sampling Rates When ADS41xx is used at lower sampling rates (< 20 MSPS), set the LOW SPEED register bit (address DFh, bit[5:4]). At low sampling rates, use the device in CMOS interface mode which saves power and results in better setup and hold time compared to LVDS interface mode. 9.1.4.1 ADS412x (12-Bit Device) 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) ADS412x, 12-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted -40 -60 -80 -60 -80 -100 -100 -120 -120 0 0.3 0.6 0.9 Input Frequency (MHz) 1.2 0 1.5 0.5 D130 1 1.5 Input Frequency (MHz) 2 2.5 fS = 5 MSPS, fIN = 3 MHz, SNR = 70.9 dBFS, SFDR = 89 dBc, SINAD = 70.8 dBFS, THD = 87 dBc Figure 114. FFT for 3-MSPS Sampling Speed Figure 115. FFT for 5-MSPS Sampling Speed 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) fS = 3 MSPS, fIN = 4 MHz, SNR = 71 dBFS, SFDR = 94 dBc, SINAD = 70.9 dBFS, THD = 91 dBc -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 0.5 1 1.5 Input Frequency (MHz) 2 2.5 fS = 5 MSPS, fIN = 12 MHz, SNR = 70.5 dBFS, SFDR = 89 dBc, SINAD = 70.4 dBFS, THD = 87 dBc Figure 116. FFT for 5-MSPS Sampling Speed 62 -40 Submit Documentation Feedback 0 0.5 1 1.5 2 2.5 3 3.5 Input Frequency (MHz) 4 4.5 5 D103 fS = 10 MSPS, fIN = 3 MHz, SNR = 71.1 dBFS, SFDR = 89 dBc, SINAD = 71 dBFS, THD = 86 dBc Figure 117. FFT for 10-MSPS Sampling Speed Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Application Information (continued) 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) ADS412x, 12-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted -40 -60 -80 -80 -120 -120 0 0.5 1 1.5 2 2.5 3 3.5 Input Frequency (MHz) 4 4.5 0 5 2 D104 fS = 10 MSPS, fIN = 12 MHz, SNR = 70.9 dBFS, SFDR = 88 dBc, SINAD = 70.8 dBFS, THD = 86 dBc -20 -20 Amplitude (dBFS) 0 -60 -80 8 10 Figure 119. FFT for 20-MSPS Sampling Speed 0 -40 4 6 Input Frequency (MHz) fS = 20 MSPS, fIN = 3 MHz, SNR = 71.1 dBFS, SFDR = 89 dBc, SINAD = 71 dBFS, THD = 87 dBc Figure 118. FFT for 10-MSPS Sampling Speed Amplitude (dBFS) -60 -100 -100 -100 -40 -60 -80 -100 -120 -120 0 2 4 6 Input Frequency (MHz) 8 10 fS = 20 MSPS, fIN = 12 MHz, SNR = 71.1 dBFS, SFDR = 89 dBc, SINAD = 71 dBFS, THD = 87 dBc 0 5 10 15 Input Frequency (MHz) 20 25 fS = 50 MSPS, fIN = 3 MHz, SNR = 71 dBFS, SFDR = 90 dBc, SINAD = 70.9 dBFS, THD = 87 dBc Figure 120. FFT for 20-MSPS Sampling Speed Figure 121. FFT for 50-MSPS Sampling Speed 0 0.5 -20 0.3 -40 INL (LSB) Amplitude (dBFS) -40 -60 0.1 -0.1 -80 -0.3 -100 -120 -0.5 0 5 10 15 Input Frequency (MHz) 20 25 fS = 50 MSPS, fIN = 12 MHz, SNR = 71 dBFS, SFDR = 89 dBc, SINAD = 71.9 dBFS, THD = 87 dBc Figure 122. FFT for 50-MSPS Sampling Speed Copyright © 2011–2017, Texas Instruments Incorporated 0 512 1024 1536 2048 2560 Output Code (LSB) 3072 3584 4096 D131 fS = 3 MSPS, fIN = 4 MHz Figure 123. Integral Nonlinearity at 3-MSPS Sampling Speed Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 63 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Application Information (continued) 0.5 0.5 0.3 0.3 0.1 0.1 INL (LSB) DNL (LSB) ADS412x, 12-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted -0.1 -0.3 -0.1 -0.3 -0.5 -0.5 0 512 1024 1536 2048 2560 Output Code (LSB) 3072 3584 4096 0 512 fS = 3 MSPS, fIN = 4 MHz 0.5 0.5 0.3 0.3 0.1 0.1 INL (LSB) DNL (LSB) 3072 3584 4096 D100 Figure 125. Integral Nonlinearity at 5-MSPS Sampling Speed -0.1 -0.3 -0.1 -0.3 -0.5 -0.5 0 512 1024 1536 2048 2560 Output Code (LSB) 3072 3584 4096 0 512 1024 D101 fS = 5 MSPS, fIN = 3 MHz 1536 2048 2560 Output Code (LSB) 3072 3584 4096 D105 fS = 10 MSPS, fIN = 3 MHz Figure 126. Differential Non-linearity at 5-MSPS Sampling Speed Figure 127. Integral Nonlinearity at 10-MSPS Sampling Speed 0.5 0.5 0.3 0.3 0.1 0.1 INL (LSB) DNL (LSB) 1536 2048 2560 Output Code (LSB) fS = 5 MSPS, fIN = 3 MHz Figure 124. Differential Nonlinearity at 3-MSPS Sampling Speed -0.1 -0.3 -0.1 -0.3 -0.5 -0.5 0 512 1024 1536 2048 2560 Output Code (LSB) 3072 3584 4096 D106 fS = 10 MSPS, fIN = 3 MHz Figure 128. Differential Nonlinearity at 10-MSPS Sampling Speed 64 1024 D132 Submit Documentation Feedback 0 512 1024 1536 2048 2560 Output Code (LSB) 3072 3584 4096 D108 fS = 20 MSPS, fIN = 3 MHz Figure 129. Integral Nonlinearity at 20-MSPS Sampling Speed Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Application Information (continued) 0.5 0.5 0.3 0.3 0.1 0.1 INL (LSB) DNL (LSB) ADS412x, 12-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted -0.1 -0.1 -0.3 -0.3 -0.5 -0.5 0 512 1024 1536 2048 2560 Output Code (LSB) 3072 3584 0 4096 512 D109 fS = 20 MSPS, fIN = 3 MHz 1024 1536 2048 2560 Output Code (LSB) 3072 3584 4096 D111 fS = 50 MSPS, fIN = 3 MHz Figure 130. Differential Nonlinearity at 20-MSPS Sampling Speed Figure 131. Integral Nonlinearity at 50-MSPS Sampling Speed 0.5 100 fS = 5 MSPS fS = 10 MSPS fS = 20 MSPS fS = 50 MSPS 90 0.3 80 60 Count (%) DNL (LSB) 70 0.1 -0.1 50 40 30 -0.3 20 10 -0.5 3584 0 4096 D112 Figure 132. Differential Nonlinearity at 50-MSPS Sampling Speed 90 73 89 72 88 71 87 5 15 25 35 45 Sampling Frequency (MSPS) 55 86 65 fIN = 3 MHz Figure 134. Performance Across Sampling Speed Copyright © 2011–2017, Texas Instruments Incorporated 92 SNR SFDR 91 74 70 75 SNR (dBFS) 75 SNR (dBFS) Figure 133. INL Histogram Across Sampling Speed 92 SNR SFDR SFDR (dBc) 76 D129 INL (± LSB) fS = 50 MSPS, fIN = 3 MHz 74 91 73 90 72 89 71 88 70 5 15 25 35 45 Sampling Frequency (MSPS) 55 SFDR (dBc) 3072 0.4 1536 2048 2560 Output Code (LSB) 0.3 1024 0.2 512 0.1 0 87 65 fIN = 12 MHz Figure 135. Performance Across Sampling speed Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 65 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Application Information (continued) ADS412x, 12-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted 9.1.4.2 ADS414x (14-Bit Device) 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) ADS414x, 14-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted. -40 -60 -80 -60 -80 -100 -100 -120 -120 0 0.3 0.6 0.9 Input Frequency (MHz) 1.2 0 1.5 0.5 D133 1 1.5 Input Frequency (MHz) 2 2.5 fS = 5 MSPS, fIN = 3 MHz, SNR = 73.8 dBFS, SFDR = 90 dBc, SINAD = 73.7 dBFS, THD = 87 dBc Figure 136. FFT for 3-MSPS Sampling Speed Figure 137. FFT for 5-MSPS Sampling Speed 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) fS = 3 MSPS, fIN = 4 MHz, SNR = 73.8 dBFS, SFDR = 97 dBc, SINAD = 73.7 dBFS, THD = 90 dBc -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 0.5 1 1.5 Input Frequency (MHz) 2 2.5 0 0.5 1 1.5 2 2.5 3 3.5 Input Frequency (MHz) 4 4.5 5 D117 fS = 10 MSPS, fIN = 3 MHz, SNR = 73.9 dBFS, SFDR = 88 dBc, SINAD = 73.7 dBFS, THD = 86 dBc Figure 138. FFT for 5-MSPS Sampling Speed Figure 139. FFT for 10-MSPS Sampling Speed 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) fS = 5 MSPS, fIN = 12 MHz, SNR = 73 dBFS, SFDR = 89 dBc, SINAD = 72.9 dBFS, THD = 87 dBc -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 0 66 -40 0.5 1 1.5 2 2.5 3 3.5 Input Frequency (MHz) 4 4.5 5 D118 0 2 4 6 Input Frequency (MHz) 8 10 fS = 10 MSPS, fIN = 12 MHz, SNR = 73.6 dBFS, SFDR = 88 dBc, SINAD = 73.4 dBFS, THD = 86 dBc fS = 20 MSPS, fIN = 3 MHz, SNR = 74 dBFS, SFDR = 89 dBc, SINAD = 73.8 dBFS, THD = 87 dBc Figure 140. FFT for 10-MSPS Sampling Speed Figure 141. FFT for 20-MSPS Sampling Speed Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Application Information (continued) 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) ADS414x, 14-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted. -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 2 4 6 Input Frequency (MHz) 8 10 0 5 10 15 Input Frequency (MHz) 20 25 fS = 20 MSPS, fIN = 12 MHz, SNR = 73.9 dBFS, SFDR = 89 dBc, SINAD = 73.7 dBFS, THD = 87 dBc fS = 50 MSPS, fIN = 3 MHz, SNR = 73.8 dBFS, SFDR = 89 dBc, SINAD = 73.6 dBFS, THD = 86 dBc Figure 142. FFT for 20-MSPS Sampling Speed Figure 143. FFT for 50-MSPS Sampling Speed 0 2 1.5 -20 INL (LSB) Amplitude (dBFS) 1 -40 -60 -80 0.5 0 -0.5 -1 -100 -1.5 -120 -2 0 5 10 15 Input Frequency (MHz) 20 25 0 fS = 50 MSPS, fIN = 12 MHz, SNR = 73.8 dBFS, SFDR = 88 dBc, SINAD = 73.6 dBFS, THD = 86 dBc 2 2 1.5 1 1 0.5 0.5 -0.5 6144 8192 10240 12288 14336 16384 Output Code (LSB) D134 Figure 145. Integral Nonlinearity at 3-MSPS Sampling Speed 1.5 0 4096 fS = 3 MSPS, fIN = 4 MHz INL (LSB) DNL (LSB) Figure 144. FFT for 50-MSPS Sampling Speed 2048 0 -0.5 -1 -1 -1.5 -1.5 -2 -2 0 2048 4096 6144 8192 10240 12288 14336 16384 Output Code (LSB) D135 fS = 3 MSPS, fIN = 4 MHz Figure 146. Differential Nonlinearity at 3-MSPS Sampling Speed Copyright © 2011–2017, Texas Instruments Incorporated 0 2048 4096 6144 8192 10240 12288 14336 16384 Output Code (LSB) D114 fS = 5 MSPS, fIN = 3 MHz Figure 147. Integral Nonlinearity at 5-MSPS Sampling Speed Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 67 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Application Information (continued) 2 2 1.5 1.5 1 1 0.5 0.5 INL (LSB) DNL (LSB) ADS414x, 14-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted. 0 -0.5 0 -0.5 -1 -1 -1.5 -1.5 -2 -2 0 2048 4096 0 6144 8192 10240 12288 14336 16384 Output Code (LSB) D115 fS = 5 MSPS, fIN = 3 MHz 2 1.5 1.5 1 1 0.5 0.5 -0.5 0 -0.5 -1 -1 -1.5 -1.5 -2 -2 0 2048 4096 0 6144 8192 10240 12288 14336 16384 Output Code (LSB) D120 2 2 1.5 1.5 1 1 0.5 0.5 0 -0.5 6144 8192 10240 12288 14336 16384 Output Code (LSB) D122 0 -0.5 -1 -1 -1.5 -1.5 -2 4096 Figure 151. Integral Nonlinearity at 20-MSPS Sampling Speed INL (LSB) DNL (LSB) Figure 150. Differential Nonlinearity at 10-MSPS Sampling Speed 2048 fS = 20 MSPS, fIN = 3 MHz fS = 10 MSPS, fIN = 3 MHz -2 0 2048 4096 6144 8192 10240 12288 14336 16384 Output Code (LSB) D123 fS = 20 MSPS, fIN = 3 MHz Figure 152. Differential Nonlinearity at 20-MSPS Sampling Speed 68 6144 8192 10240 12288 14336 16384 Output Code (LSB) D119 Figure 149. Integral Nonlinearity at 10-MSPS Sampling Speed 2 0 4096 fS = 10 MSPS, fIN = 3 MHz INL (LSB) DNL (LSB) Figure 148. Differential Nonlinearity at 5-MSPS Sampling Speed 2048 Submit Documentation Feedback 0 2048 4096 6144 8192 10240 12288 14336 16384 Output Code (LSB) D125 fS = 50 MSPS, fIN = 3 MHz Figure 153. Integral Nonlinearity at 50-MSPS Sampling Speed Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Application Information (continued) ADS414x, 14-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted. 2 70 1.5 60 50 0.5 Count (%) 0 -0.5 40 30 20 -1 10 -1.5 -2 1.4 D128 INL (± LSB) fS = 50 MSPS, fIN = 3 MHz Figure 154. Differential Nonlinearity at 50-MSPS Sampling Speed 1.2 6144 8192 10240 12288 14336 16384 Output Code (LSB) D126 1 4096 0.8 2048 0.4 0 0 0.6 DNL (LSB) 1 fS = 5 MSPS fS = 10 MSPS fS = 20 MSPS fS = 50 MSPS Figure 155. INL Histogram Across Sampling Speed 50 40 45 35 Code Occurrence(%) Code Occurrence(%) 40 30 25 20 15 10 35 30 25 20 15 RMS = 1.1523 LSB 45 35 40 RMS = 1.104 LSB Figure 158. Output Noise Histogram (With Inputs shorted to VCM) at 20-MSPS Sampling Speed Copyright © 2011–2017, Texas Instruments Incorporated 8202 8201 8200 8202 8201 8200 D124 Output Code (LSB) 8193 8202 8201 8200 8199 0 8198 5 0 8197 10 5 8199 15 10 8196 8199 20 8198 15 25 8197 20 30 8196 25 35 8195 30 8194 Code Occurrence(%) 50 40 8195 8198 Figure 157. Output Noise Histogram (With Inputs shorted to VCM) at 10-MSPS Sampling Speed 45 8194 8197 RMS = 1.080 LSB Figure 156. Output Noise Histogram (With Inputs shorted to VCM) at 5-MSPS Sampling Speed 8193 D121 Output Code (LSB) Output Code (LSB) Code Occurrence(%) 8196 D116 8195 8193 8202 8201 8200 8199 8198 8197 8196 8195 8194 0 8193 5 0 8194 10 5 D127 Output Code (LSB) RMS = 1.072 LSB Figure 159. Output Noise Histogram (With Inputs shorted to VCM) at 50-MSPS Sampling Speed Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 69 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Application Information (continued) ADS414x, 14-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted. 92 75 92 SNR SFDR 91 73 90 72 89 71 70 5 15 25 35 45 Sampling Frequency (MSPS) 55 74 91 73 90 72 89 88 71 88 87 65 70 fIN = 3 MHz Figure 160. Performance Across Sampling Speed 70 Submit Documentation Feedback SNR (dBFS) 74 SFDR (dBc) SNR (dBFS) SNR SFDR 5 15 25 35 45 Sampling Frequency (MSPS) 55 SFDR (dBc) 75 87 65 fIN = 12 MHz Figure 161. Performance Across Sampling Speed Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Application Information (continued) ADS414x, 14-Bit Resolution, at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, CMOS output interface, and 32k-point FFT, unless otherwise noted. 9.1.4.3 Power Consumption at Low Sampling Rates Figure 162 shows typical power consumption at lower sampling rates on each supply. 160 DRVDD Power (CMOS 6 pF) AVDD Power Total Power 140 Power (mW) 120 100 80 60 40 20 0 5 15 25 35 45 Sampling Frequency (MSPS) 55 65 Figure 162. Power vs Sample Rate 9.1.4.4 Output Timing at Low Sampling Rates Table 24 describes the set-up and hold times for the digital outputs of the ADS41xx with respect to the output clock at low sampling rates. Table 24. Output Timing at Low Sampling Rates in CMOS Mode (1) SAMPLING FREQUENCY (MSPS) SETUP TIME, tSU MIN TYP HOLD TIME, tHO MAX MIN TYP MAX UNIT CMOS (Low Latency Enabled) 5 99.4 100.4 97.9 98.7 ns 10 49.0 49.7 48.5 49.3 ns 20 23.3 24.2 23.9 24.8 ns 30 15.0 15.8 15.7 16.6 ns 40 10.7 11.4 11.5 12.5 ns 50 8.2 9.0 9.1 10.0 ns CMOS (Low Latency Disabled) (1) 5 99.6 100.3 97.8 98.5 ns 10 49.1 49.7 48.2 49.1 ns 20 23.6 24.2 23.6 24.6 ns 30 15.2 15.7 15.3 16.4 ns 40 10.9 11.4 11.2 12.3 ns 50 8.4 8.9 8.6 9.8 ns Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, CLOAD = 5 pF. Minimum values are across the full temperature range: TMIN= –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V. Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 71 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 9.2 Typical Application An example schematic for a typical application of the ADS414x is shown in Figure 163. LVPECL Clock Driver AVDD 100 0.1 µF 0.1 µF 150 150 DFS CLKOUTP CLKOUTM OVR_SDOUT DRVDD DRGND 7 6 5 4 3 2 1 0.1 µF OE AVDD 0.1 µF 8 50 0.1 µF 9 5 0.1 µF To FPGA AVDD 5 DRVDD To FPGA AGND 50 CLKP 10 50 0.1 µF CLKM 11 AGND 12 0.1 µF ADC Driver 50 Set by mode of operation 0.1 µF VCM 13 48 D12_D13_P AGND 14 47 D12_D13_M INP 15 46 D10_D11_P INM 16 45 D10_D11_M AGND 17 AVDD 18 44 D8_D9_P AGND 19 42 D6_D7_P AVDD 20 41 D6_D7_M NC 21 40 D4_D5_P 43 D8_D9_M 36 DRGND 35 DRVDD 34 D0_D1_P 33 D0_D1_M 22 32 NC 22 31 NC 30 RESET 29 SCLK 28 SDATA 37 D2_D3_M AVDD 27 SEN 38 D2_D3_P AVDD 24 0.1 µF 26 AVDD 39 D4_D5_M 25 AGND AVDD 22 RESERVED 23 AVDD FPGA 22 0.1 µF 0.1 µF 22 To FPGA DVDD AVDD SPI Controller Figure 163. Example Schematic for the ADS414x 9.2.1 Design Requirements Example design requirements are listed in Table 25 for the ADC portion of the signal chain. These requirements do not necessary reflect the requirements of an actual system, but rather demonstrate why the ADS412x and ADS414x can be chosen for a system based on a set of requirements. Table 25. Example Design Requirements for the ADS412x and ADS414x DESIGN PARAMETER EXAMPLE DESIGN REQUIREMENT ADS4125 CAPABILITY Sampling rate ≥ 122.88 MSPS Max sampling rate: 125 MSPS Input frequency > 125 MHz to accommodate full 2nd Nyquist zone Large-signal, –3-dB bandwidth: 400-MHz operation SNR > 68 dBFS at –1 dFBS, 170 MHz 72.2 dBFS at –1 dBFS, 170 MHz SFDR > 77dBc at –1 dFBS, 170 MHz 81 dBc at –1 dBFS, 170 MHz Input full scale voltage 2 VPP 2 VPP Overload recovery time < 3 clock cycles 1 clock cycle Digital interface Parallel LVDS Parallel LVDS Power consumption < 200 mW per channel 153 mW per channel 72 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 9.2.2 Detailed Design Procedure 9.2.2.1 Analog Input The analog input of the ADS412x and ADS414x is typically driven by a fully differential amplifier. The amplifier must have sufficient bandwidth for the frequencies of interest. The noise and distortion performance of the amplifier affect the combined performance of the ADC and amplifier. The amplifier is often ac-coupled to the ADC to allow both the amplifier and ADC to operate at the optimal common-mode voltages. The amplifier can be dccoupled to the ADC if required. An alternate approach is to drive the ADC using transformers. DC coupling cannot be used with the transformer approach. 9.2.2.2 Clock Driver The ADS412x and ADS414x must be driven by a high-performance clock driver such as a clock jitter cleaner. The clock must have low noise to maintain optimal performance. LVPECL is the most common clocking interface, but LVDS and LVCMOS can be used as well. TI does not advise driving the clock input from an FPGA unless the noise degradation can be tolerated, such as for input signals near dc where the clock noise impact is minimal. 9.2.2.3 Digital Interface The ADS412x and ADS414x supports both LVDS and CMOS interfaces. The LVDS interface must be used for best performance when operating at maximum sampling rate. The LVDS outputs can be connected directly to the FPGA without any additional components. When using CMOS outputs resistors must be placed in series with the outputs to reduce the output current spikes to limit the performance degradation. The resistors must be large enough to limit current spikes but not so large as to significantly distort the digital output waveform. An external CMOS buffer must be used when driving distances greater than a few inches to reduce ground bounce within the ADC. 9.2.3 Application Curve Figure 164 shows the results of a 100-MHz signal sampled at 65 MHz captured by the ADS4122. 0 Amplitude (dBFS) -20 -40 -60 -80 -100 -120 0 10 20 Frequency (MHz) 30 D001 SNR = 70.11 dBFS, SFDR = 87.74 dBFS, THD = 84.33 dB, SINAD = 70.03 dBFS Figure 164. 100-MHz Signal Captured by the ADS4122 Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 73 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 10 Power Supply Recommendations The ADS412x and ADS414x have two power supplies, one analog (AVDD) and one digital (DRVDD) supply. Both supplies have a nominal voltage of 1.8 V. The AVDD supply is noise sensitive and the digital supply is not. 10.1 Sharing DRVDD and AVDD Supplies For best performance, the AVDD supply must be driven by a low noise linear regulator and separated from the DRVDD supply. AVDD and DRVDD can share a single supply but must be isolated by a ferrite bead and bypass capacitors, in a PI-filter configuration, at a minimum. The digital noise is concentrated at the sampling frequency and harmonics of the sampling frequency and could contain noise related to the sampled signal. When developing schematics, leave extra placeholders for additional supply filtering. 10.2 Using DC-DC Power Supplies DC-DC switching power supplies can be used to power DRVDD without issue. AVDD can be powered from a switching regulator. Noise and spurs on the AVDD power supply affect the SNR and SFDR of the ADC and show up near dc and as a modulated component around the input frequency. If a switching regulator is used, then the regulator must be designed to have minimal voltage ripple. Supply filtering must be used to limit the amount of spurious noise at the AVDD supply pins. Extra placeholders must be placed on the schematic for additional filtering. Optimization of filtering in the final system is likely needed to achieve the desired performance. The choice of power supply ultimately depends on the system requirements. For instance, if very low phase noise is required then use of a switching regulator is not recommended. 10.3 Power Supply Bypassing Because the ADS412x and ADS414x already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power-supply noise; thus, the optimum number of capacitors depends on the actual application. A 0.1-µF capacitor is recommended near each supply pin. The decoupling capacitors must be placed very close to the converter supply pins. 11 Layout 11.1 Layout Guidelines 11.1.1 Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide for details on layout and grounding. 11.1.2 Supply Decoupling Because the ADS412x and ADS414x already include internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum number of capacitors depends on the actual application. The decoupling capacitors must be placed very close to the converter supply pins. 11.1.3 Exposed Pad In addition to providing a path for heat dissipation, the thermal pad is also electrically internally connected to the digital ground. Therefore, solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see application notes, QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271) that are both available for download at www.ti.com. 74 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 11.2 Layout Example Figure 165. ADS412x and ADS414x EVM PCB Layout Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 75 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Device Nomenclature Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value. Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay variation (channel-to-channel). Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which specified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. Integral Nonlinearity (INL) The INL is the deviation of the ADC transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as EGREF and EGCHAN. To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN. For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) × FSideal to (1 + 0.5/100) × FSideal. Offset Error The offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts. Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN. Signal-to-Noise Ratio SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at DC and the first nine harmonics. SNR = 10Log10 PS PN (2) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding DC. 76 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 Device Support (continued) SINAD = 10Log10 PS PN + PD (3) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Effective Number of Bits (ENOB) ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. ENOB = SINAD - 1.76 6.02 (4) Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). THD = 10Log10 PS PN (5) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. DC Power-Supply Rejection Ratio (DC PSRR) DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The dc PSRR is typically given in units of mV/V. AC Power-Supply Rejection Ratio (AC PSRR) AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC output code (referred to the input), then: DVOUT PSRR = 20Log 10 (Expressed in dBc) DVSUP (6) Voltage Overload Recovery The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6-dB positive and negative overload. The deviation of the first few samples after the overload (from the expected values) is noted. Common-Mode Rejection Ratio (CMRR) CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is the resulting change of the ADC output code (referred to the input), then: DVOUT CMRR = 20Log10 (Expressed in dBc) DVCM (7) Crosstalk (only for multi-channel ADCs) This is a measure of the internal coupling of a signal from an adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 77 ADS4122, ADS4125, ADS4142, ADS4145 SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 www.ti.com Device Support (continued) (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. 12.2 Documentation Support 12.2.1 Related Documentation For Related documentation, see the following: • QFN Layout Guidelines • QFN/SON PCB Attachment • ADS414x, ADS412x EVM User Guide • ADS61xx 14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 26. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS4122 Click here Click here Click here Click here Click here ADS4125 Click here Click here Click here Click here Click here ADS4142 Click here Click here Click here Click here Click here ADS4145 Click here Click here Click here Click here Click here 12.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.6 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.7 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 78 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125, ADS4142, ADS4145 www.ti.com SBAS520C – FEBRUARY 2011 – REVISED JUNE 2017 12.8 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145 79 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS4122IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ4122 ADS4122IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ4122 ADS4125IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ4125 ADS4125IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ4125 ADS4142IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ4142 ADS4142IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ4142 ADS4145IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ4145 ADS4145IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ4145 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of