LTC2265-12/
LTC2264-12/LTC2263-12
12-Bit, 65Msps/40Msps/
25Msps Low Power Dual ADCs
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
n
DESCRIPTION
2-Channel Simultaneous Sampling ADC
71dB SNR
90dB SFDR
Low Power: 167mW/112mW/94mW Total
83mW/56mW/47mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Selectable Input Ranges: 1VP-P to 2VP-P
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm × 6mm) QFN Package
The LTC®2265-12/LTC2264-12/LTC2263-12 are 2-channel,
simultaneous sampling 12-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 71dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.3LSBRMS .
The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time
(2-lane mode) or one bit at a time (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
APPLICATIONS
Communications
Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multichannel Data Acquisition
n Nondestructive Testing
n
The ENC+ and ENC – inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer
allows high performance at full speed for a wide range of
clock duty cycles.
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
VDD
CH.1
ANALOG
INPUT
CH.2
ANALOG
INPUT
ENCODE
INPUT
+
S/H
–
+
S/H
–
1.8V
–10
–30
OUT1B
DATA
SERIALIZER
OUT2A
OUT2B
DATA
CLOCK
OUT
PLL
FRAME
GND
–20
OUT1A
12-BIT
ADC CORE
12-BIT
ADC CORE
0
OVDD
OGND
226512 TA01
SERIALIZED
LVDS
OUTPUTS
AMPLITUDE (dBFS)
1.8V
LTC2265-12, 65Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
20
10
FREQUENCY (MHz)
30
226512 TA02
22654312fb
1
LTC2265-12/
LTC2264-12/LTC2263-12
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1 and 2)
OUT1A–
OUT1A+
GND
SDO
PAR/SER
VREF
GND
SENSE
VDD
TOP VIEW
VDD
Supply Voltages
VDD, OVDD................................................. –0.3V to 2V
Analog Input Voltage (AIN +, AIN –, PAR/SER,
SENSE) (Note 3)........................... –0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS,
SDI, SCK) (Note 4)..................................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2265C, 2264C, 2263C......................... 0°C to 70°C
LTC2265I, 2264I, 2263I........................–40°C to 85°C
Storage Temperature Range....................–65°C to 150°C
40 39 38 37 36 35 34 33 32 31
+
1
30 OUT1B+
–
2
29 OUT1B–
AIN1
AIN1
VCM1 3
28 DCO+
REFH 4
27 DCO–
REFH 5
26 OVDD
41
GND
REFL 6
25 OGND
REFL 7
24 FR+
VCM2 8
23 FR–
AIN2+ 9
22 OUT2A+
–
21 OUT2A–
AIN2
10
OUT2B +
OUT2B –
GND
SDI
SCK
CS
ENC–
ENC+
VDD
VDD
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2265CUJ-12#PBF
LTC2265CUJ-12#TRPBF
LTC2265UJ-12
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2265IUJ-12#PBF
LTC2265IUJ-12#TRPBF
LTC2265UJ-12
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
LTC2264CUJ-12#PBF
LTC2264CUJ-12#TRPBF
LTC2264UJ-12
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2264IUJ-12#PBF
LTC2264IUJ-12#TRPBF
LTC2264UJ-12
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
LTC2263CUJ-12#PBF
LTC2263CUJ-12#TRPBF
LTC2263UJ-12
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2263IUJ-12#PBF
LTC2263IUJ-12#TRPBF
LTC2263UJ-12
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
22654312fb
2
LTC2265-12/
LTC2264-12/LTC2263-12
CONVERTER
CHARACTERISTICS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2265-12
PARAMETER
CONDITIONS
MIN
LTC2264-12
TYP
MAX
MIN
LTC2263-12
TYP
MAX
TYP
MAX
UNITS
l
12
Integral Linearity Error
Differential Analog Input (Note 6) l
–1
±0.3
1
–1
±0.3
1
–1
±0.3
1
LSB
Differential Linearity Error
Differential Analog Input
l
–0.5
±0.1
0.5
–0.4
±0.1
0.4
–0.5
±0.1
0.5
LSB
Offset Error
(Note 7)
l
–12
±3
12
–12
±3
12
–12
±3
12
mV
Gain Error
Internal Reference
External Reference
–2.4
–0.8
–0.8
–2.4
–0.8
–0.8
–2.4
–0.8
–0.8
0.6
%FS
%FS
Resolution (No Missing Codes)
l
12
MIN
Offset Drift
0.6
12
0.6
Bits
±20
±20
±20
µV/°C
Full-Scale Drift
Internal Reference
External Reference
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Gain Matching
External Reference
±0.2
±0.2
±0.2
%FS
±3
±3
±3
External Reference
0.32
0.32
0.32
Offset Matching
Transition Noise
mV
LSBRMS
ANALOG
INPUT
The
l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN
Analog Input Range (AIN + – AIN –)
1.7V < VDD < 1.9V
l
VIN(CM)
Analog Input Common Mode (AIN + + AIN –)/2
Differential Analog Input (Note 8)
l VCM – 100mV
VSENSE
External Voltage Reference Applied to SENSE
External Reference Mode
l
IINCM
Analog Input Common Mode Current
Per Pin, 65Msps
Per Pin, 40Msps
Per Pin, 25Msps
IIN1
Analog Input Leakage Current (No Encode)
0 < AIN +, AIN – < VDD
l
–1
1
µA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–3
3
µA
IIN3
SENSE Input Leakage Current
0.625 < SENSE < 1.3V
l
–6
6
µA
tAP
Sample-and-Hold Acquisition Delay Time
0
0.15
tJITTER
Sample-and-Hold Acquisition Delay Jitter
CMRR
Analog Input Common Mode Rejection Ratio
BW-3B
Full-Power Bandwidth
Figure 6 Test Circuit
1 to 2
0.625
VP-P
VCM
VCM + 100mV
V
1.250
1.300
V
81
50
31
µA
µA
µA
ns
psRMS
80
dB
800
MHz
22654312fb
3
LTC2265-12/
LTC2264-12/LTC2263-12
DYNAMIC
ACCURACY l denotes the specifications which apply over the full operating temperature range,
The
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2265-12
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
30MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
30MHz Input
70MHz Input
140MHz Input
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
Crosstalk
10MHz Input
MIN
l
69.9
l
77
l
84
l
69.6
TYP
MAX
71
71
70.9
70.6
LTC2264-12
MIN
69.7
90
90
89
84
79
90
90
90
90
85
70.9
70.9
70.7
70.3
69.6
–105
TYP
MAX
70.9
70.8
70.8
70.5
90
90
89
84
LTC2263-12
MIN
69.4
79
90
90
90
90
84
70.8
70.7
70.6
70.2
–105
69.2
TYP
MAX
UNITS
70.5
70.5
70.5
70.2
dBFS
dBFS
dBFS
dBFS
90
90
89
84
dBFS
dBFS
dBFS
dBFS
90
90
90
90
dBFS
dBFS
dBFS
dBFS
70.5
70.4
70.3
69.9
dBFS
dBFS
dBFS
dBFS
–105
dBc
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.5 • VDD – 25mV
0.5 • VDD
0.5 • VDD + 25mV
VCM Output Temperature Drift
±25
VCM Output Resistance
–600µA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
VREF Output Temperature Drift
1.250
±25
VREF Output Resistance
–400µA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
7
0.6
V
ppm/°C
4
1.225
UNITS
Ω
1.275
V
ppm/°C
Ω
mV/V
22654312fb
4
LTC2265-12/
LTC2264-12/LTC2263-12
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC– )
Differential Encode Mode (ENC– Not Tied to GND)
VID
Differential Input Voltage
(Note 8)
l
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
l
0.2
VIN
Input Voltage Range
ENC+, ENC– to GND
RIN
Input Resistance
(See Figure 10)
CIN
Input Capacitance
V
1.2
1.6
V
V
3.6
V
10
kΩ
3.5
pF
Single-Ended Encode Mode (ENC– Tied to GND)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
VIN
Input Voltage Range
ENC+ to GND
l
RIN
Input Resistance
(See Figure 11)
CIN
Input Capacitance
1.2
V
0.6
0
3.6
V
V
30
kΩ
3.5
pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
1.3
V
–10
0.6
V
10
µA
3
pF
200
Ω
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
l
–10
10
3
µA
pF
DIGITAL DATA OUTPUTS
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125
350
175
454
250
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125
1.250
1.250
1.375
1.375
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100
mV
mV
V
V
Ω
22654312fb
5
LTC2265-12/
LTC2264-12/LTC2263-12
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2265-12
SYMBOL PARAMETER
CONDITIONS
LTC2264-12
LTC2263-12
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
VDD
Analog Supply Voltage (Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage (Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
IVDD
Analog Supply Current Sine Wave Input
l
82
98
52
63
42
50
mA
IOVDD
Digital Supply Current
l
l
11
20
15
28
18
31
10
19
15
28
18
31
10
18
14
27
17
31
mA
mA
mA
mA
l
l
167
184
175
198
209
232
112
128
121
144
146
169
94
108
101
124
121
146
mW
mW
mW
mW
PDISS
Power Dissipation
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
PSLEEP
Sleep Mode Power
1
1
1
mW
PNAP
Nap Mode Power
60
60
60
mW
PDIFFCLK
Power Increase with Differential Encode Mode Enabled
(No Increase for Sleep Mode)
20
20
20
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2265-12
SYMBOL
PARAMETER
CONDITIONS
MIN
fS
Sampling Frequency
(Notes 10, 11)
l
5
tENCL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2
tENCH
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2
tAP
Sample-and-Hold
Acquisition Delay Time
TYP
LTC2264-12
MAX
MIN
65
5
7.69
7.69
100
100
11.88
2
7.69
7.69
100
100
11.88
2
0
TYP
LTC2263-12
MAX
MIN
40
5
12.5
12.5
100
100
19
2
12.5
12.5
100
100
19
2
0
TYP
MAX
UNITS
25
MHz
20
20
100
100
ns
ns
20
20
100
100
ns
ns
0
ns
22654312fb
6
LTC2265-12/
LTC2264-12/LTC2263-12
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
1 / (8 • fS)
1 / (7 • fS)
1 / (6 • fS)
1 / (16 • fS)
1 / (14 • fS)
1 / (12 • fS)
s
tSER
Serial Data Bit Period
Two Lanes, 16-Bit Serialization
Two Lanes, 14-Bit Serialization
Two Lanes, 12-Bit Serialization
One Lane, 16-Bit Serialization
One Lane, 14-Bit Serialization
One Lane, 12-Bit Serialization
tFRAME
FR to DCO Delay
(Note 8)
l
0.35 • tSER
0.5 • tSER
0.65 • tSER
s
tDATA
DATA to DCO Delay
(Note 8)
l
0.35 • tSER
0.5 • tSER
0.65 • tSER
s
tPD
Propagation Delay
(Note 8)
l
0.7n + 2 • tSER
1.1n + 2 • tSER
1.5n + 2 • tSER
s
tR
Output Rise Time
Data, DCO, FR, 20% to 80%
0.17
ns
tF
Output Fall Time
Data, DCO, FR, FR, 20% to 80%
0.17
ns
DCO Cycle-to-Cycle Jitter
tSER = 1ns
Pipeline Latency
60
psP-P
6
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
tH
Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
l
40
250
CS to SCK Set-Up Time
l
5
ns
SCK to CS Set-Up Time
l
5
ns
tDS
SDI Set-Up Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK Falling to SDO Valid
Readback Mode, CSDO = 20pF, RPULLUP = 2k
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2265), 40MHz
(LTC2264), or 25MHz (LTC2263), 2-lane output mode, differential ENC+/
ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless
otherwise noted.
l
ns
ns
125
ns
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2265), 40MHz
(LTC2264), or 25MHz (LTC2263), 2-lane output mode, ENC+ = singleended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential
drive, unless otherwise noted. The supply current and power dissipation
specifications are totals for the entire chip, not per channel.
Note 10: Recommended operating conditions.
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
data rate is 1000Mbps, so tSER must be greater than or equal to 1ns.
22654312fb
7
LTC2265-12/
LTC2264-12/LTC2263-12
TIMING DIAGRAMS
2-Lane Output Mode, 16-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
tENCL
ENC–
ENC+
tSER
DCO–
DCO+
tDATA
tFRAME
FR–
FR+
tSER
tPD
tSER
–
OUT#A
OUT#A+
OUT#B–
OUT#B+
D3
D1
DX*
0
D11
D9
D7
D5
D3
D1
DX*
0
D11
D9
D7
D2
D0
DY*
0
D10
D8
D6
D4
D2
D0
DY*
0
D10
D8
D6
SAMPLE N-6
SAMPLE N-5
226512 TD01
SAMPLE N-4
*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
2-Lane Output Mode, 14-Bit Serialization
tAP
ANALOG
INPUT
N+2
N+1
N
tENCH
tENCL
ENC–
ENC+
tSER
DCO–
DCO+
tDATA
tFRAME
FR–
FR+
tSER
tPD
tSER
OUT#A–
OUT#A+
OUT#B–
OUT#B+
D5
D3
D1
DX* D11
D9
D7
D5
D3
D1
DX* D11
D9
D7
D5
D3
D1
DX*
D11
D9
D7
D4
D2
D0
DY* D10
D8
D6
D4
D2
D0
DY* D10
D8
D6
D4
D2
D0
DY*
D10
D8
D6
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
SAMPLE N-3
226512 TD02
NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC–
*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
22654312fb
8
LTC2265-12/
LTC2264-12/LTC2263-12
TIMING DIAGRAMS
2-Lane Output Mode, 12-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
tENCL
ENC–
ENC+
tSER
DCO–
DCO+
tDATA
tFRAME
FR+
FR–
tPD
tSER
OUT#A–
OUT#A+
OUT#B–
OUT#B+
tSER
D7
D5
D3
D1
D11
D9
D7
D5
D3
D1
D11
D9
D7
D6
D4
D2
D0
D10
D8
D6
D4
D2
D0
D10
D8
D6
SAMPLE N-6
SAMPLE N-5
226512 TD03
SAMPLE N-4
1-Lane Output Mode, 16-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
tENCL
ENC–
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
tDATA
tSER
tPD
tSER
OUT#A–
OUT#A+
DX*
DY*
0
0
SAMPLE N-6
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
SAMPLE N-5
D1
D0
DX*
DY*
0
0
D11
D10
SAMPLE N-4
D9
D8
226512 TD04
OUT#B+, OUT#B– ARE DISABLED
*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
22654312fb
9
LTC2265-12/
LTC2264-12/LTC2263-12
TIMING DIAGRAMS
1-Lane Output Mode, 14-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
tENCL
ENC–
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
OUT#A–
OUT#A+
tDATA
tSER
tPD
D1
D0
DX*
tSER
DY*
D11
SAMPLE N-6
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DX*
DY*
SAMPLE N-5
D11
D10
D9
SAMPLE N-4
D8
226512 TD05
OUT#B+, OUT#B– ARE DISABLED
*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
1-Lane Output Mode, 12-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
tENCL
ENC–
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
OUTA–
OUTA+
tDATA
tSER
tPD
D3
D2
D1
SAMPLE N-6
tSER
D0
D11
D10
SAMPLE N-5
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D11
D10
SAMPLE N-4
D9
226512 TD06
OUTB+, OUTB– ARE DISABLED
22654312fb
10
LTC2265-12/
LTC2264-12/LTC2263-12
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
R/W
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
226512 TD07
22654312fb
11
LTC2265-12/
LTC2264-12/LTC2263-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2265-12: Differential
Nonlinearity (DNL)
1.0
0
0.8
0.8
–10
0.6
0.6
0.4
0.4
0
–0.2
–0.4
0.2
0
–0.2
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
–30
AMPLITUDE (dBFS)
0.2
–20
–40
–50
–60
–70
–80
–90
–100
0
1024
2048
3072
OUTPUT CODE
226512 G01
4096
–110
–120
LTC2265-12: 8k Point FFT,
fIN = 70MHz, –1dBFS, 65Msps
–10
–20
–20
–20
–30
–30
–30
–70
–80
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–10
–60
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
10
20
FREQUENCY (MHz)
30
0
20
10
FREQUENCY (MHz)
0
18000
16000
–20
71
70
8000
–80
6000
–90
–100
4000
20
10
FREQUENCY (MHz)
30
226512 G07
0
2049
69
68
67
2000
0
30
72
SNR (dBFS)
12000
10000
COUNT
AMPLITUDE (dBFS)
–40
–50
–70
20
10
FREQUENCY (MHz)
226512 G06
14000
–30
–60
0
LTC2265-12: SNR vs Input
Frequency, –1dBFS, 2V Range,
65Msps
LTC2265-12: Shorted Input
Histogram
–10
–110
–120
30
226512 G05
226512 G04
LTC2265-12: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
65Msps
30
LTC2265-12: 8k Point FFT,
fIN = 140MHz, –1dBFS, 65Msps
0
–50
10
20
FREQUENCY (MHz)
226512 G03
–10
–40
0
226512 G02
LTC2265-12: 8k Point FFT,
fIN = 30MHz, –1dBFS, 65Msps
AMPLITUDE (dBFS)
LTC2265-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 65Msps
1.0
DNL ERROR (LSB)
INL ERROR (LSB)
LTC2265-12: Integral
Nonlinearity (INL)
2050
2051
2052
OUTPUT CODE
2053
226512 G08
66
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
226512 G09
22654312fb
12
LTC2265-12/
LTC2264-12/LTC2263-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2265-12: SFDR vs Input
Frequency, –1dBFS, 2V Range,
65Msps
LTC2265-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 65Msps
95
SFDR (dBc AND dBFS)
90
85
80
75
80
70
dBc
60
60
50
40
30
50
30
20
10
10
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
350
226512 G10
71
1-LANE, 3.5mA
IOVDD (mA)
20
70
0
72
2-LANE, 3.5mA
80
70
2-LANE, 1.75mA
10
69
68
1-LANE, 1.75mA
65
67
0
10
20
30
40
50
SAMPLE RATE (Msps)
0
60
0
10
20
30
40
50
SAMPLE RATE (Msps)
226512 G13
66
60
0.6
0.4
0.4
–0.4
–0.4
–0.8
–1.0
–1.0
1024
2048
3072
OUTPUT CODE
4096
226512 G16
–30
–0.2
–0.8
1.3
–20
0
–0.6
1.2
0
0.2
–0.6
0
0.9
1
1.1
SENSE PIN (V)
–10
AMPLITUDE (dBFS)
0.8
0.6
DNL ERROR (LSB)
0.8
0
0.8
LTC2264-12: 8k Point FFT, fIN =
5MHz, –1dBFS, 40Msps
1.0
–0.2
0.7
226512 G15
LTC2264-12: Differential
Nonlinearity (DNL)
1.0
0.2
0.6
226512 G14
LTC2264-12: Integral Nonlinearity
(INL)
INL ERROR (LSB)
–10
LTC2265-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
30
85
60
–40
–30
–20
INPUT LEVEL(dBFS)
226512 G12
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dBFS
90
75
–50
226512 G11
LTC2265-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
IVDD (mA)
0
–60
0
SNR (dBFS)
65
dBc
40
20
70
dBFS
70
dBFS
SNR (dBc AND dBFS)
90
SFDR (dBFS)
80
110
100
LTC2265-12: SNR vs Input Level,
fIN = 70MHz, 2V Range, 65Msps
–40
–50
–60
–70
–80
–90
–100
0
1024
2048
3072
OUTPUT CODE
4096
226512 G17
–110
–120
0
10
FREQUENCY (MHz)
20
226512 G18
22654312fb
13
LTC2265-12/
LTC2264-12/LTC2263-12
TYPICAL PERFORMANCE CHARACTERISTICS
0
LTC2264-12: 8k Point FFT,
fIN = 69MHz, –1dBFS, 40Msps
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
LTC2264-12: 8k Point FFT,
fIN = 29MHz, –1dBFS, 40Msps
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
20
10
FREQUENCY (MHz)
0
226512 G19
0
14000
–40
12000
–60
–70
71
70
SNR (dBFS)
–30
COUNT
10000
8000
–80
6000
–90
–100
4000
67
2000
0
0
2049
20
10
FREQUENCY (MHz)
2050
2051
2052
OUTPUT CODE
226512 G22
110
95
100
90
SFDR (dBc AND dBFS)
90
80
75
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
LTC2264-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
60
dBFS
55
80
70
60
50
350
226512 G24
LTC2264-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 40Msps
dBc
50
40
30
45
20
70
66
2053
226512 G23
LTC2264-12: SFDR vs Input
Frequency, –1dBFS, 2V Range,
40Msps
85
69
68
IVDD (mA)
AMPLITUDE (dBFS)
72
16000
–20
SFDR (dBFS)
226512 G21
18000
–10
20
10
FREQUENCY (MHz)
LTC2264-12: SNR vs Input
Frequency, –1dBFS, 2V Range,
40Msps
LTC2264-12: Shorted Input
Histogram
–50
0
226512 G20
LTC2264-12: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
40Msps
–110
–120
20
10
FREQUENCY (MHz)
LTC2264-12: 8k Point FFT,
fIN = 139MHz, –1dBFS, 40Msps
10
65
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
226512 G25
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
226512 G26
40
0
10
20
30
SAMPLE RATE (Msps)
40
226512 G27
22654312fb
14
LTC2265-12/
LTC2264-12/LTC2263-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2264-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
INL ERROR (LSB)
71
SNR (dBFS)
70
69
68
67
66
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
–0.2
–0.4
–0.2
–0.4
–0.6
–0.8
0
1024
2048
3072
OUTPUT CODE
–1.0
4096
LTC2263-12: 8k Point FFT,
fIN = 5MHz, –1dBFS, 25Msps
0
LTC2263-12: 8k Point FFT,
fIN = 30MHz, –1dBFS, 25Msps
0
–10
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dBFS)
–10
–50
–40
–50
–60
–70
–80
–70
–80
–110
–120
–110
–120
–110
–120
0
5
FREQUENCY (MHz)
10
226512 G31
LTC2263-12: 8k Point FFT,
fIN = 140MHz, –1dBFS, 25Msps
0
18000
–20
–20
–30
–30
14000
–40
12000
–70
16000
–50
COUNT
–60
–60
–70
10000
8000
–80
6000
–90
–100
–90
–100
4000
–110
–120
–110
–120
–80
0
5
FREQUENCY (MHz)
10
226512 G34
10
LTC2263-12: Shorted Input
Histogram
–10
–40
5
FREQUENCY (MHz)
226512 G33
LTC2263-12: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
25Msps
–10
–50
0
226512 G32
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
LTC2263-12: 8k Point FFT,
fIN = 70MHz, –1dBFS, 25Msps
–60
–90
–100
10
4096
–40
–90
–100
5
FREQUENCY (MHz)
2048
3072
OUTPUT CODE
–50
–90
–100
0
1024
226512 G30
–10
–40
0
226512 G29
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–0.8
226512 G28
0
0.2
–0.6
–1.0
1.3
DNL ERROR (LSB)
72
LTC2263-12: Differential
Nonlinearity (DNL)
LTC2263-12: Integral Nonlinearity
(INL)
2000
0
5
FREQUENCY (MHz)
0
2049
10
226512 G35
2050
2051
2052
OUTPUT CODE
2053
226512 G36
22654312fb
15
LTC2265-12/
LTC2264-12/LTC2263-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2263-12: SNR vs Input
Frequency, –1dBFS, 2V Range,
25Msps
LTC2263-12: SFDR vs Input
Frequency, –1dBFS, 2V Range,
25Msps
72
95
71
90
70
85
110
LTC2263-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 25Msps
69
68
80
75
67
70
66
65
dBFS
90
SFDR (dBc AND dBFS)
SFDR (dBFS)
SNR (dBFS)
100
80
70
dBc
60
50
40
30
20
10
0
100 150 200 250 300
INPUT FREQUENCY (MHz)
50
350
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
226512 G37
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
350
226512 G39
226512 G38
LTC2263-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
50
72
LTC2263-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
DCO Cycle-Cycle Jitter vs Serial
Data Rate
350
300
PEAK-TO-PEAK JITTER (ps)
71
45
SNR (dBFS)
IVDD (mA)
70
40
69
68
35
67
30
0
5
10
15
20
SAMPLE RATE (Msps)
25
226512 G40
66
0
250
200
150
100
50
0.6
0.7
0.8
0.9 1.0 1.1
SENSE PIN (V)
1.2
1.3
226512 G41
0
0
200
400
600
800
SERIAL DATA RATE (Mbps)
1000
226512 G42
22654312fb
16
LTC2265-12/
LTC2264-12/LTC2263-12
PIN FUNCTIONS
AIN1+ (Pin 1): Channel 1 Positive Differential Analog
Input.
AIN1– (Pin 2): Channel 1 Negative Differential Analog
Input.
VCM1 (Pin 3): Common Mode Bias Output, Nominally Equal
to VDD /2. VCM should be used to bias the common mode
of the analog inputs of channel 1. Bypass to ground with
a 0.1µF ceramic capacitor.
REFH (Pins 4, 5): ADC High Reference. Bypass to pins 6, 7
with a 2.2µF ceramic capacitor, and to ground with a 0.1µF
ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to pins 4, 5
with a 2.2µF ceramic capacitor, and to ground with a 0.1µF
ceramic capacitor.
VCM2 (Pin 8): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM should be used to bias the common mode
of the analog inputs of channel 2. Bypass to ground with
a 0.1µF ceramic capacitor.
AIN2+ (Pin 9): Channel 2 Positive Differential Analog
Input.
AIN2– (Pin 10): Channel 2 Negative Differential Analog
Input.
VDD (Pins 11, 12, 39, 40): Analog Power Supply, 1.7V
to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
ENC+ (Pin 13): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 14): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 15): In serial programming mode (PAR/SER = 0V),
CS is the serial interface chip select input. When CS is low,
SCK is enabled for shifting data on SDI into the mode
control registers. In parallel programming mode (PAR/SER
= VDD), CS selects 2-lane or 1-lane output mode. CS can
be driven with 1.8V to 3.3V logic.
SCK (Pin 16): In serial programming mode (PAR/SER
= 0V), SCK is the serial interface clock input. In parallel
programming mode (PAR/SER = VDD), SCK selects 3.5mA
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 17): In serial programming mode (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.
GND (Pins 18, 33, 37, Exposed Pad Pin 41): ADC Power
Ground. The exposed pad must be soldered to the PCB
ground.
OGND (Pin 25): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 26): Output Driver Supply, 1.7V to 1.9V. Bypass
to ground with a 0.1µF ceramic capacitor.
SDO (Pin 34): In serial programming mode (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k pullup resistor of 1.8V to 3.3V. If readback from the mode
control registers is not needed, the pull-up resistor is not
necessary and SDO can be left unconnected. In parallel
programming mode (PAR/SER = VDD), SDO is an input that
enables internal 100Ω termination resistors on the digital
outputs. When used as an input, SDO can be driven with
1.8V to 3.3V logic through a 1k series resistor.
22654312fb
17
LTC2265-12/
LTC2264-12/LTC2263-12
PIN FUNCTIONS
PAR/SER (Pin 35): Programming Mode Selection Pin.
Connect to ground to enable the serial programming
mode. CS, SCK, SDI and SDO become a serial interface
that controls the A/D operating modes. Connect to VDD
to enable parallel programming mode where CS, SCK,
SDI and SDO become parallel logic inputs that control a
reduced set of the A/D operating modes. PAR/SER should
be connected directly to ground or the VDD of the part and
not be driven by a logic signal.
VREF (Pin 36): Reference Voltage Output. Bypass to ground
with a 1µF ceramic capacitor, nominally 1.25V.
SENSE (Pin 38): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a
±1V input range. Connecting SENSE to ground selects
the internal reference and a ±0.5V input range. An external
reference between 0.625V and 1.3V applied to SENSE
selects an input range of ±0.8 • VSENSE.
LVDS OUTPUTS
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional internal 100Ω termination resistor between the
pins of each LVDS output pair.
OUT2B–/OUT2B+ , OUT2A–,OUT2A+ (Pins 19/20, 21/22):
Serial Data Outputs for Channel 2. In 1-lane output mode,
only OUT2A–/OUT2A+ are used.
FR–/FR+ (Pin 23/Pin 24): Frame Start Output.
DCO–/DCO+ (Pin 27/Pin 28): Data Clock Output.
OUT1B–/OUT1B+ , OUT1A–/OUT1A+ (Pins 29/30, 31/32):
Serial Data Outputs for Channel 1. In 1-lane output mode,
only OUT1A–/OUT1A+ are used.
22654312fb
18
LTC2265-12/
LTC2264-12/LTC2263-12
FUNCTIONAL BLOCK DIAGRAM
ENC+ ENC–
1.8V
1.8V
VDD
CHANNEL 1
ANALOG
INPUT
OVDD
12-BIT
ADC CORE
SAMPLEAND-HOLD
PLL
OUT1A
OUT1B
CHANNEL 2
ANALOG
INPUT
DATA
SERIALIZER
12-BIT
ADC CORE
SAMPLEAND-HOLD
OUT2A
OUT2B
VREF
1µF
1.25V
REFERENCE
DATA
CLOCK OUT
FRAME
RANGE
SELECT
REFH
REF
BUF
SENSE
REFL
OGND
VDD /2
DIFF
REF
AMP
GND
MODE
CONTROL
REGISTERS
REFH
0.1µF
REFL
VCM1
0.1µF
226512 F01
VCM2
0.1µF
PAR/SER CS SCK SDI SDO
2.2µF
0.1µF
0.1µF
Figure 1. Functional Block Diagram
22654312fb
19
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
CONVERTER OPERATION
Transformer Coupled Circuits
The LTC2265-12/LTC2264-12/LTC2263-12 are low power,
2-channel, 12-bit, 65Msps/40Msps/25Msps A/D converters that are powered by a single 1.8V supply. The analog
inputs should be driven differentially. The encode input can
be driven differentially for optimal jitter performance, or
single-ended for lower power consumption. To minimize
the number of data lines, the digital outputs are serial LVDS.
Each channel outputs two bits at a time (2-lane mode) or
one bit at a time (1-lane mode). Many additional features
can be chosen by programming the mode control registers
through a serial SPI port.
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM , setting the A/D input at its optimal DC level. At higher input frequencies a transmission
line balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differentially
around a common mode voltage set by the VCM1 or VCM2
output pins, which are nominally VDD /2. For the 2V input
range, the inputs should swing from VCM – 0.5V to VCM
+ 0.5V. There should be a 180° phase difference between
the inputs.
The two channels are simultaneously sampled by a
shared encode circuit (Figure 2).
LTC2265-12
VDD
RON
25Ω
10Ω
AIN+
CPARASITIC
1.8pF
VDD
RON
25Ω
10Ω
AIN–
CSAMPLE
3.5pF
CSAMPLE
3.5pF
CPARASITIC
1.8pF
VDD
1.2V
10k
ENC+
ENC–
10k
1.2V
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right
at the analog inputs. This lowpass filter isolates the
drive circuitry from the A/D sample-and-hold switching
and limits wideband noise from the drive circuitry.
Figure 3 shows an example of an input RC filter. The
RC component values should be chosen based on the
application’s input frequency.
226512 F02
Figure 2. Equivalent Input Circuit. Only One of
the Two Analog Channels Is Shown.
50Ω
VCM
0.1µF
0.1µF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
AIN+
LTC2265-12
0.1µF
12pF
25Ω
25Ω
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
226512 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
22654312fb
20
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
Amplifier Circuits
Figure 7 shows the analog input being driven by a high speed
differential amplifier. The output of the amplifier is ACcoupled to the A/D so the amplifier’s output common mode
voltage can be optimally set to minimize distortion.
50Ω
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
4 to 6) should convert the signal to differential before
driving the A/D.
50Ω
VCM
0.1µF
0.1µF
ANALOG
INPUT
0.1µF
0.1µF
AIN+
T2
T1
25Ω
LTC2265-12
0.1µF
2.7nH
ANALOG
INPUT
25Ω
25Ω
AIN+
LTC2265-12
0.1µF
T1
4.7pF
0.1µF
VCM
0.1µF
–
AIN
25Ω
AIN–
2.7nH
226512 F04
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 6. Recommended Front-End Circuit for Input
Frequencies Above 300MHz
Figure 4. Recommended Front-End Circuit for Input
Frequencies from 70MHz to 170MHz
50Ω
226512 F06
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
VCM
VCM
HIGH SPEED
DIFFERENTIAL
0.1µF
AMPLIFIER
0.1µF
0.1µF
ANALOG
INPUT
AIN+
T2
T1
25Ω
LTC2265-12
0.1µF
ANALOG
INPUT
+
+
–
–
1.8pF
0.1µF
25Ω
–
AIN
226512 F05
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
200Ω
200Ω
25Ω
0.1µF
AIN+
LTC2265-12
12pF
0.1µF
25Ω
AIN–
226512 F07
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
Figure 5. Recommended Front-End Circuit for Input
Frequencies from 170MHz to 300MHz
22654312fb
21
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
Reference
Encode Input
The LTC2265-12/LTC2264-12/LTC2263-12 has an internal
1.25V voltage reference. For a 2V input range using the
internal reference, connect SENSE to VDD. For a 1V input
range using the internal reference, connect SENSE to
ground. For a 2V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 9).
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE .
VREF
1µF
The reference is shared by both ADC channels, so it is
not possible to independently adjust the input range of
individual channels.
The VREF , REFH and REFL pins should be bypassed, as
shown in Figure 8. The 0.1µF capacitor between REFH and
REFL should be as close to the pins as possible (not on
the backside of the circuit board).
1.25V
EXTERNAL
REFERENCE
VREF
5Ω
1µF
Figure 9. Using an External 1.25V Reference
LTC2265-12
0.1µF
VDD
DIFFERENTIAL
COMPARATOR
VDD
1.25V BANDGAP
REFERENCE
15k
ENC+
0.625V
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR
0.625V < VSENSE < 1.300V
1µF
226512 F09
LTC2265-12
1.25V
LTC2265-12
SENSE
ENC–
RANGE
DETECT
AND
CONTROL
30k
SENSE
226512 F10
BUFFER
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
INTERNAL ADC
HIGH REFERENCE
REFH
LTC2265-12
2.2µF
0.1µF
0.1µF
0.8x
DIFF AMP
1.8V TO 3.3V
0V
REFL
INTERNAL ADC
LOW REFERENCE
ENC+
ENC–
30k
CMOS LOGIC
BUFFER
226512 F11
226512 F08
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
Figure 8. Reference Circuit
22654312fb
22
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
above VDD (up to 3.6V), and the common mode range
is from 1.1V to 1.6V. In the differential encode mode,
ENC – should stay at least 200mV above ground to avoid
falsely triggering the single-ended encode mode. For
good jitter performance ENC+ should have fast rise and
fall times.
The single-ended encode mode should be used with
CMOS encode inputs. To select this mode, ENC – is connected to ground and ENC+ is driven with a square wave
encode input. ENC+ can be taken above VDD (up to 3.6V)
so 1.8V to 3.3V CMOS logic levels can be used. The
ENC+ threshold is 0.9V. For good jitter performance
ENC+ should have fast rise and fall times.
time (1-lane mode). The data can be serialized with 16-,
14-, or 12-bit serialization (see the Timing Diagrams section for details).
The output data should be latched on the rising and falling
edges of the data clockout (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins. In the 2-lane, 14-bit serialization
mode, the frequency of the FR output is halved.
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will depend on the serialization mode as well as the speed grade
of the ADC (see Table 1). The minimum sample rate for
all serialization modes is 5Msps.
0.1µF
50Ω
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25µs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
ENC+
T1
0.1µF
100Ω
50Ω
0.1µF
ENC–
226512 F12
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
0.1µF
DIGITAL OUTPUTS
The digital outputs of the LTC2265-12/LTC2264-12/
LTC2263-12 are serialized LVDS signals. Each channel
outputs two bits at a time (2-lane mode) or one bit at a
LTC2265-12
PECL OR
LVDS
CLOCK
ENC+
LTC2265-12
0.1µF
ENC–
226512 F13
Figure 13. PECL or LVDS Encode Drive
22654312fb
23
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2265-12. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2264-12) or 25MHz (LTC2263-12).
MAXIMUM SAMPLING
FREQUENCY, fS (MHz)
SERIALIZATION MODE
DCO FREQUENCY
FR FREQUENCY
SERIAL DATA RATE
2-Lane
16-Bit Serialization
65
4 • fS
fS
8 • fS
2-Lane
14-Bit Serialization
65
3.5 • fS
0.5 • fS
7 • fS
2-Lane
12-Bit Serialization
65
3 • fS
fS
6 • fS
1-Lane
16-Bit Serialization
62.5
8 • fS
fS
16 • fS
1-Lane
14-Bit Serialization
65
7 • fS
fS
14 • fS
1-Lane
12-Bit Serialization
65
6 • fS
fS
12 • fS
By default the outputs are standard LVDS levels: a 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
DATA FORMAT
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
In addition to the 12 data bits (D11 - D0), two additional
bits (DX and DY) are sent out in the 14-bit and 16-bit
serialization modes. These extra bits are to ensure complete software compatibility with the 14-bit versions of
these A/Ds. During normal operation when the analog
inputs are not overranged, DX and DY are always logic 0.
When the analog inputs are overranged positive, DX and DY
become logic 1. When the analog inputs are overranged
negative, DX and DY become logic 0. DX and DY can also
be controlled by the digital output test pattern. See the
Timing Diagrams section for more information.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current can
be adjusted by control register A2 in serial programming
mode. Available current levels are 1.75mA, 2.1mA, 2.5mA,
3mA, 3.5mA, 4mA and 4.5mA. In parallel programming
mode the SCK pin can select either 3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing. In
parallel programming mode the SDO pin enables internal
termination. Internal termination should only be used with
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>+1.000000V
1111 1111 1111
0111 1111 1111
11
+0.999512V
1111 1111 1111
0111 1111 1111
00
+0.999024V
1111 1111 1110
0111 1111 1110
00
+0.000488V
1000 0000 0001
0000 0000 0001
00
0.000000V
1000 0000 0000
0000 0000 0000
00
–0.000488V
0111 1111 1111
1111 1111 1111
00
–0.000976V
0111 1111 1110
1111 1111 1110
00
–0.999512V
0000 0000 0001
1000 0000 0001
00
–1.000000V
0000 0000 0000
1000 0000 0000
00
≤–1.000000V
0000 0000 0000
1000 0000 0000
00
DX, DY
22654312fb
24
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
amplitude.
The digital output is randomized by applying an exclusive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The FR and DCO outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A1.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D11-D0, DX, DY) of all channels to known values. The
digital output test patterns are enabled by serially programming mode control registers A3 and A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement and randomizer.
Output Disable
The digital outputs may be disabled by serially programming mode control register A2. The current drive for all
digital outputs, including DCO and FR, are disabled to save
power or enable in-circuit testing. When disabled, the common mode of each output pair becomes high impedance,
but the differential impedance may remain low.
In nap mode any combination of A/D channels can be
powered down while the internal reference circuits and the
PLL stay active, allowing faster wake-up than from sleep
mode. Recovering from nap mode requires at least 100
clock cycles. If the application demands a very accurate DC
settling, then an additional 50µs should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
leaves nap mode. Nap mode is enabled by the mode control
register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2265-12/LTC2264-12/
LTC2263-12 can be programmed by either a parallel
interface or a simple serial interface. The serial interface
has more flexibility and can program all available modes.
The parallel interface is more limited and can only program
some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK, SDI and SDO pins are binary
logic inputs that set certain operating modes. These pins
can be tied to VDD or ground, or driven by 1.8V, 2.5V or
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 3 shows the
modes set by CS, SCK, SDI and SDO.
Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
2-Lane/1-Lane Selection Bit
0 = 2-Lane, 16-Bit Serialization Output Mode
1 = 1-Lane, 14-Bit Serialization Output Mode
SCK
LVDS Current Selection Bit
Sleep and Nap Modes
0 = 3.5mA LVDS Current Mode
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire chip is powered down,
resulting in 1mW power consumption. Sleep mode is
enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF ,
REFH and REFL. For the suggested values in Figure 8, the
A/D will stabilize after 2ms.
1 = 1.75mA LVDS Current Mode
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
SDO
Internal Termination Selection Bit
0 = Internal Termination Disabled
1 = Internal Termination Enabled
22654312fb
25
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written
to the register set by the address bits (A6:A0). If the R/W
bit is high, data in the register set by the address bits (A6:
A0) will be read back on the SDO pin (see the Timing Diagrams section). During a readback command the register
is not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back through
SDO, an external 2k pull-up resistor is required. If serial
data is only written and readback is not needed, then SDO
can be left floating and no pull-up resistor is needed. Table
4 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data bits
to logic 0. To perform a software reset, bit D7 in the reset
register is written with a logic 1. After the reset SPI write
command is complete, bit D7 is automatically set back to zero.
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
X
X
X
X
X
X
RESET
Bit 7
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode.
This Bit Is Automatically Set Back to Zero at the End of the SPI Write Command.
The Reset Register is Write Only
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_2
X
X
NAP_1
Bit 7
Clock Duty Cycle Stabilizer Bit
DCSOFF
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended.
Bit 6
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 5
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Bits 4, 3, 0
SLEEP: NAP_2: NAP_1
Sleep/Nap Mode Control Bits
000 = Normal Operation
0X1 = Channel 1 in Nap Mode
01X = Channel 2 in Nap Mode
1XX = Sleep Mode. Both Channels are disabled
Note: Any Combination of Channels Can Be Placed in Nap Mode.
Bits 1, 2
Unused, Don’t Care Bit
26
22654312fb
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE2
OUTMODE1
OUTMODE0
Bits 7-5
ILVDS2: ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 4
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0. Internal termination should only be
used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Bit 3
OUTOFF
Output Disable Bit
0 = Digital Outputs are enabled.
1 = Digital Outputs are disabled.
Bits 2-0
OUTMODE2:OUTMODE0 Digital Output Mode Control Bits
000 = 2-Lanes, 16-Bit Serialization
001 = 2-Lanes, 14-Bit Serialization
010 = 2-Lanes, 12-Bit Serialization
011 = Not Used
100 = Not Used
101 = 1-Lane, 14-Bit Serialization
110 = 1-Lane, 12-Bit Serialization
111 = 1-Lane, 16-Bit Serialization
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7
D6
D5
D4
D3
D2
D1
D0
OUTTEST
X
TP11
TP10
TP9
TP8
TP7
TP6
Bit 7
OUTTEST
Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Bit 6
Unused, Don’t Care Bit.
Bits 5-0
TP11:TP6
Test Pattern Data Bits (MSB)
TP11:TP6 Set the Test Pattern for Data Bit 11 (MSB) Through Data Bit 6.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
D7
D6
D5
D4
D3
D2
D1
D0
TP5
TP4
TP3
TP2
TP1
TP0
TPX
TPY
Bits 7-2
Test Pattern Data Bits (LSB)
TP5:TP0
TP5:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).
Bits 1-0
TPX:TPY
Set the Test Pattern for Extra Bits DX and DY. These Bits are for Compatibility with the 14-Bit Version of the A/D.
22654312fb
27
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
GROUNDING AND BYPASSING
The LTC2265-12/LTC2264-12/LTC2263-12 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD , OVDD , VCM , VREF, REFH and REFL pins. Bypass
capacitors must be located as close to the pins as possible.
Of particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2µF capacitor
between REFH and REFL can be somewhat further away.
The traces connecting the pins and bypass capacitors must
be kept short and should be made as wide as possible.
The analog inputs, encode signals and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2265-12/LTC2264-12/
LTC2263-12 is transferred from the die through the bottom-side Exposed Pad and package leads onto the printed
circuit board. For good electrical and thermal performance,
the Exposed Pad must be soldered to a large grounded
pad on the PC board. This pad should be connected to the
internal ground planes by an array of vias.
22654312fb
28
LTC2265-12/
LTC2264-12/LTC2263-12
TYPICAL APPLICATIONS
Silkscreen Top
Inner Layer 2 GND
Top Side
Inner Layer 3
22654312fb
29
LTC2265-12/
LTC2264-12/LTC2263-12
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5 Power
Bottom Side
Silkscreen Bottom
22654312fb
30
LTC2265-12/
LTC2264-12/LTC2263-12
TYPICAL APPLICATIONS
LTC2265 Schematic
PAR/SER
C4
1µF
SDO
SENSE
VDD
C5
1µF
C59
0.1µF
9
10
OUT1A–
OUT1A+
SDO
GND
VREF
PAR/SER
GND
REFH
DCO–
27
LTC2265
REFH
OVDD
26
25
REFL
OGND
REFL
FR+
VCM2
FR–
AIN2+
OUT2A+
22
–
OUT2A–
21
AIN2
VDD
AIN2
AIN2
OUT2B+
8
28
OUT2B–
7
DCO+
GND
6
VCM1
SDI
C3
0.1µF
C30
0.1µF
29
AIN1
SCK
C2
0.1µF
C1
2.2µF
5
30
OUT1B–
CS
4
OUT1B+
ENC–
3
DIGITAL
OUTPUTS
–
AIN1+
ENC+
2
VDD
1
VDD
VDD
C29
0.1µF
AIN1
SENSE
40 39 38 37 36 35 34 33 32 31
AIN1
24
OVDD
23
DIGITAL
OUTPUTS
11 12 13 14 15 16 17 18 19 20
VDD
C16
0.1µF
C7
0.1µF
C47
0.1µF
ENCODE
CLOCK
C46
0.1µF
ENCODE
CLOCK
SPI BUS
226512 TA03
22654312fb
31
LTC2265-12/
LTC2264-12/LTC2263-12
PACKAGE DESCRIPTION
UJ Package
40-Lead (6mm × 6mm) Plastic QFN
(Reference LTC DWG # 05-08-1728)
0.70 ± 0.05
6.50 ± 0.05
5.10 ± 0.05
4.42 ± 0.05
4.50 ± 0.05
(4 SIDES)
4.42 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
4.50 REF
(4-SIDES)
4.42 ± 0.10
2
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 ± 0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
22654312fb
32
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2265-12/
LTC2264-12/LTC2263-12
REVISION HISTORY
REV
DATE
DESCRIPTION
A
4/10
Revised Maximum Value for LTC2264-12 Sampling Frequency in Timing Characteristics
6
Updated Title of Curve G53 in Typical Performance Characteristics
13
Revised Descriptions and Comments in Related Parts Section
34
Revised Software Reset paragraph and Table 4 in Applications Information section
26
B
7/11
PAGE NUMBER
22654312fb
33
LTC2265-12/
LTC2264-12/LTC2263-12
RELATED PARTS
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DESCRIPTION
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Quadrature Demodulator
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24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 1900MHz, NF = 12.5dB,
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Operation, Integrated Transformer
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Amplifiers/Filters
Signal Chain Receivers
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Subsystem
22654312fb
34 Linear Technology Corporation
LT 0711 REV B • PRINTED IN USA
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