LTC3372
60V Low IQ Buck Controller
Plus 4-Channel 8A Configurable Buck DC/DCs
FEATURES
DESCRIPTION
HV Buck Controller: VIN = 4.5V to 60V, VOUT = 5V/3.3V
nn LV Buck Regulators: V
INA-H = 2.25V to 5.5V,
VOUT1‑4 ≥ 0.8V
nn 8×1A LV Buck Integrated Power Stages, Configurable
as 2, 3 or 4 Output Channels
nn 8 Unique Output Configurations (1A to 4A Per Channel)
nn Low Total No-Load Input Supply Current (I )
Q
nn 15µA HV Controller Only (5V
OUT)
nn 23μA HV Controller Only (3.3V
OUT)
nn 33μA HV Controller (3.3V
OUT) Plus One LV Regulator
nn 9μA Per Additional LV Regulator Channel
nn 1MHz to 3MHz Operation (HV Runs at 1/6 Frequency)
nn Programmable or Synchronizable to External Clock
nn Programmable Watchdog and Power-On Reset Delay
nn IC Die Temperature Monitor Output
nn Thermally Enhanced 48-Pin 7mm × 7mm QFN Package
The LTC®3372 is a highly flexible multioutput power supply
IC. The device includes a high-performance, high voltage
(HV) step-down DC/DC switching regulator controller that
drives an all N-channel synchronous power FET stage
from a 4.5V to 60V input.
nn
The LTC3372 also includes four low voltage (LV) synchronous buck regulators that can be programmed by the
C1-C3 pins to share eight 1A integrated power stages in
one of eight possible configurations. Each power stage is
powered from independent inputs which may be connected
to the HV buck’s VOUT or to other 2.25V to 5.5V supplies.
The CT pin programs timing parameters of the watchdog
timer and LV outputs’ Power-On Reset (RST). Precision
enable thresholds facilitate reliable power-up sequencing.
The LTC3372 is available in a 48-pin 7mm × 7mm
QFN package.
APPLICATIONS
All registered trademarks and trademarks are the property of their respective owners.
Automotive and Industrial Always-On Systems
nn General Purpose Multi-Channel Power Supplies
nn
TYPICAL APPLICATION
47µF
×2
100k
INTVCC
INTVCC /GND
8.06k
90
VIN
PGOOD
TG
VOUTPRG
ITH
VOUT1
1.0V
2A
VOUT2
1.2V
2A
VOUT
VINA
VINB
SWA
SWB
FB4
EN4
VINC
VIND
SWC
SWD
VINF
VINE
SWF
SWE
FB2
FB3
EN3
TEMP
WDI
WDO
PLLIN/MODE
VOUT
3.3V/5V
3A*
47µF
C1 C2 C3
RSTB
3372 TA01a
70
60
50
40
30
20
10
SENSE+
–
SENSE
VOUT /EXTVCC
VINH
VING
SWH
SWG
EN2
5mΩ
150µF
×2
BG
FB1
EN1
RT
CT
2.2µH
SW
LTC3372
TRACK/SS
GND
0.1µF
BOOST
0.01µF
VOUT
4.7µF
RUN
2.2nF
100pF
80
INTVCC
EFFICIENCY (%)
VIN
60V MAX
4.5V MIN
LV Efficiency vs Output Current
100
0
0.0001
VOUT
VOUT4
2.5V
2A
VOUT
100k
VINA–H = 3.3V
VOUT = 1.8V
fSW = 2MHz
VOUT3
1.8V
2A
INTVCC
*FULL LOAD IS EQUIVALENT TO SPECIFIED LOAD CURRENT
PLUS THE FULL LOAD INPUT CURRENT FROM VOUT1-4
0.001
0.01
0.1
OUTPUT CURRENT (A)
1A Buck
2A Buck
3A Buck
4A Buck
1
4
3372 TA01b
Low Voltage Buck Regulator Configurations
C3
0
0
0
0
1
1
1
1
C2
0
0
1
1
0
0
1
1
C1
0
1
0
1
0
1
0
1
BUCK1 BUCK2 BUCK3
2A
2A
2A
3A
1A
2A
3A
1A
1A
4A
1A
1A
3A
2A
–
4A
–
2A
4A
–
1A
4A
–
–
BUCK4
2A
2A
3A
2A
3A
2A
3A
4A
Rev. A
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1
LTC3372
TABLE OF CONTENTS
Features............................................................................................................................. 1
Applications........................................................................................................................ 1
Typical Application ................................................................................................................ 1
Description......................................................................................................................... 1
Absolute Maximum Ratings...................................................................................................... 3
Order Information.................................................................................................................. 4
Electrical Characteristics......................................................................................................... 4
Typical Performance Characteristics........................................................................................... 8
Pin Functions......................................................................................................................14
Block Diagram.....................................................................................................................17
Operation..........................................................................................................................18
Low Voltage Regulators......................................................................................................................................... 20
Applications Information........................................................................................................23
High Voltage Buck Controller................................................................................................................................. 23
Low Voltage Buck Regulators................................................................................................................................ 33
Printed Circuit Board PCB Layout Considerations.................................................................................................. 35
Typical Applications..............................................................................................................37
Package Description.............................................................................................................42
Revision History..................................................................................................................43
Typical Application...............................................................................................................44
Related Parts......................................................................................................................44
2
Rev. A
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LTC3372
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply (VIN) Voltage.......................... –0.3V to 65V
Topside Driver (BOOST) Voltage..................–0.3V to 71V
Switch (SW) Voltage...................................... –5V to 65V
(BOOST-SW) Voltage.................................... –0.3V to 6V
RUN Voltage............................................... –0.3V to 65V
TRACK/SS, VOUT/EXTVCC, SENSE+, SENSE–, PGOOD,
RT, PLL/MODE, FB1-4, EN1-4, C1-3, WDI,
WDO, RST, VINA-H Voltages........................... –0.3V to 6V
TG, BG.............................................................. (Note 11)
ITH, VOUTPRG, CT,
TEMP Voltages......................... –0.3V to (INTVCC + 0.3V)
IRST, IWDO.................................................................5mA
Operating Junction Temperature Range
(Notes 2, 3)............................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
VOUTRPG
ITH
SENSE+
SENSE–
VOUT /EXTVCC
TRACK/SS
VIN
RUN
BOOST
SW
TG
TOP VIEW
49
GND
36
35
34
33
32
31
30
29
28
27
26
25
BG
INTVCC
EN4
FB4
VINH
SWH
SWG
VING
VINF
SWF
SWE
VINE
FB2 13
EN2 14
C1 15
C2 16
C3 17
RT 18
PLL/MODE 19
WDI 20
WDO 21
CT 22
EN3 23
FB3 24
RST 1
TEMP 2
EN1 3
FB1 4
VINA 5
SWA 6
SWB 7
VINB 8
VINC 9
SWC 10
SWD 11
VIND 12
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
TJMAX = 150°C, θJA = 34°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
Rev. A
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3
LTC3372
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3372EUK#PBF
LTC3372EUK#TRPBF
LTC3372UK
48-Lead (7mm × 7mm) Plastic QFN
–40°C to 125°C
LTC3372IUK#PBF
LTC3372IUK#TRPBF
LTC3372UK
48-Lead (7mm × 7mm) Plastic QFN
–40°C to 125°C
LTC3372HUK#PBF
LTC3372HUK#TRPBF
LTC3372UK
48-Lead (7mm × 7mm) Plastic QFN
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VOUT = VINA-H = 3.3V unless
otherwise noted.
SYMBOL
PARAMETER
VIN
VIN Pin Operating Voltage Range
IQ (Forced
Continuous/
PulseSkipping
Mode)
No-Load VIN Pin DC Current
No-Load VOUT/EXTVCC Pin + SENSE– Pin
DC Current
IQ (Burst
Mode)
No-Load VIN Pin DC Current
No-Load VOUT/EXTVCC Pin DC Current
HV Controller On Only
HV Controller and One LV Regulator On
Additional IQ, per LV Regulator On
Additional IQ, Watchdog On (Float CT Pin)
Additional IQ, TEMP On (Float TEMP Pin)
No-Load SENSE– Pin DC Current
PLL/MODE = GND
(Burst Mode)
No-Load VIN Pin DC Current
HV Controller On Only
HV Controller and LV Regulator On
Additional IQ, Watchdog On (Float CT Pin)
Additional IQ, TEMP On (Float TEMP Pin)
No-Load VOUT/EXTVCC Pin DC Current
HV Controller On Only
HV Controller and One LV Regulator On
Additional IQ, per LV Regulator On
Additional IQ, Watchdog On (Float CT Pin)
Additional IQ, TEMP On (Float TEMP Pin)
CT = TEMP = INTVCC (Watchdog VOUTPRG =
l
GND
and TEMP Monitor Off, Unless
(3.3V VOUT)
Otherwise Specified)
Total No-Load Input Supply Current
HV Controller On Only
HV Controller and One LV Regulator On
Additional IQ, per LV Regulator On
Additional IQ, Watchdog On (Float CT Pin)
Additional IQ, TEMP On (Float TEMP Pin)
PLL/MODE = GND
IQ
(Note 4)
(Burst
Mode)
ISD
4
CONDITIONS
MIN
TYP
4.5
PLL/MODE = INTVCC or INTVCC /2
Run = VIN
EN1-4 = GND
No-Load VIN Pin DC Current
No-Load VOUT/EXTVCC Pin + SENSE– Pin
DC Current
60
UNITS
V
VOUTPRG =
INTVCC
(5V VOUT)
7
1450
µA
µA
VOUTPRG =
GND
(3.3V VOUT)
1300
130
µA
µA
VOUTPRG =
INTVCC
(5V VOUT)
VIN = 12V, VINA-H = VOUT (LV
Regulators Powered from HV
Regulator’s Output), No Load on
VOUT or VOUT1-4.
VIN = 12V, VINA-H = VOUT (LV
Regulators Powered from HV
Regulator’s Output), No Load on
VOUT or VOUT1-4
MAX
l
4
10
µA
l
20
52
+26
+7
+15
0.5
46
74
+39
+12
µA
µA
µA
µA
µA
µA
22
23
+1
+2
42
33
+4.2
µA
µA
µA
µA
l
4
29
+23
+6
+13
8.5
39
+33
+8
µA
µA
µA
µA
µA
l
15
31
+14
+4
+8
35
45
+20
+6
µA
µA
µA
µA
µA
23
33
+9
+3
+7
46
46
+12
+7
µA
µA
µA
µA
µA
3.5
8
μA
l
VOUTPRG =
INTVCC
(5V VOUT)
Total No-Load Input Supply Current
HV Controller On Only
HV Controller and One LV Regulator On
Additional IQ, per LV Regulator On
Additional IQ, Watchdog On (Float CT Pin)
Additional IQ, TEMP On (Float TEMP Pin)
VOUTPRG =
l
CT = TEMP = INTVCC (Watchdog GND
(3.3V
V
)
OUT
and TEMP Monitor Off, unless
otherwise specified)
VIN Pin Current in Shutdown
RUN = EN1-4 = GND
2
Rev. A
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LTC3372
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VOUT = VINA-H = 3.3V unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.875
3.217
5.000
3.300
5.125
3.383
V
V
1.17
1.22
50
1.27
V
mV
High Voltage Buck Controller
VOUT
Regulated Output Voltage
(Note 5) ITH = 0.7V to 2V
VOUTPRG = INTVCC, VIN = 6V to 60V
VOUTPRG = GND, VIN = 4.5V to 60V
VRUN
RUN Pin Controller Enable Threshold
RUN Pin Voltage Rising
Hysteresis
IRUN
RUN Pin Pull-Up Current
RUN = 0V
gm
Error Amplifier Transconductance
(Note 5) ITH = 1.2V, Sink/Source 5μA
ITRACK/SS
Soft-Start Charge Current
TRACK/SS = 0V
ISENSE+
SENSE+ Pin Current
VSENSE(MAX) Maximum Current Sense Threshold
SENSE– = 3.3V
DMAX(HV)
Maximum Duty Cycle In Dropout
RRT = 400k
TG
l
l
0.5
μA
2
7
10
mS
14
μA
±1
μA
82
mV
68
75
97.5
98
%
Top Gate Pull-Up On-Resistance
Top Gate Pull-Down On-Resistance
2.3
1.5
Ω
Ω
BG
Bottom Gate Pull-Up On-Resistance
Bottom Gate Pull-Down On-Resistance
2.4
1.1
Ω
Ω
tD(TG/BG)
Delay Time, Top Gate Off to Bottom Gate On
(Note 6)
40
ns
tD(BG/TG)
Delay Time, Bottom Gate Off to Top Gate On
(Note 6)
18
ns
tON(MIN)
Minimum On-Time (Top Gate)
(Note 7)
60
ns
PGOOD
PGOOD Pin Voltage When Low
PGOOD Pin Leakage Current When High
IPGOOD = 2mA
PGOOD = 5V
0.2
0.4
1
V
μA
UV
VOUT /EXTVCC Pin Undervoltage Threshold
Falling, Relative to Regulated VOUT
Hysteresis
–5
–7.5
2.5
–10
%
%
OV
VOUT /EXTVCC Pin Overvoltage Threshold
Rising, Relative to Regulated VOUT
Hysteresis
+5
+7.5
2.5
+10
%
%
SENSE– Pin Overvoltage Threshold
Rising, Relative to Regulated VOUT
Hysteresis
+15
2.5
%
%
tPGOOD
PGOOD Delay for Reporting OV/UV Fault
PGOOD High to Low
40
μs
INTVCC
No Load Internal VCC Regulated Voltage
INTVCC Voltage Load Regulation
6V < VIN < 60V
IINTVCC = 0mA to 50mA
No Load Internal VCC Voltage
Source Resistance
IINTVCC = 0mA to 50mA
VOUT Threshold for INTVCC Switchover from
VIN to VOUT
VOUT Rising
Hysteresis
Undervoltage Lockout (UVLO) Threshold on
INTVCC
INTVCC Voltage Rising
INTVCC Voltage Falling
Internal Bias Start Up Time
VOUT = 0V
l
VOUT = 3.3V
4.9
5.1
–1
5.3
–2
5
–2.5
VOUT = 5V
4.5
l
l
3.6
V
%
V
Ω
4.7
0.25
4.9
V
V
4.0
3.8
4.25
4.0
V
V
1.2
ms
Oscillator and Phase-Locked Loop
fOSC
Frequency of Internal Oscillator
(LV Regulators’ Switching Frequency)
VRT = INTVCC
VRT = INTVCC
RRT = 400k
l
l
1.9
1.75
1.85
fSW
HV Controller Switching Frequency
fPLL/MODE
Synchronization Frequency Range
tLOW, tHIGH > 60ns
l
1
VPLL/MODE
PLL/MODE Level High
PLL/MODE Level Low
For Synchronization
For Synchronization
l
l
1.3
VRT
RT Servo Voltage
RRT = 400k
l
770
2
2
2
2.1
2.25
2.15
1/6•fOSC
kHz
3
0.25
800
MHz
MHz
MHz
825
MHz
V
V
mV
Rev. A
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5
LTC3372
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VOUT = VINA-H = 3.3V unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
200
220
240
mV
Temperature Monitor
VTEMP(ROOM) TEMP Voltage at 25°C
∆VTEMP/°C
VTEMP Slope
7
mV/°C
OT
Overtemperature Shutdown
170
°C
OT Hyst
Overtemperature Hysteresis
10
°C
Low Voltage (LV) Buck Regulators
VINA-H
Input Operating Voltage
l
2.25
5.5
V
VOUT1-4
Regulated Output Voltage Set Point
l
0.8
VINA-H
V
UVLO
Undervoltage Lockout Threshold on VINA-H
VINA-H Falling
VINA-H Rising
l
l
1.95
2.05
2.05
2.15
2.15
2.25
V
V
IQ(VINA-H)
Quiescent Current into VINA-H Pins, Per
Enabled LV Regulator (Note 8)
Burst Mode, FB1-4 = 0.82V
Forced Continuous Mode, FB1-4 = 0V
25
400
35
550
µA
µA
ISD(VINA-H)
Shutdown Current into VINA-H Pins
0
1
µA
VFB1
VFB2-4
IFB1-4
Feedback Leakage Current
FB1-4 = 0.85V
DMAX
Maximum Duty Cycle
FB1-4 = 0V
RPMOS
PMOS On-Resistance
ISW = 100mA, 1A – Per Power Stage
290
mΩ
RNMOS
NMOS On-Resistance
ISW = –100mA, 1A – Per Power Stage
180
mΩ
ILEAKP
PMOS Leakage Current
EN1-4 = GND
–1
1
µA
ILEAKN
NMOS Leakage Current
EN1-4 = GND
–1
1
µA
tSS
Soft-Start Time
(Note 10)
UV
Rising Undervoltage RST Threshold
Regulator 1
Regulated Feedback Voltage for Regulator 1
l
792
800
808
mV
Regulated Feedback Voltage for Regulators
2-4
l
780
800
820
mV
50
nA
–50
l
100
%
0.25
1.5
3
ms
% Relative to Regulated VFB
Hysteresis
l
–4
–2
1
–1
%
%
Rising RST Undervoltage Threshold
Regulators 2-4
% Relative to Regulated VFB
Hysteresis
l
–7
–5
1
–3
%
%
OV
RST Overvoltage Threshold of Regulators
1-4
% Relative to Regulated VFB
Hysteresis
l
+5
+7.5
–3
+10
%
%
ILIM
PMOS Current Limit
1 Buck with 1 Power Stage (Note 9)
1.4
1.8
2.2
A
1 Buck with 2 Power Stages (Note 9)
3.6
A
1 Buck with 3 Power Stages (Note 9)
5.4
A
1 Buck with 4 Power Stages (Note 9)
7.2
A
Interface Logic Pins (RST, WDO, WDI, CT, C1, C2, C3)
IOH
Output High Leakage Current
RST, WDO 5.5V at Pin
VOL
Output Low Voltage
RST, WDO 3mA at Pin
VIH
WDI Input High Threshold
l
0.1
µA
0.4
V
1.2
CT, C1, C2, C3 Input High Threshold
l INTVCC – 0.4
VIL
WDI, C1, C2, C3 Input Low Threshold
l
tWDI(WIDTH)
WDI Pulse Width
l
6
1
V
V
0.4
80
V
ns
Rev. A
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LTC3372
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VOUT = VINA-H = 3.3V unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Interface Logic Pins (EN1, EN2, EN3, EN4)
VEN
Enable Rising Threshold
All LV Regulators Disabled
l
400
730
1200
mV
Enable Rising Threshold
At Least One LV Regulator Enabled
l
380
400
420
mV
l
290
315
340
mV
1
µA
Enable Falling Threshold
IEN
Enable Pin Leakage Current
EN = 3.3V
CT Timing Parameters; CT = 10nF
tWDIO
Time from WDO Low Until Next WDO Low
CT = 10nF
9.7
12.9
16.1
s
tWDI
Time from Last WDI Until Next WDO Low
CT = 10nF
1.22
1.62
2.03
s
tWDO
WDO Low Time Absent a Transition at WDI
CT = 10nF
160
202
280
ms
tRST
RST Assertion Delay
CT = 10nF
160
202
280
ms
tWDL
Watchdog Lower Boundary
CT = 10nF
38
50.6
63
ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3372 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3372E is guaranteed to meet specifications from 0°C
to 85°C operating junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3372I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTC3372H is guaranteed over the –40°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes; operating lifetime is derated for junction temperatures
greater than 125°C. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature (TJ
in °C) is calculated from the ambient temperature (TA in °C) and power
dissipation (PD in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
Note 3: This IC includes overtemperature protection which protects the
device during momentary overload conditions. Junction temperatures
will exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 4: The IQ (Total Input Supply Quiescent Current) is the total average
current drawn from the input power supply by a typical application in Burst
Mode with no load currents (from either the HV Controller VOUT or the LV
Regulators’ VOUT1-4).
Note 5: The HV Controller’s output regulation is tested in a feedback loop
that servos the ITH pin to a specified voltage and measures the resulted
voltage at VOUT/EXTVCC pin.
Note 6: Delays are measured using 50% levels, with TG and BG driving
minimum capacitive load.
Note 7: The minimum on-time conditions is specified for an inductor
peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 8: The IQ(VINA-H) (Quiescent Current into VINA-H Pins) are measured
with power switches not switching. Dynamic supply current when
switching may be higher due to the gate charge being delivered.
Note 9: The current limit features are intended to protect the IC from short
term or intermittent fault conditions. Continuous operation above the
maximum specified pin current rating may result in device degradation
over time.
Note 10: The soft-start is the time from the first top switch turn on,
after an enable rising, until the feedback has reached 90% of its nominal
regulation voltage.
Note 11: Do not apply a voltage or current source to these pins. They
must be connected to the gates of the external power MOSFETs, otherwise
permanent damage may occur.
Rev. A
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7
LTC3372
TYPICAL PERFORMANCE CHARACTERISTICS
(HV Controller) TA = 25°C, unless otherwise noted.
Efficiency and Power Loss
vs Output Current
90
VIN = 12V BURST EFFICIENCY
VOUT = 3.3V
60
FCM LOSS
PULSE–SKIPPING
LOSS
1000
80
100
50
BURST LOSS
40
10
30
PULSE–SKIPPING
EFFICIENCY
20
10
0
0.0001
1
70
60
PULSE–SKIPPING
LOSS
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
10
100
50
BURST LOSS
40
30
0
0.0001
FCM EFFICIENCY
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
3372 G01
80
98
VOUT = 5V
92
88
VOUT = 3.3V
86
84
82
80
SUPPLY CURRENT (µA)
EFFICIENCY (%)
96
90
50
HV Only
HV+1LV
HV Only
HV+1LV
70
94
fSW = 333kHz
ILOAD = 5A
60
50
VOUT = 3.3V
40
20
0
5 10 15 20 25 30 35 40 45 50 55 60
INPUT VOLTAGE (V)
35
10
25
20
15
10
3.45
3.40
3.35
3.30
3.25
VOUT = 5V
5
0
–75 –50 –25
5 10 15 20 25 30 35 40 45 50 55 60
INPUT VOLTAGE (V)
0 25 50 75 100 125 150
TEMPERATURE (°C)
3372 G05
Output Voltage vs Temperature
Forced Continuous Mode
3.50
VIN = 12V
3.45
8
7
OUTPUT VOLTAGE (V)
VIN SHUTDOWN CURRENT (µA)
9
3.50
VOUT = 3.3V
30
Shutdown Current vs Temperature
3.55
HV Only
HV+1LV
HV Only
HV+1LV
6
5
4
3
2
5.10
VIN = 12V
ILOAD = 100mA
3.40
5.05
VOUT = 5V
5.00
4.95
3.35
3.30
VOUT = 3.3V
4.90
OUTPUT VOLTAGE (V)
VIN SHUTDOWN CURRENT (µA)
40
VIN = 12V
3372 G04
Shutdown Current vs VIN
3.60
4.85
3.25
1
5 10 15 20 25 30 35 40 45 50 55 60
INPUT VOLTAGE (V)
3372 G06
8
45
10
3.65
3.20
VOUT = 5V
30
3372 G03
3.70
Burst Mode Quiescent Current
vs Temperature
SUPPLY CURRENT (µA)
100
0.1
10
3372 G02
Burst Mode Quiescent Current
vs VIN
Efficiency vs VIN
10
PULSE–SKIPPING
EFFICIENCY
1
20
0.1
1000
FCM LOSS
10
FCM EFFICIENCY
10000
VIN = 12V BURST EFFICIENCY
90 VOUT = 5V
POWER LOSS (mW)
70
100
POWER LOSS (mW)
EFFICIENCY (%)
80
10000
EFFICIENCY (%)
100
Efficiency and Power Loss
vs Output Current
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3372 G07
3.20
–75 –50 –25
4.80
0 25 50 75 100 125 150
TEMPERATURE (°C)
3372 G08
Rev. A
For more information www.analog.com
LTC3372
TYPICAL PERFORMANCE CHARACTERISTICS
(HV Controller) TA = 25°C, unless otherwise noted.
3.318
5.010
3.316
5.009
VOUT = 5V
3.314
5.008
3.312
5.007
VOUT = 3.3V
5.006
3.308
5.005
3.306
5.004
5 10 15 20 25 30 35 40 45 50 55 60
INPUT VOLTAGE (V)
80
78
76
74
72
70
68
66
64
62
60
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
80
Maximum Current Sense Voltage
vs ITH Voltage
900
PULSE–SKIPPING MODE
700
20
0
–40
5.25
600
500
400
300
200
100
–20
FORCED CONTINUOUS MODE
0
0.2
0.4
0.6 0.8
VITH (V)
1.0
–100
1.4
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0
SENSE– VOLTAGE (V)
3372 G11
INTVCC Voltage vs Gate Charge
Current VOUT = 5V
5.25
INTVCC VOLTAGE (V)
INTVCC VOLTAGE (V)
5.10
5.05
5.00
4.95
4.90
4.85
5.00
4.75
4.50
4.25
4.80
5
10
15
20
25
GATE CHARGE CURRENT (mA)
30
3372 G14
VIN = 4.5V
4.25
3.75
0
5
10
15
20
25
GATE CHARGE CURRENT (mA)
30
3372 G13
Current Limit in Foldback
5.50
0
4.50
3372 G12
5.20
4.75
4.75
INTVCC Line Regulation in
Dropout
5.15
VIN = 12V
VIN = 6V
4.00
0
1.2
INTVCC Voltage vs Gate Charge
Current VOUT = 3.3V
5.00
INTVCC VOLTAGE (V)
40 Burst Mode
OPERATION
5.25
FORCED CONTINUOUS MODE
VIN = 12V
VOUT = 5V
800
60
3372 G10
SENSE– Pin Input Bias Current
SENSE– CURRENT (µA)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
3372 G09
VOUT = 3.3V
GATE CHARGE CURRENT = 10mA
4.00
4.50 4.75 5.00 5.25 5.50 5.75 6.00 6.25 6.50
INPUT VOLTAGE (V)
3372 G15
MAXIMUM CURRENT SENSE VOLTAGE (mV)
3.310
MAXIMUM CURRENT SENSE VOLTAGE (mV)
Maximum Current Sense
Threshold vs Duty Cycle
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Output Voltage Line Regulation
Forced Continuous Mode
80
70
60
50
40
30
20
0
10 20 30 40 50 60 70 80 90 100
VOUT TO REGULATED VOLTAGE RATIO (%)
3372 G16
Rev. A
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9
LTC3372
TYPICAL PERFORMANCE CHARACTERISTICS
(HV Controller) TA = 25°C, unless otherwise noted.
TRACK/SS Pull-Up Current
vs Temperature
1.275
11.0
10.5
RUN PIN VOLTAGE (V)
TRACK/SS CURRENT (µA)
4.20
1.300
VIN = 5V
11.5
Undervoltage Lockout Threshold
vs Temperature
10.0
9.5
9.0
8.5
8.0
VIN = 12V
4.10
1.250
1.225
RISING
1.200
FALLING
1.175
1.150
7.5
7.0
–75 –50 –25
1.100
–75 –50 –25
4.00
3.95
3.90
0 25 50 75 100 125 150
TEMPERATURE (°C)
3.70
–75 –50 –25
3372 G19
Load Step Forced Continuous
Mode
Load Step Pulse-Skipping Mode
ILOAD
5A/DIV
ILOAD
5A/DIV
ILOAD
5A/DIV
IIND
5A/DIV
IIND
5A/DIV
IIND
5A/DIV
VOUT
AC–COUPLED
100mV/DIV
VOUT
AC–COUPLED
100mV/DIV
3372 G20
3372 G21
100µs/DIV
VIN = 12V
VOUT = 3.3V
ILOAD = 100mA to 8A
VIN = 12V
VOUT = 3.3V
ILOAD = 100mA to 8A
Inductor Current at Light Load
100µs/DIV
VIN = 12V
VOUT = 3.3V
ILOAD = 100mA to 8A
3372 G22
Soft Start-Up
FORCED
CONTINUOUS
2A/DIV
VIN
5V/DIV
BURST
2A/DIV
VOUT = 5V
PULSESKIPPING
2A/DIV
VOUT = 3.3V
VOUT
2V/DIV
VIN = 12V
VOUT = 3.3V
ILOAD = 200µA
10
0 25 50 75 100 125 150
TEMPERATURE (°C)
3372 G18
Load Step Burst Mode Operation
100µs/DIV
FALLING
3.85
3.75
3372 G17
VOUT
AC–COUPLED
100mV/DIV
RISING
4.05
3.80
1.125
0 25 50 75 100 125 150
TEMPERATURE (°C)
4.15
INTVCC VOLTAGE (V)
12.0
Shutdown (RUN) Threshold
vs Temperature
5µs/DIV
3372 G23
2ms/DIV
3372 G24
Rev. A
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LTC3372
TYPICAL PERFORMANCE CHARACTERISTICS
(LV Buck Regulator) TA = 25°C, unless otherwise noted.
2A Buck Efficiency and Power
Loss vs Output Current
10000
BURST EFFICIENCY
90
1000
100
50
FCM LOSS
40
30
10
BURST LOSS
EFFICIENCY (%)
FCM EFFICIENCY
60
1
20
VIN = 3.3V
VOUT = 1.8V
10
0
0.0001
0.001
0.01
0.1
OUTPUT CURRENT (A)
1 2
70
ILOAD = 100mA
60
50
40
30 VOUT = 1.8V
fSW = 2MHz
20
0
ILOAD = 10mA
2
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
3372 G25
2A Buck Efficiency
vs VOUT Forced Continuous Mode
EFFICIENCY (%)
100
ILOAD = 1A
95
80
60
50
ILOAD = 10mA
40
30
20
ILOAD = 1mA
10
VIN = 3.3V
fSW = 2MHz
2A Buck Efficiency
vs VOUT Burst Mode Operation
85
80
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 10mA
ILOAD = 1A
30
20
10
0
0.0001
FCM
VIN = 3.3V
VOUT = 1.8V
fSW = 1MHz
fSW = 2MHz
fSW = 3MHz
0.001
0.01
0.1
OUTPUT CURRENT (A)
1 2
40
30
10
VIN = 3.3V
VOUT = 1.8V
fSW = 2MHz
0
0.0001
0.001
0.01
0.1
OUTPUT CURRENT (V)
1.800
VIN = 3.3V
VOUT = 1.8V
1.790
800
798
796
4
1A Buck Load Regulation Across
VIN Forced Continuous Mode
VOUT = 1.8V
1.770
1.760
1.750
1.740
1.730
1.720
794
1.710
0 25 50 75 100 125 150
TEMPERATURE (°C)
3372 G32
3372 G31
1
1.780
802
792
–75 –50 –25
1A Buck
2A Buck
3A Buck
4A Buck
3372 G30
OUTPUT VOLTAGE (V)
40
50
2A Buck Regulator Feedback
Voltage vs Temperature
804
5.5
60
3372 G29
REGULATED FEEDBACK VOLTAGE (mV)
EFFICIENCY (%)
50
5
70
20
806
60
3
3.5
4
4.5
INPUT VOLTAGE (V)
80
70
0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
OUTPUT VOLTAGE (V)
100
70
2.5
100
90
2A Buck Efficiency vs Output Current
Across Switching Frequency
BURST MODE
2
90
3372 G28
80
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 1A
Efficiency vs Output Current
Burst Mode Operation
VIN = 3.3V
fSW = 2MHz
75
0
0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
OUTPUT VOLTAGE (V)
90
80
3372 G27
ILOAD = 100mA
70
85
70
5.5
EFFICIENCY (%)
90
90
3372 G26
EFFICIENCY (%)
100
VOUT = 1.8V
fSW = 2MHz
75
ILOAD = 1mA
10
0.1
2A Buck Efficiency
vs VIN Burst Mode
95
80
POWER LOSS (mW)
70
100
ILOAD = 1A
90
80
EFFICIENCY (%)
100
EFFICIENCY (%)
100
2A Buck Efficiency
vs VIN Forced Continuous Mode
1.700
0.001
VIN = 2.25V
VIN = 3.3V
VIN = 5V
0.01
0.1
OUTPUT CURRENT (A)
1
3372 G33
Rev. A
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11
LTC3372
TYPICAL PERFORMANCE CHARACTERISTICS
(LV Buck Regulator) TA = 25°C, unless otherwise noted.
2A Buck Regulated Feedback
Voltage vs VINA-H
808
VOUT = 1.8V
REGULATED FEEDBACK VOLTAGE (mV)
1.820
OUTPUT VOLTAGE (V)
1.800
1.780
1.760
1.740
1.720
1.700
0.001
VIN = 2.25V
VIN = 3.3V
VIN = 5V
0.01
0.1
OUTPUT CURRENT (A)
1
804
VFB1
798
ILOAD = 10mA
ILOAD = 1A
794
2
2.5
2.10
VIN = 3.3V
2.08
2.06
2.04
2.5
2.0
1.5
Default Oscillator Frequency
vs Temperature
1400
VINA–H = 3.3V
2.06
1.90
–75 –50 –25
Enable Threshold vs Temperature
900
VIN = 3.3V
800
800
600
400
–200
0 25 50 75 100 125 150
TEMPERATURE (°C)
3372 G39
EN THRESHOLD (mV)
VTEMP (mV)
0 25 50 75 100 125 150
TEMPERATURE (°C)
3372 G40
12
1.90
–75 –50 –25
VTEMP vs Temperature
700
600
RISING
500
400
FALLING
300
0
1.92
1.98
1.92
200
1.94
2.00
1.94
1000
2.04
1.96
2.02
1.96
1200
1.98
RT = 402kΩ
VINA–H = 3.3V
3372 G38
3372 G37
2.00
0 25 50 75 100 125 150
TEMPERATURE (°C)
RT Programmed Oscillator
Frequency vs Temperature
0
250 300 350 400 450 500 550 600 650 700 750 800
RT (kΩ)
0 25 50 75 100 125 150
TEMPERATURE (°C)
2.02
VIN = 3.3V
VIN = 5V
3372 G36
0.5
NMOS
100
–75 –50 –25
FSW (MHz)
1.50
–75 –50 –25
5.5
1.0
150
2.08
5
FSW (MHz)
FSW (MHz)
PMOS RESISTANCE (mΩ)
4.0
200
2.10
3
3.5
4
4.5
INPUT VOLTAGE (V)
3.0
250
1.65
1.55
Oscillator Frequency vs RT
3.5
300
1.70
3372 G35
PMOS
350
1.75
1.60
796
VIN = 5V
VIN = 3.3V
VIN = 2.25V
400
1.80
800
1A Buck NMOS and PMOS RDS(ON)
vs Temperature Across VIN
450
1.85
802
3372 G34
500
1.90
FORCED CONTINUOUS MODE
VIN = 3.3V
VFB2
VOUT = 1.8V
806
792
4
1A Buck PMOS Current Limit
vs Temperature
CURRENT LIMIT (A)
4A Buck Output Voltage
vs Output Current
0
25
50
75
100
TEMPERATURE (°C)
125
150
3372 G41
200
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3372 G42
Rev. A
For more information www.analog.com
LTC3372
TYPICAL PERFORMANCE CHARACTERISTICS
(LV Buck Regulator) TA = 25°C, unless otherwise noted.
Precise Enable Threshold
vs Temperature
420
410
UVLO THRESHOLD (V)
390
380
370
360
350
FALLING
2.20
IIND
1A/DIV
RISING
2.15
2.10
VOUT
AC–COUPLED
50mV/DIV
2.05
FALLING
2.00
100µs/DIV
VIN = 3.3V
VOUT = 1.8V
ILOAD = 100mA to 1.6A
1.95
330
320
–75 –50 –25
ILOAD
1A/DIV
2.25
RISING
340
2A Buck Load Step Burst Mode
2.30
VIN = 3.3V
400
EN THRESHOLD (mV)
VINA-H UVLO Threshold
vs Temperature
0 25 50 75 100 125 150
TEMPERATURE (°C)
1.90
–75 –50 –25
3372 G43
0 25 50 75 100 125 150
TEMPERATURE (°C)
3372 G45
3372 G44
2A Buck Load Step Forced
Continuous Mode
2A Buck Start-Up
ILOAD
1A/DIV
VIN
1V/DIV
IIND
1A/DIV
VOUT
AC–COUPLED
50mA/DIV
VOUT
1V/DIV
100µs/DIV
VIN = 3.3V
VOUT = 1.8V
ILOAD = 100mA to 1.6A
3372 G46
VIN = 3.3V
VOUT = 1.8V
2ms/DIV
3372 G47
Rev. A
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13
LTC3372
PIN FUNCTIONS
RST (Pin 1): LV Regulator Reset Logic Output. This pin is
pulled low when the feedback pin (FB1-4) voltage of any
enabled LV regulator is outside of its power good window.
The window is –2% to +7.5% (typical) for regulator 1,
and –5% to +7.5% (typical) for regulators 2-4, around
the regulated 0.8V level. This pin is pulled low when all
LV regulators are disabled. Assertion (the pin goes high)
delay is scaled by the CT capacitor.
TEMP (Pin 2): Temperature Indication Pin. TEMP outputs
a voltage of 220mV (typical) at 25°C. The TEMP voltage
will increase by 7mV/°C (typical) at higher temperatures
giving an external indication of the IC’s internal die temperature. The temperature monitor can be shut down by
tying the TEMP pin to INTVCC to reduce quiescent current.
If all LV regulators are disabled, the temperature monitor
shuts down and the TEMP pin becomes high impedance.
EN1 (Pin 3): LV Buck Regulator 1 Enable Input. Active
high. Do not float.
FB1 (Pin 4): LV Buck Regulator 1 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
VINA (Pin 5): LV Power Stage A Input Supply. Bypass to
GND with a 10µF or larger ceramic capacitor.
SWA (Pin 6): LV Power Stage A Switch Node. External
inductor connects to this pin.
SWB (Pin 7): LV Power Stage B Switch Node. External
inductor connects to this pin.
VINB (Pin 8): LV Power Stage B Input Supply. Bypass to
GND with a 10µF or larger ceramic capacitor.
VINC (Pin 9): LV Power Stage C Input Supply. Bypass to
GND with a 10µF or larger ceramic capacitor.
SWC (Pin 10): LV Power Stage C Switch Node. External
inductor connects to this pin.
SWD (Pin 11): LV Power Stage D Switch Node. External
inductor connects to this pin.
VIND (Pin 12): LV Power Stage D Input Supply. Bypass to
GND with a 10µF or larger ceramic capacitor.
14
FB2 (Pin 13): LV Buck Regulator 2 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
In configurations where LV Regulator 2 is not used, FB2
should be tied to ground.
EN2 (Pin 14): LV Buck Regulator 2 Enable Input. Active
high. In configurations where LV Regulator 2 is not used,
tie EN2 to ground. Do not float.
C1 (Pin 15): LV Regulator Configuration Control Input Bit.
With C2 and C3, C1 configures the buck output current
power stage combinations. C1 should either be tied to
INTVCC or ground. Do not float.
C2 (Pin 16): LV Regulator Configuration Control Input Bit.
With C1 and C3, C2 configures the buck output current
power stage combinations. C2 should either be tied to
INTVCC or ground. Do not float.
C3 (Pin 17): LV Regulator Configuration Control Input Bit.
With C1 and C2, C3 configures the buck output control
power stage combinations. C3 should either be tied to
INTVCC or ground. Do not float.
RT (Pin 18): Oscillator Frequency Pin. This pin provides
two modes of setting the switching frequency. Connecting a
resistor from RT to ground will set the switching frequency
based on the resistor value. If RT is tied to INTVCC the
internal 2MHz oscillator will be used. Do not float.
PLL/MODE (Pin 19): Oscillator Synchronization Input and
Mode Select Pin. Driving this pin with an external clock
signal synchronizes the internal oscillator to the applied
clock. The LV bucks synchronize to the oscillator frequency
and HV buck synchronizes to 1/6th frequency when in
forced continuous mode. When no external clock is applied the oscillator frequency is programmed by the RT
pin. When not synchronizing to an external clock this input
determines how the controller and regulators operate at
light load. Floating or grounding this pin selects Burst Mode
operation, and tying this pin to INTVCC forces continuous
inductor current mode operation for all the converters and
the controller. Tying this pin to a voltage greater than 1.2V
and less than INTVCC–1.3V selects pulse-skipping mode
operation for the controller, but Burst Mode operation for
the low voltage converters. This pin has a 100k internal
resistor to ground.
Rev. A
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LTC3372
PIN FUNCTIONS
WDI (Pin 20): Watchdog Timer Input. The WDI pin must
be toggled either low to high or high to low every 1.62
seconds. Failure to toggle WDI results in the WDO pin
being pulled low for 202ms. All times correspond to a
10nF capacitor on the CT pin.
WDO (Pin 21): Watchdog Timer. Open-drain output. WDO
is pulled low for 202ms during a watchdog timeout period.
The WDO pin pulls low if the WDI input does not transition
in less than 1.62 seconds since its last transition or 12.9
seconds after a watchdog timeout period. An UVLO event
resets the watchdog timer and WDO asserts itself low for
the 202ms watchdog timeout period. All times correspond
to a 10nF capacitor on the CT pin.
CT (Pin 22): Timing Capacitor Pin. A capacitor connected
to GND sets a time constant which is scaled for use by
the WDI, WDO, and RST pins. Tying the CT pin to INTVCC
disables the watchdog timer to reduce quiescent current.
EN3 (Pin 23): LV Buck Regulator 3 Enable Input. Active
high. In configurations where LV Regulator 3 is not used,
tie EN3 to ground. Do not float.
FB3 (Pin 24): LV Buck Regulator 3 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
In configurations where LV Regulator 3 is not used, FB3
should be tied to ground.
VINE (Pin 25): LV Power Stage E Input Supply. Bypass to
GND with a 10μF or larger ceramic capacitor.
SWE (Pin 26): LV Power Stage E Switch Node. External
inductor connects to this pin.
SWF (Pin 27): LV Power Stage F Switch Node. External
inductor connects to this pin.
VINH (Pin 32): LV Power Stage H Input Supply. Bypass to
GND with a 10μF or larger ceramic capacitor.
FB4 (Pin 33): LV Buck Regulator 4 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
EN4 (Pin 34): LV Buck Regulator 4 Enable Input. Active
high. Do not float.
INTVCC (Pin 35): Internal VCC Pin. Output of an internal
linear low-dropout (LDO) regulator powered from VIN. The
HV buck gate drive and control circuits are powered from
this voltage source when VOUT is < 4.7V. When VOUT >
4.7V the bias connects to Vout and the LDO is shutdown.
Must be de-coupled to GND pin with a minimum of 4.7μF
low ESR (ceramic) capacitor.
BG (Pin 36): HV Controller High Current Gate Drive for
Bottom (Synchronous) N-channel MOSFET. Voltage swing
at this pin is from ground to INTVCC.
TG (Pin 37): HV Controller High Current Gate Drive for Top
N-channel MOSFET. This is the output of floating driver
with a voltage swing equal to INTVCC superimposed on
the switch node voltage SW.
SW (Pin 38): HV Controller Switch Node Connection to
Inductor.
BOOST (Pin 39): HV Controller Bootstrapped Supply to the
Topside Floating Driver. A capacitor should be connected
between the BOOST and SW pin and a Schottky diode
should be connected between the BOOST and INTVCC
pins. Voltage swing at the BOOST pin is from INTVCC to
(VIN + INTVCC).
VINF (Pin 28): LV Power Stage F Input Supply. Bypass to
GND with a 10μF or larger ceramic capacitor.
RUN (Pin 40): HV Controller Enable Input. Forcing this
pin above 1.2V turns on the HV controller. This pin has a
0.5µA internal pull-up current from ground to around 4V,
and can be forced up to 65V (absolute maximum).
VING (Pin 29): LV Power Stage G Input Supply. Bypass to
GND with a 10μF or larger ceramic capacitor.
VIN (Pin 41): HV Input Supply Pin. A bypass capacitor
should be tied between this pin and the GND pin.
SWG (Pin 30): LV Power Stage G Switch Node. External
inductor connects to this pin.
TRACK/SS (Pin 42): HV Controller External Tracking and
Soft-Start Input. When this pin is above 1.2V, the controller
regulates the output voltage VOUT to the programed 5V or
3.3V level. When this pin is below 1.2V, the output voltage
SWH (Pin 31): LV Power Stage H Switch Node. External
inductor connects to this pin.
Rev. A
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15
LTC3372
PIN FUNCTIONS
is regulated proportionally lower. An internal 10μA pullup current source is connected to this pin. A capacitor to
ground at this pin sets the ramp time to the final regulated
output voltage. Alternatively, a resistor divider on another
voltage supply connected to this pin allows the controller’s
output to track another supply during start-up.
SENSE+ (Pin 45): HV Controller Positive (+) Input to
Differential Current Comparator. The ITH pin voltage and
controlled offsets between the SENSE– and SENSE+ pins
set the current trip threshold. The current comparator
can be used for either inductor DCR sensing or traditional
current sensing resistor (RSENSE) sensing.
VOUT/EXTVCC (Pin 43): HV Controller Output Voltage
Sensing and External VCC Power Input. Connect this pin
to the HV controller’s regulated output voltage. The HV
controller VOUT is regulated to either 3.3V or 5V by an
internal resistor divider selected by the VPROG pin. This
pin is also provides an external VCC connection and supplies internal bias voltages from VOUT to improve low IQ
performance and reduce power loss.
ITH (Pin 46): HV Controller Error Amplifier Output and
Compensation Point. The current comparator threshold
increases with this control voltage.
SENSE– (Pin 44): HV Controller Negative (–) Input to
Differential Current Comparator. This SENSE– pin also
functions as the output voltage sense pin for a secondary
15% overvoltage protection in addition to the 7.5% overvoltage protection at the VOUT/EXTVCC pin. In the situation
that SENSE– pin is separated from VOUT/EXTVCC pin to
achieve point-of-load (POL) regulation, SENSE– can begin
drawing a >500µA current when SENSE– is 200mV greater
than VOUT (VOUT = 5V) or INTVCC (VOUT = 3.3V). When
voltage on SENSE– pin is close to INTVCC, SENSE– can
begin drawing >500µA current. Do not connect a filtering
resistor in series with SENSE– pin unless SENSE– stays
close to ground in the application.
16
VOUTPRG (Pin 47): HV Controller Output Voltage Programming Pin. When this pin is tied to INTVCC, the output voltage is regulated to 5V. When tied to ground, the output
voltage is regulated to 3.3V.
PGOOD (Pin 48): HV Controller Power Good Open-Drain
Logic Output. This pin is pulled low when the voltage at the
VOUT/EXTVCC pin is outside of the ±7.5% window around
the regulated level, or voltage at SENSE– pin is more than
15% above the regulated level of VOUT.
GND (Exposed Pad Pin 49): Ground. The exposed pad
must be soldered to a continuous printed circuit board
ground plane directly under the IC package for rated thermal performance. The exposed pad is a shared ground for
signal grounds, driver ground and power stage grounds
of all HV and LV buck regulators.
Rev. A
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LTC3372
BLOCK DIAGRAM
VIN
INTVCC
DB
OV
BOOST
1.29V
+
PGOOD
–
VFB
+
UV
CB
DROP
OUT
DET
LTC3372: CLK/6 (1/6 fOSC)
1.11V
S
Q
R
Q
TG
CIN
BOT
TOP ON
SW
SWITCH
LOGIC
–
SHDN
VOUT
INTVCC
COUT
BG
MODE
0.5µA
OV
RUN
0.425V
+
SLEEP
–
+ IREV
–
ICMP
–+
+–
+
2mV
2.7V
0.65V
15% ABOVE
REGULATION
SENSE+
SENSE–
SLOPE COMP
+
–
VOUT /EXTVCC
+
VIN
–
EA
VFB
1.2V
TRACK/SS
VOUT/EXTVCC
3.3V/5V
PROGRAM
–
VOUTPRG
GATE
CONTROL
5.1V
LDO
EN
EN
SHDN
RST
2(VFB)
+
4.7V
CC
ITH
–
FOLDBACK
10µA
CC2
RC
TRACK/SS
CSS
SHDN
INTVCC
HIGH VOLTAGE CONTROLLER
RT
PLL/MODE
4
CLK (fOSC)
OSCILLATOR
CT
MODE
BANDGAP OT
REF
UVLO
UV
CT
OSCILLATOR
WDI
TEMP
MONITOR
WDO
TEMP
2
SD
WATCHDOG TIMER
STATE MACHINE
CT
CLOCK
LOW VOLTAGE REGULATORS
VINA
RST
4 PGOOD
DELAY
1A POWER
STAGE A
SWA
1A POWER
STAGE B
SWB
1A POWER
STAGE C
SWC
1A POWER
STAGE D
SWD
1A POWER
STAGE E
SWE
1A POWER
STAGE F
SWF
1A POWER
STAGE G
SWG
1A POWER
STAGE H
SWH
VINB
SD
REF
CLK
MODE
4
VINC
VINB
EN1
FB1
VIND
BUCK REGULATOR 1
CONTROL
VIND
EN2
FB2
VINE
BUCK REGULATOR 2
CONTROL
VINE
EN3
FB3
VINF
BUCK REGULATOR 3
CONTROL
VING
VING
EN4
FB4
BUCK REGULATOR 4
CONTROL
CONFIGURATION LINES
C1
C2
C3
VINH
GND
(EXPOSED PAD)
33721 BD
Rev. A
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17
LTC3372
OPERATION
The LTC3372 is a single IC that combines a high voltage
(HV) buck (step-down) DC/DC switching regulator controller and a total of four configurable low voltage (LV)
buck regulators.
Main Control Loop of HV Buck Controller
The HV controller uses a constant frequency, current mode
buck (step-down) architecture. During normal operation,
the external top MOSFET is turned on when the clock sets
the RS latch, and is turned off when the main current
comparator, ICMP, resets the RS latch. The peak inductor
current at which ICMP trips and resets the latch is controlled by the voltage on the ITH pin, which is the output
of the error amplifier, EA. The error amplifier compares
an internal 1.2V reference voltage to the feedback voltage
generated by an internal resistor divider connected to the
VOUT/EXTVCC pin. The divider can be selected to program
an output of either 3.3V to 5V. When the load current
increases, it causes a slight decrease in VFB relative to
the reference, which causes the EA to increase the ITH
voltage until the average inductor current matches the
new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the beginning of the next
clock cycle, or the inductor current starts to reverse, as
indicated by the reverse current comparator IREV (at light
load in pulse-skipping mode or Burst Mode).
INTVCC Power
Power for the top and bottom MOSFET drivers and some
other internal circuitry is derived from the INTVCC pin. When
the VOUT/EXTVCC pin is tied to a voltage less than 4.7V,
the VIN LDO (low dropout linear regulator) supplies 5.1V
from VIN to INTVCC. If VOUT/EXTVCC is taken above 4.7V,
the VIN LDO is turned off and an internal PMOS switch
connects VOUT/EXTVCC to INTVCC. Using the VOUT/EXTVCC
pin allows the INTVCC power to be derived from the high
efficiency HV buck regulator output.
The top MOSFET driver is biased from the floating bootstrap
capacitor, CB, which normally recharges during each cycle
through an external diode, DB, when the top MOSFET turns
off. If the input voltage, VIN, decreases to a voltage close
18
to VOUT, the loop may enter dropout and attempt to turn
on the top MOSFET continuously. The dropout detector
detects this and forces the top MOSFET off for a short
time every tenth cycle to allow CB to recharge, resulting
in an effective duty cycle of 98%.
Shutdown and Start-Up (RUN, TRACK/SS Pins)
It typically takes 1.2ms for the internal bias circuits (including INTVCC) to be ready after the first time either the RUN
pin or any of the EN1-4 pins rises above 730mV. During
the 1ms internal bias circuit startup time, neither the HV
or LV regulators are enabled. The HV controller is enabled
when the RUN pin is pulled above 1.2V and the internal
bias is enabled. Pulling RUN pin below 1.16V disables
the HV controller.
The RUN pin has an internal 0.5μA current that pulls up
the pin to enable the HV controller. Alternatively, the RUN
pin may be externally pulled up or driven by logic. The
RUN pin can tolerate up to 65V (absolute maximum), so
it can be conveniently tied to VIN in an always-on application in which the controller is enabled continuously and
never shut down.
The RUN pin can also be used as an undervoltage lockout
(UVLO) by connecting it to the midpoint of an external resistor divider network of VIN (see Applications Information
section).
The start-up of the controller’s output voltage VOUT is
controlled by the voltage on the TRACK/SS pin. When the
voltage on the TRACK/SS pin is less than the 1.2V internal
reference, the HV controller regulates the VFB voltage to the
TRACK/SS pin voltage instead of the 1.2V reference. This
allows the TRACK/SS pin to be used to program a soft-start
by connecting an external capacitor from the TRACK/SS
pin to GND. An internal 10μA pull-up current charges this
capacitor creating a voltage ramp on the TRACK/SS pin. As
the TRACK/SS voltage rises linearly from 0V to 1.2V and
beyond, the output voltage VOUT rises smoothly from zero
to its final value. Alternatively the TRACK/SS pin can be
used to cause the start-up of VOUT to track that of another
supply. Typically, this requires connecting to the TRACK/
SS pin an external resistor divider from the other supply
to ground (see the Applications Information section).
Rev. A
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LTC3372
OPERATION
Output Overvoltage Protection
Overvoltage comparators guard against transient overshoots as well as other more serious conditions that may
overvoltage the output.
When the VOUT/EXTVCC pin voltage rises by more than
7.5% above its regulation set point, the top power MOSFET
gate (TG) is turned off and the bottom power MOSFET gate
(BG) is turned on until the overvoltage condition is cleared.
The SENSE– pin functions as the output voltage sense pin
for a secondary +15% overvoltage protection in addition
to the +7.5% overvoltage protection at VOUT/EXTVCC pin.
When voltage at this pin is over 15% higher than the
regulated output voltage set point, the HV controller will
turn TG off and BG on. This provides an additional layer of
protection when point-of-load (POL) regulation is desired.
Power Good Indicator (PGOOD) Pin
The PGOOD pin is connected to the open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the VOUT/EXTVCC voltage
is outside of the ±7.5% window around the regulated
level. The PGOOD pin is also pulled low when the RUN
pin is low (shut down). When the VOUT/EXTVCC voltage is
within the ±7.5% window, the MOSFET is turned off and
the pin is allowed to be pulled up by an external resistor
to a source no greater than 6V.
Foldback Current Limit
When the output voltage falls to less than 70% of its nominal
level, foldback current limiting is activated. Foldback progressively lowers the peak current limit as the output drops in a
sustained overcurrent or short-circuit condition. Foldback current limiting is disabled during the soft-start interval (as long
as the VFB voltage is keeping up with the TRACK/SS voltage).
Light Load Current Operation
The HV buck controller can be enabled to enter one of
the three modes at light load current: (a) high efficiency
Burst Mode, (b) forced continuous conduction mode, or
(c) pulse-skipping mode operations at light load currents.
The LTC3372’s PLL/MODE pin selects the light load
operation modes for both the HV controller and LV
buck regulators. To select Burst Mode operation, tie the
PLL/MODE pin to SGND. To select forced continuous
mode operation, tie the PLL/MODE pin to INTVCC. When
PLL/MODE pin is connected to an external clock, both HV
controller and the LV buck regulators are synchronized to
the external clock in forced continuous mode operation.
To select pulse-skipping mode for the HV controller, tie the
PLL/MODE pin to a DC voltage greater than 1.2V but less
than INTVCC – 3.3V. The LV buck regulators will operate
in Burst Mode operation.
When the controller is enabled for Burst Mode operation, the
minimum peak current in the inductor is set to approximately
25% of the maximum sense voltage even though the voltage
on the ITH pin indicates a lower value. If the average inductor
current is higher than the load current, the error amplifier,
EA, will decrease the voltage on the ITH pin. When the ITH
voltage drops below 0.425V, the internal sleep signal goes
high (enabling sleep mode) and both external MOSFETs are
turned off. The ITH pin is then disconnected from the output
of the EA and parked at 0.450V.
In sleep, much of the internal circuitry is turned off, reducing the quiescent currents that the controllers draws.
The load current is supplied by the output capacitor. As
the output voltage decreases, the EA’s output begins to
rise. When the output voltage drops enough, the ITH pin
is reconnected to the output of the EA, the sleep signal
goes low, and the controller resumes normal operation
by turning on the top external MOSFET on the next cycle
of the internal oscillator.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator, IREV, turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus, the
controller operates in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than in
Rev. A
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19
LTC3372
OPERATION
Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interference to other circuitry. In forced continuous mode,
the output ripple is independent of load current. Clocking the LTC3372 from an external source enables forced
continuous mode (see the Programming the Operating
Frequency section.)
When the PLL/MODE pin is connected for pulse-skipping
mode, the HV controller operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads,
the current comparator, ICMP, may remain tripped for
several cycles and force the external top MOSFET to stay
off for the same number of cycles (i.e., skipping pulses).
The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous
operation, exhibits low output ripple as well as low noise
and reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
It typically takes 1ms for the internal bias circuits (including INTVCC) to be ready after the first time RUN or
any EN pin rises above 0.73V. All regulators are disabled
during internal circuit start-up time. When a LV regulator
is enabled there is an additional 150μs delay before the
soft start ramp begins. All LV regulators have soft start
and forward and reverse current limiting to control inrush
current during start-up and to provide short-circuit protection in normal operation.
The LV buck switching regulators are phased in 90° steps
to reduce noise and input ripple. The phase step determines
the fixed edge of the switching sequence, which is when
the PMOS turns on. The PMOS off (NMOS on) phase is
subject to the duty cycle demanded by the regulator. Buck
1 is set to 0°, Buck 2 is set to 90°, Buck 3 is set to 270°,
and Buck 4 is set to 180°. In shutdown all SW nodes are
high impedance. The buck regulator enable pins may be
tied to VOUT voltages through a resistor divider, to program
power-up sequencing.
LV Buck Regulators with Combined Power Stages
LOW VOLTAGE REGULATORS
Low Voltage Buck Switching Regulator
The LTC3372 contains eight low voltage (LV) monolithic
1A synchronous buck switching power stages. Each power
stage contains an integrated PMOS top-side switch and
a NMOS bottom-side switch. The eight power stages are
controlled by up to four constant frequency peak current
mode controllers. All of the switching regulators are
internally compensated and need only external feedback
resistors to set their output voltages.
Each LV buck switching regulator can operate with an
independent input voltage and has its own FB and EN
pins to maximize flexibility. The enable pins have two
different enable thresholds that depend on the operating
state of the other LV regulators. When all of the LV regulators are disabled, the EN pin threshold is 0.73V . Once
any LV regulator is enabled, the EN pin thresholds of the
remaining LV regulators are set to a precision internalreference-based 400mV. This precision EN threshold may
20
be used to provide event based sequencing via feedback
from other previously enabled regulators.
Up to four adjacent LV buck regulators may be combined
in a master-slave configuration by setting the configuration
via the C1, C2, and C3 pins. These pins should either be
tied to ground or pin strapped to INTVCC in accordance with
the desired configuration code (Table 1). Any combined
SW pins must be tied together, as must any of the combined VIN pins. EN1 and FB1 are utilized by Buck 1, EN2
and FB2 by Buck 2, EN3 and FB3 by Buck 3, and EN4 and
FB4 by Buck 4. If any buck is not used or is not available
in the desired configuration, then the associated FB and
EN pins must be tied to ground.
Any available combination of 2, 3, or 4 adjacent buck
regulators serves to provide up to either 2A, 3A, or 4A
of average output load current. For example, code 110
(C3C2C1) configures Buck 1 to operate as a 4A regulator
through VINA-H /SWA-H pairs A, B, C, and D, while Buck
2 is disabled, Buck 3 operates as a 1A regulator through
VINA-H /SWA-H pair E, and Buck 4 operates as a 3A regulator through VINA-H /SWA-H pairs F, G, and H.
Rev. A
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LTC3372
OPERATION
Table 1. Master Slave Program Combinations (Each Letter
Corresponds to a Low Voltage Power Stage)
PROGRAM
CODE
C3C2C1
BUCK 1
BUCK 2
BUCK 3
BUCK 4
000
AB
CD
EF
GH
001
ABC
D
EF
GH
010
ABC
D
E
FGH
011
ABCH
D
E
FG
100
ABC
DE
Not Used
FGH
101
ABCD
Not Used
EF
GH
110
ABCD
Not Used
E
FGH
111
ABCD
Not Used
Not Used
EFGH
Power Failure Reporting via RST Pin
Power failure conditions of all LV buck regulators are
reported by the single RST pin. Each LV regulator has an
internal power good signal. If LV Buck 1 output voltage
falls below 98%, or any of the Buck 2-4 outputs falls below
95%, of its programmed value, or if any LV regulator’s
output rises above 107.5% of its programmed value, its
internal power good signal is pulled low. If any internal
power good signal stays low for greater than 100μs, then
the RST pin is pulled low. The RST low signal indicates to
a microprocessor that a power failure fault has occurred.
The 100μs filter time prevents a false fault indication low
due to a output/load transient.
The internal power good comparators have hysteresis, so
the regulated output voltage of an enabled regulator has
to move back into the power good window by more than
the hysteresis for its power good signal to transition high.
Once all enabled LV regulator outputs are power good for
202ms (typical, CT = 10nF), the RST output goes high
impedance (pulled high by external resistor/current). If
all LV buck regulators are disabled, RST pulls low.
Temperature Monitoring and Overtemperature
Protection
To prevent thermal damage to the IC and its surrounding
components, the LV regulators have an overtemperature
(OT) function. When the LTC3372 die temperature reaches
170°C (typical) all LV buck switching regulators are shut
down and remain in shutdown until the die temperature
falls to 160°C (typical).
The temperature may be read back by the user by sampling
the TEMP pin analog voltage. The temperature, T, indicated
by the TEMP pin voltage is given by:
V
− 45mV
T = TEMP
• 1°C
7mV
To reduce quiescent current (IQ), if all the LV buck regulators are shut down, the temperature monitor also shuts
down and the TEMP pin becomes high impedance. The
temperature monitor can be disabled by tying the TEMP
pin to INTVCC to save IQ.
Programming the Operating Frequency
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output voltage ripple.
The frequency of the internal oscillator (system clock)
is determined by an external resistor that is connected
between the RT pin and ground. The operating frequency
can be calculated using the following equation:
fOSC =
8 • 10 11 • ΩHz
RT
The oscillator is designed to function with operating frequencies between 1MHz and 3MHz, it has safety clamps
that prevent the oscillator from running faster than 4MHz
(typical) or slower than 250kHz (typical). Tying the RT pin
to INTVCC sets the oscillator to the default internal operating frequency of 2MHz (typical).
The internal oscillator can be synchronized through an
internal PLL circuit to an external frequency by applying
a square wave clock signal to the PLL/MODE pin. During
synchronization, the top MOSFET turn-on of LV buck regulator 1 is phase-locked to the rising edge of the external
frequency source. All other LV regulators are locked to
the appropriate phase of the external frequency source.
Rev. A
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21
LTC3372
OPERATION
The synchronization frequency range is 1MHz to 3MHz.
A synchronization signal on the PLL/MODE pin will force
all low voltage (LV) active buck switching regulators to
operate in forced continuous mode PWM.
The LV regulators switch directly off the internal oscillator
in 90-degree phase increments. The LTC3372 HV controller switches at one-sixth (1/6) of the internal oscillator
frequency with a range of between 166kHz to 500kHz.
Windowed Watchdog Timer
A standard watchdog function is used to ensure that the
system is in a valid state by continuously monitoring the
microprocessor’s activity. The microprocessor must toggle
the logic state of the WDI pin periodically in order to clear
the watchdog timer. The WDI pin reset is read only on a
WDI falling edge, such that a single reset signal may be
asserted by pulsing the WDI pin for a time greater than
the minimum pulse width. If timeout occurs, a WDO low
is asserted for the reset timeout period, issuing a system
reset. Once the reset timeout completes, WDO is released
to go high and the watchdog timer starts again.
During power-up, the watchdog timer initiates in the
timeout state with WDO asserted low. As soon as the
reset timer times out, WDO goes high and the watchdog
timer is started.
A windowed watchdog function is implemented by adding a lower boundary condition to the standard watchdog
function. If the WDI input receives a falling edge prior to
the watchdog lower boundary, the part considers this a
watchdog failure, and asserts WDO low (releasing again
after the reset timeout period as described above). This will
again be followed by another lower boundary time period.
The watchdog timer shuts down when RUN and EN1-4
are off (all HV and LV regulators are shut down). Tying the
CT pin to INTVCC disables the watchdog timer regardless
of the RUN and EN1-4 pins (HV and LV regulators either
on or off).
Choosing the CT Capacitor
The watchdog timeout period is adjustable and can be
optimized for software execution. The watchdog timeout
period is adjusted by connecting a capacitor between CT
and ground. Given a specified watchdog timeout period,
the capacitor is determined by:
CT = tWDO • 49.39 [nF/s]
For example, using a standard capacitor value of 10nF
gives a 202ms watchdog timeout period. Further, the other
watchdog timing periods scale with tWDO. The watchdog
lower boundary time (tWDL) scales as precisely 1/4 of
tWDO, the watchdog upper boundary time following the
previous WDI pulse scales as eight times that of tWDO, and
the watchdog upper boundary time following a watchdog
timeout scales as 64 times that of tWDO. Finally the RST
assertion delay will scale to the same time as tWDO.
These timing periods are illustrated in Figure 1. Each WDO
low period is equal to the time period t2-t1 (202ms for a
10nF CT capacitor, typical). If a WDI falling edge occurs
before the watchdog lower boundary, indicated by t3-t2
(50.6ms for a 10nF CT capacitor, typical), then another
watchdog timeout period occurs. If a WDI falling edge
occurs after the watchdog lower boundary (t4), then the
watchdog counter resets, beginning with another watchdog lower boundary period. In the case where a WDI low
transition is not detected by the specified time another
watchdog timeout period is initiated. This time is indicated
by t5-t4 (1.62s for a 10nF CT capacitor, typical). If a WDI
low transition is not detected within the specified time following a watchdog timeout period, then another watchdog
timeout period is initiated. This time is indicated by t7-t6
(12.9s for a 10nF CT capacitor, typical).
WDO
WDI
3372 F01
t1 t2 t3
t4
t5
t6
t7
Figure 1. WDO Timing Parameters
22
Rev. A
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LTC3372
APPLICATIONS INFORMATION
High Voltage Buck Controller
HIGH VOLTAGE BUCK CONTROLLER
The Typical Application on the first page is a basic application circuit. The HV controller inductor current sensing can
be configured to use either DCR (inductor resistance) or a
low value sense resistor. The choice between the two current sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
has become popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs. Finally, input and output capacitors are
selected.
programmed current limit unpredictable. If inductor DCR
sensing is used (Figure 3b), resistor R1 should be placed
close to the switching node, to prevent noise from coupling
into sensitive small-signal nodes.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
3372 F02
INDUCTOR OR RSENSE
Figure 2. Sense Lines Placement with Inductor or Sense Resistor
VIN
INTVCC
VIN
BOOST
TG
Current Sense Pins (SENSE+ and SENSE–)
RSENSE
SW
The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode voltage range on
these pins is 0V to 6V (abs max), allowing margin for
tolerances and transients for the HV regulator’s regulated
5V or 3.3V output.
The SENSE+ pin is high impedance over the full common
mode range, drawing at most ±1μA. This high impedance
allows the current comparators to be used in inductor
DCR sensing.
Connect the SENSE– pin directly to the sense point at the
VOUT side of the inductor (in DCR sensing) or the current
sense resistor (RSENSE), without adding any resistor in series. The impedance of the SENSE– pin changes depending
on its voltage. When SENSE– is less than INTVCC – 0.5V,
a small current of less than 1μA flows out of the pin. As
SENSE– approaches INTVCC, the current transitions higher
to close to 1mA.
Filter components mutual to the sense lines should be
placed close to the IC, and the sense lines should run
close together to a Kelvin connection underneath the
current sense element (shown in Figure 2). Sensing current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
COUT
LTC3372
VOUT
BG
SENSE+
SENSE–
R1*
C1* PLACE CAPACITOR NEAR
SENSE PINS
GND
3372 F03a
*R1 AND C1 ARE OPTIONAL
(3a) Using a Resistor to Sense Current
VIN
INTVCC
VIN
BOOST
INDUCTOR
TG
L
SW
LTC3372
DCR
VOUT
BG
R1
SENSE+
C1*
R2
SENSE–
GND
*PLACE C1 NEAR
SENSE PINS
(R1||R2) • C1 =
L
DCR
RSENSE(EQ) = DCR
R2
R1 + R2
3372 F03b
(3b) Using the Inductor DCR to Sense Current
Figure 3. Current Sensing Methods
Rev. A
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23
LTC3372
APPLICATIONS INFORMATION High Voltage Buck Controller
Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 3a. RSENSE is chosen based on the required
output current.
This LTC3372’s current comparator has a fixed maximum
current limit threshold of 75mV (typical). The current
comparator threshold voltage sets the peak of the inductor current, yielding a maximum average output current,
IMAX, equal to the peak value less half the peak-to-peak
ripple current, ∆IL. To calculate the sense resistor value,
use the equation:
R SENSE =
VSENSE(MAX)
IMAX +
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
ΔIL
2
R SENSE(EQUIV) =
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value (68mV) for the Maximum Current Sense
Threshold (VSENSE(MAX)) in the Electrical Characteristics
table.
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due
to the internal compensation required to meet stability
criterion for buck regulators operating at greater than
50% duty factor. The maximum current sense threshold
vs duty cycle curve is provided in the Typical Performance
Characteristics section to estimate this reduction in peak
inductor current depending upon the operating duty factor.
Inductor DCR Current Sensing
For applications requiring the highest possible efficiency at
high load currents, the LTC3372’s HV controller is capable
of sensing the voltage drop across the inductor DCR, as
shown in Figure 3b. The DCR of the inductor represents the
small amount of DC resistance of the copper wire, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such
an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
DCR sensing.
24
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
VSENSE(MAX)
IMAX +
ΔIL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value (68mV) for the Maximum Current Sense
Threshold (VSENSE(MAX)) in the Electrical Characteristics
table.
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio (RD):
RD =
R SENSE(EQUIV)
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1 || R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ±1μA current.
The equivalent resistance R1 || R2 is scaled to the room
temperature inductance and maximum DCR:
R1|| R2 =
L
(DCR at 20°C) • C1
Rev. A
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LTC3372
APPLICATIONS INFORMATION
High Voltage Buck Controller
The sense resistor values are:
R1=
R1|| R2
RD
; R2 =
R1• RD
1− RD
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
P LOSS R1=
(VIN(MAX) − VOUT ) • VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current, ∆IL, decreases with higher inductance or higher frequency and increases with higher VIN:
ΔIL =
⎛ V
⎞
VOUT ⎜ 1− OUT ⎟
VIN ⎠
(f)(L)
⎝
1
Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ∆IL = 0.3(IMAX). The maximum ∆IL occurs
at the maximum input voltage.
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for the
HV controller: one N-channel MOSFET for the top (main)
switch, and one N-channel MOSFET for the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC voltage.
This voltage is typically 5.1V during start-up (see VOUT Pin
Connection). Consequently, logic-level threshold MOSFETs
must be used in most applications. Pay close attention to
the BVDSS specification for the MOSFETs as well.
Selection criteria for the power MOSFETs include the onresistance, RDS(ON), Miller capacitance, CMILLER, input
Rev. A
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25
LTC3372
APPLICATIONS INFORMATION High Voltage Buck Controller
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
VOUT
VIN
Synchronous Switch Duty Cycle =
VIN − VOUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
⎛I
⎞
(VIN )2 ⎜ MAX ⎟ (RDR )(CMILLER ) •
⎝ 2 ⎠
⎡
1 ⎤
1
+
⎢
⎥(f)
⎣ VINTVCC − VTHMIN VTHMIN ⎦
V − VOUT
(IMAX )2 (1+ δ) RDS(ON)
PSYNC = IN
VIN
A Schottky diode can be placed in parallel with the bottom MOSFET to conduct during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on,
storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in
efficiency at high VIN. A 1A to 3A Schottky is generally a
good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
IGQ = f(QGT + QGB)
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
26
The term (1+ δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Another consideration is the losses due to the gate charge
of the MOSFETs. Each cycle, the bottom FET gate driver
draws a pulse of current from the INTVCC pin when turning
on the bottom FET gate. Another pulse of current is drawn
by the boost capacitor as the bottom FET turns on. This
energy is used by the floating high side driver to turn on
the top MOSFET. The INTVCC decoupling capacitor smooths
the current flowing through the LDO. The resulting DC
current can be estimated as:
V
PMAIN = OUT (IMAX )2 (1+ δ)RDS(ON) +
VIN
a short-circuit when the synchronous switch is on close
to 100% of the period.
The LDO losses will then become:
PLDO = (VIN – VINTVCC) • IGQ
To avoid the LDO losses, program VOUT for 5V with the
VOUTPRG pin. With this setting, the INTVCC LDO is shut
down and the INTVCC pin is tied to VOUT with an internal
switch. This will provide significant power loss reductions
for high input voltages.
The losses in the gate driver are also affected by the MOSFET
gate charge. A conservative estimate of the these losses is:
PGATE_DRIVE = IGQ • VINTVCC
Rev. A
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LTC3372
APPLICATIONS INFORMATION
High Voltage Buck Controller
CIN and COUT Selection
Setting Output Voltage (HV Controller)
The selection of CIN is usually based off the worst-case
RMS input current. The highest (VOUT)(IOUT) product needs
to be used in the formula to determine the maximum RMS
capacitor current requirement.
The HV controller output voltage is set by the VOUTPRG
pin through an internal resistor voltage divider. When
the VOUTPRG pin is tied to INTVCC, the output voltage is
regulated to 5V. When tied to ground, the output voltage
is regulated to 3.3V.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current must be used. The maximum RMS
capacitor current is given by:
I
1/2
CIN Required IRMS ≈ MAX [(VOUT )(VIN − VOUT )]
VIN
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do
not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature
than size or height requirements in the design. Due to the
high operating frequency, ceramic capacitors can also be
used for CIN. Always consult the manufacturer if there is
any question.
A small (0.1µF to 1µF) bypass capacitor between the
chip VIN pin and ground, placed close to the IC, is also
suggested. A small (
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