LTC3410BESC6-1.875

LTC3410B 2.25MHz, 300mA Synchronous Step-Down Regulator in SC70 U FEATURES DESCRIPTIO ■ The LTC ®3410B is a high efficiency monolithic synchronous buck regulator using a constant frequency, current mode architecture. The device is available in adjustable and fixed output voltage versions. Supply current during operation is only 200µA, dropping to 1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. 3410bfa 11 LTC3410B U W U U APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3410B. These items are also illustrated graphically in Figures 4 and 5. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1/R2 must be connected between the (+) plate of COUT and ground. 3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 4. Keep the (–) plates of CIN and COUT as close as possible. 5. Keep the switching node, SW, away from the sensitive VFB node. 1 1 RUN LTC3410B 2 – VFB GND 2 R2 3 + LTC3410B-1.875 6 COUT VOUT L1 VIN SW 5 RUN – R1 3 + CFWD 6 COUT VOUT 4 VOUT GND L1 CIN VIN SW 5 VIN 4 CIN VIN 3410B F04a BOLD LINES INDICATE HIGH CURRENT PATHS BOLD LINES INDICATE HIGH CURRENT PATHS 3410B F04b Figure 4b. LTC3410B-1.875 Layout Diagram Figure 4a. LTC3410B Layout Diagram VIA TO GND R1 VOUT VIN VIA TO VIN L1 PIN 1 L1 CFWD LTC3410B VIN VIA TO VIN VIA TO VOUT R2 PIN 1 VOUT SW LTC3410B1.875 SW COUT CIN COUT CIN GND 3410B F05a Figure 5a. LTC3410B Suggested Layout 3410B F05b Figure 5b. LTC3410B Fixed Output Voltage Suggested Layout 3410bfa 12 LTC3410B U W U U APPLICATIO S I FOR ATIO Design Example For best efficiency choose a 300mA or greater inductor with less than 0.3Ω series resistance. As a design example, assume the LTC3410B is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 0.3A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 2.5V. With this information we can calculate L using Equation (1), L= ⎛ V ⎞ 1 VOUT ⎜ 1− OUT ⎟ VIN ⎠ ( f )( ∆IL ) ⎝ CIN will require an RMS current rating of at least 0.125A ≅ ILOAD(MAX)/2 at temperature and COUT will require an ESR of less than 0.5Ω. In most cases, a ceramic capacitor will satisfy this requirement. For the feedback resistors, choose R1 = 412k. R2 can then be calculated from equation (2) to be: ⎛V ⎞ R2 = ⎜ OUT − 1⎟ R1 = 875.5k; use 887k ⎝ 0.8 ⎠ (3) Figure 6 shows the complete circuit along with its efficiency curve. Substituting VOUT = 2.5V, VIN = 4.2V, ∆IL = 100mA and f = 2.25MHz in Equation (3) gives: 2.5V ⎛ 2.5V ⎞ ⎜ 1− ⎟ = 4.5µH 2.25MHz(100mA) ⎝ 4.2V ⎠ VIN 2.7V TO 4.2V 4 † CIN 2.2µF CER VIN SW 3 4.7µH* VOUT 2.5V 10pF LTC3410B 1 COUT† 2.2µF CER RUN VFB 6 887k GND 2, 5 412k † TAIYO YUDEN JMK212BJ225 *MURATA LQH32CN4R7M23 3410 F07a Figure 6a 100 90 VOUT 100mV/DIV AC COUPLED 80 EFFICIENCY (%) L= 70 60 IL 200mA/DIV 50 40 ILOAD 200mA/DIV 30 20 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 0 1 10 100 OUTPUT CURRENT (mA) 1000 4µs/DIV VIN = 3.6V VOUT = 2.5V ILOAD = 100mA TO 300mA 3410 F07c 3410 F07b Figure 6b Figure 6c 3410bfa 13 LTC3410B U TYPICAL APPLICATIO VIN 2.7V TO 4.2V 4 † CIN 2.2µF VIN SW 3 VOUT 1.5V 10pF LTC3410B 1 4.7µH* COUT† 2.2µF RUN VFB 6 GND 2, 5 3410 TA02 402k 464k † TAIYO YUDEN JMK212BJ225 *MURATA LQH32CN4R7M23 100 90 EFFICIENCY (%) 80 70 60 50 40 30 20 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 0 1 10 100 OUTPUT CURRENT (mA) 1000 3410 TA03 VOUT 100mV/DIV AC COUPLED IL 200mA/DIV ILOAD 200mA/DIV 4µs/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 100mA TO 250mA 3410 TA04 3410bfa 14 LTC3410B U PACKAGE DESCRIPTIO SC6 Package 6-Lead Plastic SC70 (Reference LTC DWG # 05-08-1638) 0.47 MAX 0.65 REF 1.80 – 2.20 (NOTE 4) 1.00 REF INDEX AREA (NOTE 6) 1.80 – 2.40 1.15 – 1.35 (NOTE 4) 2.8 BSC 1.8 REF PIN 1 RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.10 – 0.40 0.65 BSC 0.15 – 0.30 6 PLCS (NOTE 3) 0.80 – 1.00 0.00 – 0.10 REF 1.00 MAX GAUGE PLANE 0.15 BSC 0.26 – 0.46 0.10 – 0.18 (NOTE 3) SC6 SC70 1205 REV B NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE INDEX AREA 7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70 8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB 3410bfa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC3410B U TYPICAL APPLICATIO Using Low Profile Components,