LTC3777
150V VIN and VOUT Synchronous
4-Switch Buck-Boost Controller +
Switching Bias Supply
DESCRIPTION
FEATURES
4-Switch Current Mode Single Inductor Architecture
Allows VIN Above, Below or Equal to VOUT
nn Wide V Range: 4.5V to 150V
IN
nn Wide Output Voltage Range: 1.2V ≤ V
OUT ≤ 150V
nn Synchronous Rectification: Up to 99% Efficiency
nn ±1% 1.2V Voltage Reference
nn Input or Output Average Current Limit
nn Integrated 12µA I , 150V, 85mA, Switching Bias
Q
for Optimal Thermal Performance
nn Programmable 6V to 10V DRV
CC Optimizes Efficiency
nn No Top FET Refresh Noise in Boost or Buck Mode
nn V
OUT Disconnected from VIN During Shutdown
nn Phase-Lockable Fixed Frequency (50kHz to 600kHz)
nn No Reverse Current During Start-Up
nn 150V Rated RUN Pin with Accurate Turn-On Threshold
nn Thermally Enhanced 48-Lead e-LQFP Package
The LTC®3777 is a high performance buck-boost switching
regulator controller that operates from input voltages
above, below or equal to the output voltage. The constant
frequency current mode architecture allows a phase-lockable
frequency of up to 600kHz, while an input/output constant
current loop provides support for battery charging. The
150V integrated switching bias supply is a high efficiency
step-down regulator that draws only 12µA typical DC supply
current with a regulated output voltage at no load.
nn
With a wide 4.5V to 150V input and output range and
seamless transfers between operating regions, the
LTC3777 is ideal for industrial, telecom and batterypowered systems.
The LTC3777 features a power good output indicator
and a MODE pin to select between pulse-skipping mode
or forced continuous mode of operation. The PLLIN pin
allows the IC to be synchronized to an external clock. The
SS pin ramps the output voltage during start-up. Current
foldback limits MOSFET heat dissipation during shortcircuit conditions.
APPLICATIONS
nn
Industrial, Transportation, Medical, Military, Avionics
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
4mΩ
VIN
16V TO 120V
20µF
5Ω
5µF
0.1µF
VINSNS
VIN
DRV CC
LTC3777
10µF
133k
BRUN
220µH
715k
BSW
BVFB
BGND
51.1k
1µF
10k
2.2µF
100k
0.1µF
56.2k
EXTV CC
RUN
PGOOD
V5
SS
FREQ
30
100
100Ω
98
SENSEN
220pF
SGND
PGND
4mΩ
100Ω
475k
BG2
BOOST2
24
EFFICIENCY
96
18
94
12
0.22µF
SW2
TG2
VOUTSNS
VFB
ITH
MODE
PLLIN
6
92
IAVGSNSP
IAVGSNSN
4.7µF
1k
100Ω
90
100Ω
100pF
10k
POWER LOSS (W)
1µF
Efficiency and Power Loss
vs Input Voltage
0.22µF
SW1
TG1
BG1
SENSEP
BVIN
BOV
56µF
15µH
VINOV
1.21k
44µF
BOOST1
EFFICIENCY (%)
1k
BVOUT
12V
85mA
VOUT
48V, 10A
30µF
VOUT = 48V
IOUT = 10A
0
POWER LOSS
0
12 24 36 48 60 72 84 96 108 120
VIN VOLTAGE (V)
3777 TA01b
12.1k
10nF
3777 TA01a
Rev A
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1
LTC3777
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
48
47
46
45
44
43
42
41
40
39
38
37
VFB
SS
V5
DRVCC
EXTVCC
DRVSET
VINOV
BG1
NC
SW1
TG1
BOOST1
TOP VIEW
BRUN 1
NC 2
BSW 3
NC 4
BVIN 5
NC 6
BOV 7
BFBO 8
NC 9
BGND 10
BISET 11
BVFB 12
36
35
34
33
32
31
30
29
28
27
26
25
49
PGND
VIN
NC
VINSNS
NC
VOUTSNS
NC
IAVGSNSN
IAVGSNSP
NC
RUN
NC
BOOST2
SENSEP 13
SENSEN 14
ITH 15
SGND 16
MODE 17
PLLIN 18
FREQ 19
PGOOD 20
BG2 21
NC 22
SW2 23
TG2 24
Input Supply Voltage (VIN), BVIN............... 150V to –0.3V
Topside Driver Voltage
BOOST1, BOOST2......................................161V to –0.3V
Switch Voltage SW1, SW2........................... 150V to –5V
RUN, BRUN............................................... 150V to –0.3V
IAVGSNSP , IAVGSNSN.....................................150V to –10V
VINSNS, VOUTSNS....................................... 150V to –0.3V
EXTVCC Voltage......................................... 36V to –0.3V
DRVCC Voltage.............................................11V to –0.3V
BOOST1-SW1, BOOST2-SW2.......................11V to –0.3V
TG1-SW1, TG2-SW2, BG1, BG2........................... (Note 8)
V5, BOV, BFBO, BVFB, BISET Voltage............. 6V to –0.3V
MODE, PLLIN, SS, PGOOD........................... V5 to –0.3V
ITH, FREQ, DRVSET...................................... V5 to –0.3V
SENSEP, SENSEN, VINOV............................. V5 to –0.3V
VFB Voltage................................................ 2.7V to –0.3V
Operating Junction Temperature
Range (Notes 2, 3).................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
EXTVCC /DRVCC Peak Current...............................100mA
LXE PACKAGE
48-LEAD (7mm × 7mm) PLASTIC e-LQFP
TJMAX = 150°C, θJA = 36°C/W
EXPOSED PAD (PIN 49) IS PGND, MUST BE SOLDERED TO PCB
FOR RATED ELECTRICAL AND THERMAL CHARACTERISTICS
ORDER INFORMATION
LEAD FREE FINISH
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3777ELXE#PBF
LTC3777 LXE
48-Lead (7mm × 7mm) Plastic e-LQFP
–40°C to 125°C
LTC3777ILXE#PBF
LTC3777 LXE
48-Lead (7mm × 7mm) Plastic e-LQFP
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev A
2
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LTC3777
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 15V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VVINOV = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Input Supply Operating Voltage Range
(Note 4)
4.5
VOUT
IQ
Output Supply Operating Voltage Range
TYP
1.2
V
150
V
1.212
V
(Note 5)
–15
-50
nA
(Note 5); VIN = 7V to 100V
0.02
0.2
%
0.01
0.2
%
(Note 5); ITH Voltage = 1.4V
Feedback Current
Reference Voltage Line Regulation
Output Voltage Load Regulation
(Note 5); Measured in Servo Loop; ∆ITH
Voltage = 1.5V to 2V
Transconductance Amplifier gm
(Note 5); ITH = 1.4V; Sink/Source 5µA
1.5
Input DC Supply Current
(Note 6)
3.6
Shutdown
RUN = 0V
Undervoltage Lockout
V5 Ramping Up
4.1
V5 Ramping Down
3.6
VRUN Rising
1.1
l
1.188
l
RUN Pin Hysteresis
RUN Pin Source Current
UNITS
150
1.2
Regulated Feedback Voltage
RUN Pin ON Threshold
MAX
VRUN < 1.2V
RUN Pin Hysteresis Current
VRUN > 1.2V
VIN Overvoltage Lockout Threshold
(Rising)
VVINOV Rising
mmho
5.5
mA
40
75
µA
4.35
4.6
V
3.85
4.1
V
1.2
1.3
V
100
mV
2.5
µA
6.5
1.18
VIN Overvoltage Hysteresis
1.28
µA
1.38
50
V
mV
SENSE Pins Current
VSENSEP = VSENSEN = 0
±2
µA
IAVGSNS Pins Current
VIAVGSNSP = VIAVGSNSN = 10V
15
µA
Soft-Start Charge Current
VSS = 0V
Maximum Current Sense Threshold
(Buck Region Valley Current Mode)
VFB = 1V
Maximum Current Sense Threshold
(Boost Region Peak Current Mode)
VFB = 1V
Maximum Input / Output Average
Current Sense Threshold
VIAVGSNSP = VIAVGSNSN = 10V, VFB = 1V
DC(MAX, BOOST)
Maximum Duty Factor
% Switch C On
90
%
DC(MIN, BOOST)
Minimum Duty Factor for Main Switch in % Switch C On
Boost Operation
9
%
DC(MIN, BUCK)
Minimum Duty Factor for Main Switch in % Switch B On
Buck Operation
9
%
IAVGSNSP
IAVGSNSN
VSENSE(MAX)
4
5
6
µA
l
70
90
110
mV
l
120
140
160
mV
47.5
50
52.5
mV
Gate Driver
TG Pull-Up On Resistance
TG Pull-Down On Resistance
VDRVCC = 6V
3.1
1.5
Ω
BG Pull-Up On Resistance
BG Pull-Down On Resistance
VDRVCC = 6V
5.5
3
Ω
TG Transition Time:
Rise Time
Fall Time
VDRVCC = 6V (Note 7)
CLOAD = 3300pF
60
ns
BG Transition Time:
Rise Time
Fall Time
VDRVCC = 6V (Note 7)
CLOAD = 3300pF
60
ns
Rev A
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3
LTC3777
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 15V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VVINOV = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVCC = 6V
60
ns
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVCC = 6V
60
ns
DRVCC LDO Regulator
VDRVCC
VEXTVCC
DRVCC Regulation Voltage from Internal
VIN LDO
VEXTVCC = 0V
7V < VIN < 150V, VDRVSET = 0V
8V < VIN < 150V, VDRVSET = 1/4 VV5
9V < VIN < 150V, VDRVSET = Float
10V < VIN < 150V, VDRVSET = 3/4 VV5
11V < VIN < 150V, VDRVSET = VV5
DRVCC Load Regulation from VIN LDO
DRVCC Regulation Voltage from Internal
EXTVCC LDO
ICC = 0mA to 50mA, VEXTVCC = 0V
DRVCC Load Regulation from Internal
EXTVCC LDO
ICC = 0mA to 50mA, VEXTVCC = 12V
VDRVSET = 0V
EXTVCC LDO Switchover Voltage
EXTVCC Ramping Positive
EXTVCC Hysteresis
% of DRVCC Regulation Voltage
5.5
6.5
7.5
8.45
9.15
7V < VEXTVCC < 30V, VDRVSET = 0V
8V < VEXTVCC < 30V, VDRVSET = 1/4 VV5
9V < VEXTVCC < 30V, VDRVSET = Float
10V < VEXTVCC < 30V, VDRVSET = 3/4 VV5
11V < VEXTVCC < 30V, VDRVSET = VV5
5.8
6.8
7.8
8.75
9.65
5.8
6.8
7.8
8.8
9.5
6.1
7.1
8.1
9.15
9.85
V
V
V
V
V
0.5
2
%
6.1
7.1
8.1
9.1
10
6.4
7.4
8.4
9.45
10.35
V
V
V
V
V
0.5
2
%
DRVCC – 0.5
V
10
%
V5 Linear Regulator
V5 Regulation Voltage
6V < VDRVCC < 10V
V5 Load Regulation
IV5 = 0mA to 20mA, VDRVCC = 7V
5.3
5.5
5.7
V
0.5
1
%
250
275
kHz
Oscillator and Phase-Locked Loop
Nominal Frequency
RFREQ = 68.5kΩ
Low Fixed Frequency
RFREQ ≤ 20kΩ
30
40
50
kHz
High Fixed Frequency
RFREQ = 135kΩ
450
500
550
kHz
PLLIN Input Threshold
VPLLIN Rising
VPLLIN Falling
1.2
V
V
600
kHz
20
22
µA
0.1
0.3
V
±1
µA
225
2
PLLIN Input Resistance
Synchronizable Oscillator Frequency
IFREQ
200
PLLIN = External Clock
Frequency Setting Current
l
50
l
18
kΩ
PGOOD Output
PGOOD Voltage Low
IPGOOD = 2mA
PGOOD Leakage Current
VPGOOD = 5.5V
PGOOD Trip Level
VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
PGOOD delay
–10
%
VFB Ramping Positive
10
%
VPGOOD High to Low
125
µs
Rev A
4
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LTC3777
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). BVIN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
150
V
Switching Bias Supply
VBVIN
Input Voltage Operating Range
4
VBVOUT
Output Voltage Operating Range
(Note 9)
0.8
BUVLO
BVIN Undervoltage Lockout
BVIN Rising
BVIN Falling
Hysteresis
3.5
3.3
IQB
DC Supply Current (Note 6)
Active Mode
Sleep Mode
Shutdown Mode
No Load
BVRUN = 0V
VIN
V
3.8
3.6
250
4.15
3.95
V
V
mV
150
12
1.4
350
22
6
µA
µA
µA
1.2
1.09
110
1.3
1.19
V
V
mV
VBRUN
BRUN Pin Threshold
BRUN Rising
BRUN Falling
Hysteresis
1.1
0.99
IBRUN
BRUN Pin Leakage Current
BRUN = 1.3V (Note 9)
–10
0
10
nA
VBOV
BOV Pin Threshold
BOV Rising
BOV Falling
Hysteresis
1.1
0.99
1.2
1.09
110
1.3
1.19
V
V
mV
0.786
0.800
0.814
3
5
9
mV
Output Supply (BVFB)
VBVFB
Feedback Comparator Threshold
BVFB Rising
VBVFBH
Feedback Comparator Hysteresis
BVFB Falling (Note 9)
V
IBVFB
Feedback Pin Current
BVFB = 1V (Note 9)
–10
0
10
nA
IPEAKB
Peak Current Comparator Threshold
BISET Floating
BISET Shorted to GND
170
17
240
25
310
33
mA
mA
ILBSWB
Switch Pin Leakage Current
BVIN = 150V, BSW = 0V
0.1
1
μA
tINT(SS)B
Internal Soft-Start Time
(Note 9)
Operation
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3777 is tested under pulsed load conditions such that TJ
≈ TA. The LTC3777E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3777I is guaranteed over the full –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature TJ
is calculated from the ambient temperature TA and power dissipation PD
according to the formula:
TJ = TA + (PD • θJA),
where θJA = 36°C/W for the e-LQFP package.
Note 3: This IC includes over temperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
1
ms
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: When biased from an auxiliary supply through the EXTVCC pin, the
LTC3777 can operate from a VIN voltage lower than 4.5V. Otherwise the
minimum VIN operational voltage is 4.5V after startup.
Note 5: The LTC3777 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB.
Note 6: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
Note 7: Rise and fall times are measured using 10% and 90% levels.
Delay times are measured using 50% levels.
Note 8: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur. These pins are rated for an absolute maximum voltage of –0.3V
to 11V.
Note 9: Guaranteed by design and wafer level measurements.
Rev A
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5
LTC3777
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Load Current and Input Voltage
Continuous Mode
96
10
EFFICIENCY
VOUT = 48V
fSW = 250kHz
6
84
VIN = 72V
VIN = 48V
VIN = 24V
80
76
5
4
72
3
68
2
10
6
94
EFFICIENCY
4
91
POWER LOSS
2
88
0
85
5
10 15 20 25 30 35 40 45 50 55
VIN VOLTAGE (V)
ILOAD
5A/DIV
IL
5A/DIV
IL
5A/DIV
VOUT
1V/DIV
AC-COUPLED
VOUT
1V/DIV
AC-COUPLED
Load Step Buck-Boost Region
Continuous Mode
ILOAD
5A/DIV
IL
5A/DIV
VOUT
1V/DIV
AC-COUPLED
3777 G03
VIN = 36V
VOUT = 48V
Load Step Buck-Boost Region
Pulse-Skipping Mode
200µs/DIV
3777 G04
VIN = 48V
VOUT = 48V
Load Step Buck Region
Continuous Mode
ILOAD
5A/DIV
ILOAD
5A/DIV
IL
5A/DIV
IL
5A/DIV
IL
5A/DIV
VOUT
1V/DIV
AC-COUPLED
VOUT
1V/DIV
AC-COUPLED
VOUT
1V/DIV
AC-COUPLED
3777 G06
VIN = 120V
VOUT = 48V
200µs/DIV
200µs/DIV
3777 G05
Load Step Buck Region
Pulse-Skipping Mode
ILOAD
5A/DIV
200µs/DIV
0
3777 G02
Load Step Boost Region
Pulse-Skipping Mode
ILOAD
5A/DIV
VIN = 48V
VOUT = 48V
10
8
97
3777 G01
Load Step Boost Region
Continuous Mode
200µs/DIV
FIGURE 18 CIRCUIT
1
POWER LOSS
60
0.1
1
LOAD CURRENT (A)
CIRCUIT OF FIGURE 19
VOUT = 12V
IOUT = 5A
POWER LOSS (W)
7
64
VIN = 36V
VOUT = 48V
8
88
POWER LOSS (W)
EFFICIENCY (%)
92
100
9
EFFICIENCY (%)
100
Efficiency and Power Loss
vs Input Voltage
3777 G07
VIN = 120V
VOUT = 48V
200µs/DIV
3777 G08
Rev A
6
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LTC3777
TYPICAL PERFORMANCE CHARACTERISTICS
Forced Continuous Mode
Boost Region
Forced Continuous Mode
Buck-Boost Region
Pulse-Skipping Mode
Boost Region
SW1
100V/DIV
SW1
100V/DIV
SW1
100V/DIV
SW2
100V/DIV
SW2
100V/DIV
SW2
100V/DIV
IL
5A/DIV
IL
5A/DIV
IL
1A/DIV
VOUT
200mV/DIV
AC-COUPLED
VOUT
200mV/DIV
AC-COUPLED
VOUT
200mV/DIV
AC-COUPLED
VIN = 24V
VOUT = 48V
ILOAD = 0A
5µs/DIV
3777 G09
VIN = 24V
VOUT = 48V
ILOAD = 0A
5µs/DIV
3777 G10
VIN = 48V
VOUT = 48V
ILOAD = 0A
Forced Continuous Mode
Buck Region
Pulse-Skipping Mode
Buck-Boost Region
SW1
100V/DIV
SW1
100V/DIV
SW2
100V/DIV
SW2
100V/DIV
SW2
100V/DIV
IL
1A/DIV
IL
5A/DIV
IL
5A/DIV
VOUT
200mV/DIV
AC-COUPLED
VOUT
200mV/DIV
AC-COUPLED
VOUT
200mV/DIV
AC-COUPLED
5µs/DIV
3777 G12
VIN = 120V
VOUT = 48V
ILOAD = 0A
Start-Up from RUN
Forced Continuous Mode
Pre-Biased Output
5µs/DIV
3777 G13
VIN = 120V
VOUT = 48V
ILOAD = 0A
Start-Up Forced Continuous Mode
Boost Region
SW1
50V/DIV
SW1
100V/DIV
SW2
50V/DIV
SW2
100V/DIV
IL
5A/DIV
IL
500mA/DIV
IL
500mA/DIV
VOUT
50V/DIV
VOUT
50V/DIV
VOUT
50V/DIV
3777 G15
5ms/DIV
VIN = 24V
VOUT = 48V
15Ω RESISTIVE LOAD
3777 G16
5µs/DIV
3777 G14
Start-Up Forced Continuous Mode
Buck-Boost Region
SW1
100V/DIV
SW2
100V/DIV
2.5ms/DIV
VIN = 24V
VOUT = 48V
VOUT PRE-BIAS = 12V
200mA LOAD
3777 G11
Pulse-Skipping Mode
Buck Region
SW1
100V/DIV
VIN = 48V
VOUT = 48V
ILOAD = 0A
5µs/DIV
5ms/DIV
VIN = 48V
VOUT = 48V
15Ω RESISTIVE LOAD
3777 G17
Rev A
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7
LTC3777
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown from RUN
Forced Continuous Mode
Boost Region
Start-Up Forced Continuous Mode
Buck Region
SW1
100V/DIV
SW2
100V/DIV
IL
500mA/DIV
VOUT
50V/DIV
5ms/DIV
VIN = 120V
VOUT = 48V
15Ω RESISTIVE LOAD
Shutdown from RUN
Pulse-Skipping Mode
Boost Region
RUN
5V/DIV
RUN
5V/DIV
SW1
100V/DIV
SW2
100V/DIV
IL
20A/DIV
SW1
100V/DIV
SW2
100V/DIV
IL
20A/DIV
VOUT
50V/DIV
VOUT
50V/DIV
3777 G18
200µs/DIV
VIN = 24V
VOUT = 48V
5A LOAD
Shutdown from RUN
Forced Continuous Mode
Buck-Boost Region
3777 G19
Shutdown from RUN
Forced Continuous Mode
Buck Region
RUN
5V/DIV
SW1
100V/DIV
SW1
100V/DIV
VIN
100V/DIV
12V to 120V
SW2
100V/DIV
IL
2A/DIV
SW2
100V/DIV
IL
20A/DIV
ITH
2V/DIV
IL
1A/DIV
VOUT
50V/DIV
VOUT
50V/DIV
VOUT
500mV/DIV
AC-COUPLED
200µs/DIV
3777 G21
Line Transient Falling Edge
10.5
IL
1A/DIV
VOUT
500mV/DIV
AC-COUPLED
1ms/DIV
1ms/DIV
VOUT = 48V
6.5
VIN LDO, EXTVCC = 0V
EXTVCC = 12V
DRVCC VOLTAGE (V)
DRVCC VOLTAGE (V)
ITH
2V/DIV
3777 G22
DRVCC vs Load Current
VIN
100V/DIV
VOUT = 48V
200µs/DIV
VIN = 120V
VOUT = 48V
ILOAD = 5A
3777 G20
Line Transient Rising Edge
RUN
5V/DIV
VIN = 48V
VOUT = 48V
NO LOAD
200µs/DIV
VIN = 24V
VOUT = 48V
5A LOAD
10.0
9.5
3777 G23
DRVCC vs Load Current
label2
label5
label4
label3
VIN LDO, EXTVCC = 0V
EXTVCC = 8.5V
6.0
5.5
3777 G24
9.0
VIN = 12V
DRVSET = V5
0
20
40
60
80
LOAD CURRENT (mA)
100
3777 G25
5.0
VIN = 12V
DRVSET = 0V
0
20
40
60
80
LOAD CURRENT (mA)
100
3777 G26
Rev A
8
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LTC3777
TYPICAL PERFORMANCE CHARACTERISTICS
VINOV Transient Forced
Continuous Mode Buck Region
Peak Current Threshold vs VITH
(Boost)
Current Foldback Limit
IL
10A/DIV
VOUT
50V/DIV
3777 G27
10ms/DIV
VIN = 120V
VOUT = 48V
50Ω RESISTIVE LOAD
200
BOOST
150
100
50
0
–50
–100
BUCK
–150
0
CURRENT LIMIT (SENSEP – SENSEN) (mV)
SW2
100A/DIV
CURRENT LIMIT (SENSEP – SENSEN) (mV)
200
SW1
100V/DIV
150
100
50
0
–50
–100
–150
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VFB (V)
0
0.4
0.8
3777 G28
Valley Current Threshold vs VITH
(Buck)
0
–50
–100
0
100
BOOST
50
0
–50
BUCK
1210
1200
1190
0
25 50 75 100 125 150
TEMPERATURE (°C)
1180
–50 –25
V5 Low Dropout Regulation
Voltage vs Temperature
12
4.1
4.0
3.9
3.8
5.6
10
DRVCC (V)
RISING
5.5
EXTVCC = 30V
9
8
DRVSET = V5
DRVSET = 3/4 • V5
DRVSET = 1/2 • V5
DRVSET = 1/4 • V5
7
5.4
DRVSET = GND
FALLING
0
EXTVCC LDO vs Temperature
11
V5 LDO VOLTAGE (V)
UVLO THRESHOLD (V)
4.3
3.6
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3777 G32
5.7
3.7
0
3777 G31
Undervoltage Lockout Threshold
(V5) vs Temperature
4.2
3777 G29
–100
3777 G30
4.4
2.8
150
–150
–50 –25
0.2 0.4 0.6 0.8 1.1 1.3 1.5 1.7 1.9 2.1
VITH (V)
2.4
1220
FEEDBACK VOLTAGE (mV)
CURRENT LIMIT (SENSEP – SENSEN) (mV)
CURRENT LIMIT (SENSEP – SENSEN) (mV)
200
50
2.0
Regulated Feedback Voltage
vs Temperature
Maximum Current Limit
vs Temperature
100
1.2 1.6
VITH (V)
6
25 50 75 100 125 150
TEMPERATURE (°C)
5.3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3777 G33
3777 G34
5
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3777 G35
Rev A
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9
LTC3777
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Temperature
VIN LDO vs Temperature
800
700
SWITCHING FREQUENCY (kHz)
11
DRVCC (V)
20.5
FREQ = V5
DRVSET = V5, VIN = 11V
9
DRVSET = 3/4 • V5, VIN = 10V
8
DRVSET = 1/2 • V5, VIN = 9V
7
DRVSET = 1/4 • V5, VIN = 8V
6
DRVSET = GND, VIN = 7V
5
–50 –25
0
20.2
RFREQ = 120k
500
400
300
RFREQ = 67.5k
RFREQ = 27.5k
0
–50 –25
0
19.7
FREQ = GND
19.6
19.5
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
5.2
RUN THRESHOLD (V)
ON
OFF
1.2
1.1
1.0
1
25 50 75 100 125 150
TEMPERATURE (°C)
0.9
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
Soft-Start Pull-Up Current
vs Temperature
SS PULL–UP CURRENT (µA)
1.3
2
0
3777 G38
1.4
4
SUPPLY CURRENT (mA)
19.9
RUN Threshold vs Temperature
5
0
20.0
3777 G37
Input Supply Current
vs Temperature
0
–50 –25
20.1
19.8
200
3777 G36
3
VFREQ = 0.8V
20.3
600
100
25 50 75 100 125 150
TEMPERATURE (°C)
20.4
IFREQ (µA)
12
10
Frequency Setting Current
vs Temperature
0
25 50 75 100 125 150
TEMPERATURE (°C)
3777 G40
3777 G39
5.1
5.0
4.9
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3777 G41
Rev A
10
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LTC3777
TYPICAL PERFORMANCE CHARACTERISTICS – SWITCHING BIAS SUPPLY
Efficiency vs Load Current,
BVOUT = 12V
Feedback Comparator Trip
Threshold vs Temperature
BRUN and BOV Comparator
Threshold vs Temperature
BRUN OR BOV THRESHOLD VOLTAGE (V)
802
100
EFFICIENCY (%)
84
76
68
60
52
44
BISET OPEN
36
BVIN = 36V
BVIN = 72V
BVIN = 150V
28
20
0.1
1
10
LOAD CURRENT (mA)
BVFB THRESHOLD VOLTAGE (V)
92
801
800
799
798
–55
100
95
5
35
65
TEMPERATURE (°C)
–25
125
30
SLEEP
BVIN SUPPLY CURRENT (µA)
BVIN SUPPLY CURRENT (µA)
15
10
5
SHUTDOWN
0
30
60
90
BVIN VOLTAGE (V)
1.20
1.18
1.16
1.14
1.12
1.08
1.06
–55 –25
120
150
20
3777 G44
SHUTDOWN
65
35
5
95
TEMPERATURE (°C)
3777 G47
BVIN = 48V
200µs/DIV
BVOUT = 3.3V
1mA TO 100mA LOAD STEP
FIGURE 18 CIRCUIT
10
–25
155
LOAD
CURRENT
50mA/DIV
SLEEP
0
–55
125
OUTPUT
VOLTAGE
50mV/DIV
25
5
65
35
95
5
TEMPERATURE (°C)
Load Step Transient Response
BVIN = 150V
15
FALLING
1.10
Quiescent Supply Current
vs Temperature
Quiescent Supply Current
vs Input Voltage
RISING
1.22
3777 G43
3777 G42
0
155
1.24
125
155
3777 G45
3777 G46
Operating Waveforms, BVIN = 48V
OUTPUT
VOLTAGE
50mV/DIV
Operating Waveforms, BVIN = 150V
OUTPUT
VOLTAGE
100mV/DIV
SWITCH
VOLTAGE
20V/DIV
OUTPUT
VOLTAGE
1V/DIV
SWITCH
VOLTAGE
50V/DIV
INDUCTOR
CURRENT
200mA/DIV
BVIN = 48V
10µs/DIV
BVOUT = 3.3V
BIOUT = 100mA
FIGURE 18 CIRCUIT
3777 G48
Short-Circuit and Recovery
INDUCTOR
CURRENT
100mA/DIV
INDUCTOR
CURRENT
200mA/DIV
500µs/DIV
FIGURE 18 CIRCUIT
BVIN = 150V
BVOUT = 12V
BIOUT = 50mA
50µs/DIV
3777 G50
3777 G49
Rev A
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11
LTC3777
PIN FUNCTIONS
BRUN (Pin 1): Bias Supply Run Control Input. A voltage
on this pin above 1.21V enables normal operation.
Forcing this pin below 0.7V shuts down the switching
bias supply, reducing quiescent current to approximately
1.4µA. Optionally, connect to the input supply through a
resistor divider to set the undervoltage lockout.
BSW (Pin 3): Bias Supply Switch Node Connection to
Inductor. This pin connects to the drains of the internal
power MOSFET switches.
BVIN (Pin 5): Bias Supply Main Supply Pin. A ceramic
bypass capacitor should be tied between this pin and
GND.
BOV (Pin 7): Bias Supply Overvoltage Lockout Input.
Connect to the input supply through a resistor divider
to set the overvoltage lockout level. A voltage on this
pin above 1.21V disables the internal MOSFET switches.
Normal operation resumes when the voltage on this pin
decreases below 1.10V. Exceeding the OVLO lockout
threshold triggers a soft-start reset, resulting in a graceful
recovery from an input supply transient. Tie this pin to
ground if the overvoltage is not used.
BFBO (Pin 8): Bias Supply Feedback Comparator Output.
The typical pull-up current is 20µA. The typical pull-down
impedance is 70Ω. This output signal can be used to
synchronize other ICs.
BGND (Pin 10): Ground.
BISET (Pin 11): Bias Supply Peak Current Set Input. Leave
floating for the maximum peak current (230mA typical) or
short to ground for minimum peak current (25mA typical).
The maximum output current is one-half the peak current.
BVFB (Pin 12): Bias Supply Output Voltage Feedback.
Connect to an external resistive divider to divide the output
voltage down for comparison to the 0.8V reference.
SENSEP (Pin 13): The positive input to the differential
current comparator. This pin is normally connected to a
sense resistor at the source of the power MOSFET. The ITH
pin voltage and controlled offsets between the SENSEP
and SENSEN pins, in conjunction with RSENSE , set the
current trip threshold.
SENSEN (Pin 14): The negative input to the differential
current sense comparator. This pin is normally connected
to the ground side of the sense resistor.
ITH (Pin 15): Error Amplifier Output. The current
comparator trip threshold increases with the ITH control
voltage. The ITH pin is also used for compensating the
control loop of the converter.
SGND (Pin 16): Signal ground. All feedback and soft-start
connections should return to SGND. For optimum load
regulation, the SGND pin should be Kelvin connected to
the PCB location between the negative terminals of the
output capacitors.
MODE (Pin 17): Mode Selection pin. Tying this pin to
SGND or below 0.8V enables forced continuous mode.
Tying it to V5 enables pulse-skipping mode.
PLLIN (Pin 18): External Synchronization Input to Phase
Detector. For external sync, apply a clock signal to this pin
and the internal PLL will synchronize the internal oscillator
to the clock. The PLL compensation network is integrated
into the IC. When synchronized to an external clock, the
regulator can operate either in forced continuous or pulseskipping mode. The mode of operation is controlled by
the setting on the MODE pin.
FREQ (Pin 19): The frequency control pin for the internal
VCO. Frequencies between 40kHz and 500kHz can be
programmed by using a resistor between FREQ and
SGND. The resistor and an internal 20µA source current
create a voltage used by the internal oscillator to set the
frequency.
PGOOD (Pin 20): Fault indicator Output. Open-drain
output that pulls to ground when the voltage on the VFB
pin is not within ±10% of its set point.
BG1/BG2 (Pins 41 and 21): Bottom Gate Driver Outputs.
This pin drives the gate(s) of the bottom N-Channel
MOSFET between PGND to DRVCC.
SW1, SW2 (Pins 39 and 23): Switch Node Connections
to the Inductors.
Rev A
12
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LTC3777
PIN FUNCTIONS
TG1, TG2 (Pin 38 and 24): High Current Gate Drives
for Top N-Channel MOSFETs. These are the outputs of
floating high side drivers with a voltage swing equal to
DRVCC superimposed on the switch node voltage SW.
BOOST1. BOOST2 (Pin 37 and 25): Boosted Floating
Driver Supplies. The (+) terminal of the bootstrap
capacitor connects to this pin. This pin swings from a
diode drop below DRVCC up to VIN + DRVCC.
RUN (Pin 27): Enable Control Input. A voltage above 1.2V
turns on the IC. There is a 2.5µA pull-up current on this
pin. Once the RUN pin rises above the 1.2V threshold the
pull-up current increases to 6.5µA. Forcing this pin below
1.1V shuts down the controller. This pin can be tied to VIN
for always-on operation. Do not float this pin.
IAVGSNSP (Pin 29): The positive input to the Input / Output
Average Current Sense Amplifier.
IAVGSNSN (Pin 30): The negative input to the Input / Output
Average Current Sense Amplifier. Short IAVGSNSP and
IAVGSNSN pins together, and tie them to V5, if this average
current loop function is not used.
VOUTSNS (Pin 32): VOUT Sense Input to the Buck-Boost
Transition comparator. Connect this pin to the drain of
the top N-channel MOSFET on the output side through
a 1kΩ resistor.
VINSNS (Pin 34): VIN Sense Input to the Buck-Boost
Transition comparator. Connect this pin to the drain of
the top N-channel MOSFET on the input side.
VIN (Pin 36): Main Supply Pin. A bypass capacitor should
be tied between this pin and the PGND pin.
VINOV (Pin 42): Connect to the input supply through a
resistor divider to set the over-voltage lockout level. A
voltage on this pin above 1.28V disables all switching,
and the top GATE pins are held low, the bottom GATE pins
are held high, and VOUT is disconnected from VIN. DRVCC
and V5 regulation is maintained during an over-voltage
event. Normal operation resumes when the voltage on this
pin decreases below 1.23V. Exceeding the VINOV lockout
threshold triggers a soft-start reset, resulting in a graceful
recovery from an input supply transient. Tie this pin to
ground if the overvoltage function is not used.
DRVSET (Pin 43): Sets the regulated output voltage of the
DRVCC linear regulator from 6V to 10V in 1V increments.
Tying this pin to SGND sets DRVCC to 6V, tying it to
1/4 • V5 sets DRVCC to 7V, while floating this pin sets
DRVCC to 8V, tying it to 3/4 •V5 sets DRVCC to 9V, and
tying it to V5 sets DRVCC to 10V.
EXTVCC (Pin 44): External Power Input to an Internal
LDO Connected to DRVCC. When the voltage on this pin
is greater than the DRVCC LDO setting minus 500mV, this
LDO bypasses the internal LDO powered from VIN. Tie this
pin to ground if the EXTVCC is not used.
DRVCC (Pin 45): Output of the Internal or External Low
Dropout Regulator. The gate drivers are powered from
this voltage source. The DRVCC voltage is set by the
DRVSET pin. A low ESR 4.7µF (X5R or better) ceramic
bypass capacitor should be connected between DRVCC
and PGND, as close as possible to the IC. Do not use the
DRVCC pin for any other purpose.
V5 (Pin 46): Output of the Internal 5.5V Low Dropout
Regulator. The control circuits are powered from this
voltage. Bypass this pin to SGND with a minimum of
2.2µF low ESR tantalum or ceramic capacitor, as close
as possible to the IC.
SS (Pin 47): Soft-Start Input. The voltage ramp rate at this
pin sets the voltage ramp rate of the regulated voltage.
This pin has a 5μA pull-up current. A capacitor to ground
at this pin sets the ramp time to final regulated output
voltage.
VFB (Pin 48): Error Amplifier Input. The FB pin should be
connected through a resistive divider network to VOUT to
set the output voltage.
PGND (Exposed Pad Pin 49): Driver Power Ground.
Connects to the (–) terminal of CIN, COUT and RSENSE.
The exposed pad must be soldered to PCB ground for
electrical contact and rated thermal performance.
Rev A
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13
LTC3777
BLOCK DIAGRAM
42
VINOV
1.2V
27
34
32
17
2.5µA
RUN
+
–
OV
–
+
SHDN
VINSNS
VOUTSNS
BUCK/BOOST
TRANSITION
DETECTOR
MODE
MODE
SELECT
200k
VOUT /BOOST2
CHARGE
CONTROL
VIN /BOOST1
VIN
+
SW1
–
IDREV
DRVCC
BOOST1
BOOST2
BOOST1
18
SW1
DRVCC
BG1
PGND
IREV
+
BG2
CCM
–
DCM
FCB
VFLD
PLLIN
TG1
FCB
CCM/DCM
BUCK
LOGIC
BBT
PHASE DET
BOOST
LOGIC
DRVCC
BOOST2
200k
20µA
19
–
FREQ
SW2
TG2
ICMP
+
VIN
DA
37
FET A
38
D1
39
41
FET B
49
L1
RSENSE
21
23
FET D
CB
25
DB
IAVGSNSP
+
DRVCC
29
A1
IAVGSNSN
–
SLOPE
RSENSE2
30
+
IOS
5
VIN
1
L2
3
VBVOUT
R3
12
R4
7
10
8
11
36
BVIN
VOUT
COUT
–
EA
BRUN
5µA
BSW
BVFB
VFB
–
+
+
1.2V
BOV
SS
ITH
LOW IQ
SWITCHING
BIAS
SUPPLY
SENSEP
BGND
SENSEN
BFBO
1.32V
BISET
DRVCC LDO
CONTROL
VIN
+
–
VIN LDO
45
FET C
D2
24
OV/SHDN
OSCILLATOR
CIN
CA
VFB
1.08V
+
–
+
–
PGOOD
48
47
R1
R2
15
13
14
20
–
+
DRVSET
+
–
EXTVCC LDO
DRVCC
4R
CDRVCC
16 SGND
V5
UVLO
1R
EXTVCC
44
43
V5
LDO
UVLO
DRVSET
46
V5
3777 BD
CV5
Rev A
14
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LTC3777
OPERATION
MAIN CONTROL LOOP
The LTC3777 is a 150V synchronous buck-boost
controller with an integrated 150V, 85mA, high efficiency
synchronous switching bias supply. The 150V switching
bias supply draws only 12µA typical DC supply current
while maintaining a regulated output voltage at no load.
The 150V synchronous buck-boost is a current mode
controller that provides an output voltage above, equal
to or below the input volt- age. The ADI proprietary
topology and control architecture employs a currentsensing resistor. The inductor current is controlled by the
voltage on the ITH pin, which is the output of the error
amplifier EA. The VFB pin receives the voltage feedback
signal, which is compared to the internal reference voltage
by the EA. If the input/output current regulation loop is
implemented, the sensed inductor current is controlled
by either the sensed feedback voltage or the input/output
current.
DRVCC /EXTVCC / V5 Power
Power for the top and bottom MOSFET drivers is derived
from the DRVCC pin. The DRVCC supply voltage can be
programmed from 6V to 10V in 1V steps using the
DRVSET pin. The internal VIN LDO (low dropout linear
regulator) can provide power from VIN to DRVCC. The
internal VIN LDO uses an internal P-channel pass device
between the VIN and DRVCC pins. To prevent high on-chip
power dissipation in high input voltage applications, the
LTC3777 also includes an integrated 150V, low IQ 85mA
synchronous step-down regulator to bias the buck-boost
controller. See Integrated Switching Bias Supply in the
Operation section for more information.
When the EXTVCC pin is tied to a voltage below its
switchover voltage (DRVCC – 500mV), the VIN LDO
is enabled and supplies power from VIN to DRVCC. If
EXTVCC is taken above its switchover voltage, the VIN
LDO is turned off and an EXTVCC LDO is turned on. Once
enabled, the EXTVCC LDO supplies power from EXTVCC
to DRVCC. Using the EXTVCC pin allows the DRVCC power
to be derived from a high efficiency supply such as the
low IQ integrated step-down regulator bias supply or the
LTC3777 switching regulator output if the output voltage
is less than 36V.
Most of the internal circuitry is powered from the V5
rail that is generated by an internal linear regulator from
DRVCC. The V5 pin needs to be bypassed with a 1µF to
10µF external capacitor between V5 and SGND. This pin
provides a 5.5V output that can supply up to 20mA of
current. See the Applications Information section for more
details.
Top MOSFET DRIVER and Internal Charge Path
Each of the two top MOSFET drivers is biased from its
floating bootstrap capacitor, which is normally recharged
by DRVCC through an external diode when the top MOSFET
is turned off and when SW goes low. When the LTC3777
operates exclusively in the buck or boost regions, one
of the top MOSFETs is constantly on. An internal charge
path, from VOUT and BOOST2 to B00ST1 or from VIN and
B00ST1 to B00ST2, charges the bootstrap capacitor so
that the top MOSFET can be kept on. However, if a high
leakage external diode is used such that the internal charge
path cannot provide sufficient charge to the external
bootstrap capacitor, an internal UVLO comparator, which
constantly monitors the drop across the capacitor, will
sense the (BOOST – SW) voltage when it is below the
boost capacitor refresh threshold. This will turn off its top
MOSFET for about one-twelfth of the clock period every
four cycles to allow the bootstrap capacitor to recharge.
The boost capacitor refresh threshold varies with the
DRVSET pin setting.
Shutdown and Start-Up
The LTC3777 can be shut down by pulling the RUN pin
low. Pulling RUN below 1.1V shuts down the main control
loop for the controller and most internal circuits, including
the DRVCC and V5 regulators. Releasing RUN allows an
internal 2.5µA current to pull-up the pin and enable the
controller. When RUN is above the accurate threshold of
1.2V, the internal LDO will power up DRVCC. At the same
time, a 6.5µA pull-up current will kick in to provide more
RUN pin hysteresis. The RUN pin may be externally pulled
up or driven directly by logic. The RUN pin can tolerate up
to 150V (absolute maximum), so it can be conveniently
tied to VIN in always-on applications where the controller
is enabled continuously and never shut down. The RUN
Rev A
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15
LTC3777
OPERATION
pin will have no internal pull-up current when externally
driven to a voltage above 4V.
VOUT
VIN
TG1
A
SW1
Soft-Start
The start-up of the controller’s output voltage VOUT is
controlled by the voltage on the SS pin. When the voltage
on the SS pin is less than the 1.2V internal reference,
the LTC3777 regulates the VFB voltage to the SS voltage
instead of the 1.2V reference. This allows the SS pin to
be used to program soft-start by connecting an external
capacitor from the SS pin to SGND. An internal 5µA
pull-up current charges this capacitor, creating a voltage
ramp on the SS pin. As the SS voltage rises linearly from
0V to 1.2V (and beyond), the output voltage VOUT rises
smoothly from zero to its final value. When RUN is pulled
low to disable the controller, or during an overvoltage
event on the VIN input supply or during an overtemperature
shutdown event, or when V5 drops below its undervoltage
lockout threshold of 3.85V, the SS pin is pulled low by
an internal MOSFET. When in undervoltage lockout, the
controller is disabled and the external MOSFETs are held
off.
Certain applications can require the start-up of the
converter into a non-zero load voltage, where residual
charge is stored on the VOUT capacitor at the onset of
converter switching. In order to prevent the VOUT from
discharging under these conditions, the part will be forced
into discontinuous mode of operation until the SS voltage
crosses VFB or 1.32V, whichever is lower.
Power Switch Control
Figure 1 shows a simplified diagram of how the four
power switches are connected to the inductor, VIN, VOUT
and GND. Figure 2 shows the regions of operation for
the LTC3777 as a function of VOUT – VIN or switch duty
cycle, DC. The power switches are properly controlled so
the transfer between regions is continuous. Hysteresis is
added to prevent chattering when transitioning between
regions.
BG1
D
L
TG2
SW2
B
C
BG2
RSENSE
3777 F01
Figure 1. Simplified Diagram of the Output Switches
DCMAX
BOOST
DCMIN
BOOST
DCMAX
BUCK
A ON, B OFF
PWM C, D SWITCHES
BOOST REGION
FOUR SWITCH PWM
BUCK/BOOST REGION
D ON, C OFF
PWM A, B SWITCHES
BUCK REGION
DCMIN
BUCK
3777 F02
Figure 2. Operating Region vs Duty Cycle
Buck Region (VIN >> VOUT)
When VIN is significantly higher than VOUT, the part will run
in the buck region. In this region switch C is always off. At
the start of every cycle, synchronous switch B is turned on
first. Inductor current is sensed when synchronous switch
B is turned on. After the sensed inductor valley current
falls below a reference voltage, which is proportional to
VITH, synchronous switch B is turned off and switch A
is turned on for the remainder of the cycle. Switches A
and B will alternate, behaving like a typical synchronous
buck regulator. The duty cycle of Switch A increases
until the maximum duty cycle of the converter reaches
DC(MAX_BUCK), given by:
1⎞
⎛
DC(MAX,BUCK) = ⎜ 1− ⎟ • 100% = 91.67%
⎝ 12 ⎠
Figure 3 shows the typical buck region waveforms. If VIN
approaches VOUT, the buck-boost region is reached.
Rev A
16
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LTC3777
OPERATION
CLOCK
SWITCH A
SWITCH B
LOW
SWITCH C
HIGH
SWITCH D
IL
3777 F03
Figure 3. Buck Region (VIN >> VOUT)
Buck-Boost Region (VIN ≈ VOUT)
When VIN is close to VOUT, the controller enters the buckboost region. Figure 4 shows the typical waveforms in this
region. At the beginning of a clock cycle, if the controller
starts with B and D on, the controller first operates as if in
the buck region. When ICMP trips, switch B is turned off,
and switch A is turned on. At 120° clock phase, switch C is
turned on. The LTC3777 starts to operate as a boost until
ICMP trips. Then, switch D is turned on for the remainder
of the clock period. If the controller starts with switches
A and C on, the controller first operates as a boost, until
ICMP trips and switch D is turned on. At 120°, switch B is
turned on, making it operate as a buck. Then, ICMP trips,
turning switch B off and switch A on for the remainder of
the clock period.
Boost Region (VIN
VIN(MIN)
2
(
)
• VOUT − VIN(MIN) • 100
f •IOUT(MAX) • %Ripple • VOUT
(
)
VOUT • VIN(MAX) − VOUT • 100
f •IOUT(MAX) • %Ripple • VIN(MAX)
2
H,
H
where:
3777 F10
Figure 10. Phase-Locked Loop Block Diagram
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for the amount of time corresponding to
the phase difference. The voltage on the filter network is
f is operating frequency, Hz
% Ripple is allowable inductor current ripple
VIN(MIN) is minimum input voltage, V
VIN(MAX) is maximum input voltage, V
VOUT is output voltage, V
IOUT(MAX) is maximum output load current, A
For high efficiency, choose an inductor with low core loss,
such as ferrite. Also, the inductor should have low DC
resistance to reduce the I2R losses, and must be able to
handle the peak inductor current without saturating. To
minimize radiated noise, use a toroid, pot core or shielded
bobbin inductor.
Rev A
24
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LTC3777
APPLICATIONS INFORMATION
Inductor Core Selection
Once the inductance value is determined, the type of
inductor must be selected. Core loss is independent of
core size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase
in inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
CIN and COUT Selection
In the boost region, input current is continuous. In the
buck region, input current is discontinuous. In the buck
region, the selection of input capacitor CIN is driven by
the need to filter the input square wave current. Use a low
ESR capacitor sized to handle the maximum RMS current.
For buck operation, the input RMS current is given by:
IRMS ≈ IOUT(MAX) •
VOUT
VIN
•
−1
VIN
VOUT
for a given output ripple voltage. The steady ripple due to
charging and discharging the bulk capacitance is given by:
ΔVRIPPLE(BOOST,CAP) =
(
IOUT(MAX) • VOUT − VIN(MIN)
COUT • VOUT • f
)V
where COUT is the output filter capacitor.
The steady ripple due to the voltage drop across the ESR
is given by:
∆V(BOOST,ESR) = IOUT(MAX,BOOST) • ESR
In buck mode, VOUT ripple is given by:
⎛
⎞
1
ΔVOUT ≤ ΔIL ⎜ ESR +
8 • f • COUT ⎟⎠
⎝
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Aluminum electrolytic and ceramic capacitors are available
in surface mount packages. Ceramic capacitors have
excellent low ESR characteristics but can have a high
voltage coefficient. Bulk capacitors are now available with
low ESR and high ripple current ratings, such as OSCON and
aluminum electrolytics with hybrid conductive polymers.
Power MOSFET Selection and Efficiency
Considerations
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX) / 2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
based on only 2000 hours of life which makes it advisable
to derate the capacitor.
In the boost region, the discontinuous current shifts
from the input to the output, so COUT must be capable
of reducing the output voltage ripple. The effects of ESR
(equivalent series resistance) and the bulk capacitance
must be considered when choosing the right capacitor
The LTC3777 requires four external N-channel power
MOSFETs, two for the top switches (switches A and
D, shown in Figure 1) and two for the bottom switches
(switches B and C, shown in Figure 1). Important
parameters for the power MOSFETs are the breakdown
voltage VBR,DSS, threshold voltage VGS,TH, on-resistance
RDS(ON), reverse transfer capacitance CRSS and maximum
current IDS(MAX).
The peak-to-peak drive levels are set by the DRVCC
voltage. This voltage can range from 6V to 10V depending
on the DRVSET pin setting. Therefore, both logic-level
and standard-level threshold MOSFETs can be used in
Rev A
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25
LTC3777
APPLICATIONS INFORMATION
most applications, depending on the programmed DRVCC
voltage. Pay close attention to the BVDSS specification for
the MOSFETs as well.
The LTC3777’s ability to adjust the gate drive level between
6V to 10V allows an application circuit to be precisely
optimized for efficiency. When adjusting the gate drive level,
the final arbiter is the total input current for the regulator.
If a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
In order to select the power MOSFETs, the power
dissipated by the device must be known. For switch A,
the maximum power dissipation happens in the boost
region, when it remains on all the time. Its maximum
power dissipation at maximum output current is given by:
2
PA,BOOST
⎛V
⎞
= ⎜ OUT •IOUT(MAX) ⎟ • ρτ • RDS(ON)
⎝ VIN
⎠
where ρt is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C, as shown in
Figure 11. For a maximum junction temperature of 125°C,
using a value ρt = 1.5 is reasonable.
ρT NORMALIZED ON-RESISTANCE (Ω)
2.0
PB,BUCK =
VIN VOUT
•IOUT(MAX)2 •
VIN
• RDS(ON)
Switch C operates in the boost region as the control switch.
Its power dissipation at maximum current is given by:
PC,BOOST =
( VOUT
VIN ) VOUT
VIN
•RDS(ON) + k • VOUT 3 •
2
•IOUT(MAX)2 •
IOUT(MAX)
VIN
• CRSS • f
where CRSS is usually specified by the MOSFET
manufacturers. The constant k, which accounts for the
loss caused by reverse recovery current, is inversely
proportional to the gate drive current and has an empirical
value of 1.7.
For switch D, the maximum power dissipation happens
in the boost region, when its duty cycle is higher than
50%. Its maximum power dissipation at maximum output
current is given by:
PD,BOOST
V
= IN
VOUT
2
⎛V
⎞
• ⎜ OUT •IOUT(MAX) ⎟ • ρτ • RDS(ON)
⎝ VIN
⎠
For the same output voltage and current, switch A has the
highest power dissipation and switch B has the lowest
power dissipation unless a short occurs at the output.
1.5
1.0
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
0.5
0
–50
Switch B operates in the buck region as the synchronous
rectifier. Its power dissipation at maximum output current
is given by:
TJ = TA + P • RTH(JA)
50
100
0
JUNCTION TEMPERATURE (°C)
150
3777 F11
Figure 11. Normalized RDS(ON) vs Temperature
The RTH(JA) to be used in the equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the case to the ambient temperature (RTH(JC)). This value
of TJ can then be compared to the original, assumed value
used in the iterative calculation process.
Rev A
26
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LTC3777
APPLICATIONS INFORMATION
Schottky Diode (D1, D2) Selection
The Schottky diodes, D1 and D2, shown in the Block
Diagram, conduct during the dead time between the
conduction of the power MOSFET switches. They are
intended to prevent the body diode of synchronous
switches B and D from turning on and storing charge
during the dead time. In particular, D2 significantly
reduces reverse recovery current between switch D
turn-off and switch C turn-on, which improves converter
efficiency and reduces switch C voltage stress. In order
for the diode to be effective, the inductance between it
and the synchronous switch must be as small as possible,
mandating that these components be placed adjacently.
Setting Output Voltage
The LTC3777 output voltage is set by two external
feedback resistive dividers carefully placed across the
output, as shown in Figure 12. The regulated output
voltage is determined by:
VOUT = 1.2V • (1 + RB /RA)
To improve the frequency response, a feed forward
capacitor, CFF, may be used. Great care should be taken
to route the VFB line away from noise sources, such as
the inductor or the SW line.
DRVCC and V5 LDOs. In this state the LTC3777 draws only
40μA of quiescent current. Releasing the RUN pin allows
an internal 2.5µA current to pull-up the pin and enable the
controller. The RUN comparator itself has about 100mV
of hysteresis. When the voltage on the RUN pin exceeds
1.2V, the current sourced into the RUN pin is switched
from 2.5µA to 6.5µA current. The user can therefore
program both the rising threshold and the amount of
hysteresis using an external resistive divider.
The RUN pin is high impedance above 3V and must be
externally pulled up/down or driven directly by logic, as
shown in Figure 13. The RUN pin can tolerate up to 150V
(absolute maximum), so it can be conveniently tied to VIN
in always-on applications where the controller is enabled
continuously and never shut down.
The RUN and VINOV pins can alternatively be configured as
undervoltage (UVLO) and overvoltage (OVLO) lockouts on
the VIN supply with a resistor divider from VIN to ground. A
simple resistor divider can be used as shown in Figure 14
to meet specific VIN voltage requirements. One can
program additional hysteresis for the RUN comparator
by adjusting the values of the resistive divider.
VIN
SUPPLY
LTC3777
RB
4.7M
LTC3777
RUN
VOUT
LTC3777
RUN
CFF
3777 F13
VFB
Figure 13. RUN Pin Interface to Logic
RA
3777 F12
Figure 12. Setting Output Voltage
VIN
R3
RUN Pin and Overvoltage /Undervoltage Lockout
The LTC3777 is enabled using the RUN pin. It has a rising
threshold of 1.2V with 100mV of hysteresis. Pulling the
RUN pin below 1.1V shuts down the main control loop
for the controller and most internal circuits, including the
RUN
R4
LTC3777
VINOV
R5
3777 F14
Figure 14. Adjustable UV and OV Lockout
Rev A
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27
LTC3777
APPLICATIONS INFORMATION
The current that flows through the R3-R4-R5 divider will
directly add to the shutdown and active current of the
LTC3777, and care should be taken to minimize the impact
of this current on the overall efficiency of the application
circuit. Resistor values in the megohm range may be
required to keep the impact on quiescent shutdown
current low. To pick resistor values, the sum total of R3
+ R4 + R5 (RTOTAL) should be chosen first based on the
allowable DC current that can be drawn from VIN.
The individual values of R3, R4 and R5 can then be
calculated from the following equations:
⎛
⎞
1.2V
R5 = RTOTAL • ⎜
⎝ Rising VIN OVLO Threshold ⎟⎠
⎛
⎞
1.2V
− R5
R4 = RTOTAL • ⎜
⎝ Rising VIN UVLO Threshold ⎟⎠
R3 = RTOTAL − R4 − R5
For applications that do not need a precise external OVLO,
the VINOV pin should be tied directly to ground. The RUN
pin in this type of application can be used as an external
UVLO using the following equations with R5 = 0Ω.
⎛ R3 ⎞
VIN(ON) = 1.2V ⎜ 1+ ⎟ − 2.5µ • R3
⎝ R4 ⎠
⎛ R3 ⎞
VIN(OFF) = 1.1V ⎜ 1+ ⎟ − 6.5µ • R3
⎝ R4 ⎠
Similarly, for applications that do not require a precise
UVLO, the RUN pin can be tied to VIN. In this configuration,
the UVLO threshold is limited to the internal VIN UVLO
thresholds as shown in the Electrical Characteristics table.
The resistor values for the OVLO can be computed using
the previous equations with R3 = 0Ω.
Be aware that the VINOV pin cannot be allowed to exceed
its absolute maximum rating of 6V. To keep the voltage on
the VINOV pin from exceeding 6V, the following relation
should be satisfied:
R5
⎛
⎞
VIN(MAX) • ⎜
< 6V
⎝ R3 + R4 + R5 ⎟⎠
Soft-Start
The start-up of VOUT is controlled by the voltage on the SS
pin. If its RUN pin voltage is below 1.1V the controller is in
the shutdown state; its SS pin is actively pulled to ground
in this shutdown state. If the RUN pin voltage is above
1.2V, the controller powers up. A soft-start current of
5μA then starts to charge the SS soft-start capacitor. Note
that soft-start is achieved not by limiting the maximum
output current of the controller but by controlling the
output ramp voltage according to the ramp rate on the
SS pin. When the voltage on the SS pin is less than the
internal 1.2V reference, the LTC3777 regulates the VFB pin
voltage to the voltage on the SS pin instead of the internal
reference. Current foldback is disabled during this phase.
The soft-start range is defined to be the voltage range
from 0V to 1.2V on the SS pin. The total soft-start time
can be calculated as:
⎛ 1.2V ⎞
tSS = CSS • ⎜
⎝ 5µA ⎟⎠
DRVCC Regulator
In addition to the switching bias supply, the LTC3777
features two separate low dropout linear regulators (LDO)
that can supply power at the DRVCC pin. The internal VIN
LDO uses an internal P-channel pass device between the
VIN and DRVCC pins. The internal EXTVCC LDO uses an
internal P-channel pass device between the EXTVCC and
DRVCC pins.
The DRVCC supply is regulated between 6V to 10V,
depending on the DRVSET pin setting. The internal VIN
and EXTVCC LDOs can supply a peak current of at least
50mA. The DRVCC pin must be bypassed to ground with
a minimum of 4.7μF ceramic capacitor. Good bypassing is
needed to supply the high transient currents required by
the MOSFET gate drivers. The DRVSET pin programs the
DRVCC supply voltage and selects the appropriate EXTVCC
switchover threshold voltages as shown in the Electrical
Characteristics table. The DRVSET pin has five logic level
states. When DRVSET is either grounded, floated or tied to
Rev A
28
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LTC3777
APPLICATIONS INFORMATION
V5, the typical value for the DRVCC voltage will be 6V, 8V
and 10V respectively. Use the 10V setting with careful PCB
layout. This is because any overshoot between BOOST
and SW would exceed the absolute maximum voltage of
11V for the floating driver. Set DRVSET to one-fourth of
V5 and three-fourths of V5 for 7V and 9V DRVCC voltages.
Please note that the DRVSET pin has an internal 200k
pull-down to SGND and a 200k pull-up to V5. The EXTVCC
turn on threshold is the selected DRVCC regulation voltage
minus 500mV. The turn off threshold is 500mV below the
turn on threshold.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the
maximum junction temperature rating for the LTC3777 to
be exceeded. The DRVCC current, which is dominated by
the gate charge current, may be supplied by the VIN LDO,
or the EXTVCC LDO. When the voltage on the EXTVCC pin
is less than its switchover threshold (as determined by the
DRVSET pin), the VIN LDO is enabled. Power dissipation
in this case is highest and is equal to VIN • IDRVCC. This
power is dissipated inside the IC. The gate charge current
is dependent on operating frequency as discussed in the
Efficiency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 2 of the Electrical Characteristics
table. For example, if DRVCC is set to 6V, the DRVCC current
is limited to less than 38mA from a 40V supply when not
using the EXTVCC LDO at a 70°C ambient temperature:
TJ = 70°C + (38mA)(40V)(36°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the VIN supply current must be checked while
operating in forced continuous mode (MODE = SGND) at
maximum VIN.
When the voltage applied to EXTVCC rises above its
switchover threshold, the VIN LDO is turned off and the
EXTVCC LDO is enabled. The EXTVCC LDO remains on as
long as the voltage applied to EXTVCC remains above the
switchover threshold minus the comparator hysteresis.
The EXTVCC LDO attempts to regulate the DRVCC voltage
to the voltage as programmed by the DRVSET pin, so
while EXTVCC is less than this voltage, the LDO is in
dropout and the DRVCC voltage is approximately equal to
EXTVCC. When EXTVCC is greater than the programmed
voltage, up to an absolute maximum of 36V, DRVCC is
regulated to the programmed voltage.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from the LTC3777’s switching
regulator output (5.7V ≤ VOUT ≤ 36V) during normal
operation and from the VIN LDO when the output is out
of regulation (e.g., start-up, short-circuit).
Significant efficiency and thermal gains can be realized by
powering DRVCC from the output, since the VIN current
resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
For 5.5V to 36V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT. Tying the EXTVCC pin
to a 12V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + 38mA • (12V) ( 36°C / W ) = 86°C
While using the EXTVCC LDO there is an VIN under voltage
detection circuit that disables the EXTVCC LDO if the VIN
voltage is less that the DRVCC voltage that is set by the
DRVSET pin.
For applications where the minimum VIN voltage of
LTC3777 needs to be less than 4.5V, the EXTVCC pin can
be used to power the VIN of LTC3777. The VIN under
voltage detection circuit is disabled when DRVSET is set
to three-fourths of V5, for 9V DRVCC voltage. Under this
condition the DRVCC voltage can be higher than the VIN
of LTC3777 and an external blocking diode should be
connected from the VIN pin of LTC3777 to the external
VIN supply, to avoid back feeding the VIN supply.
The following list summarizes the four possible
connections for EXTVCC:
1. EXTVCC grounded. This will cause DRVCC to be
powered from the internal VIN LDO resulting in an
efficiency penalty of up to 10% at high input voltages.
2. EXTVCC connected directly to the regulator output.
This is the normal connection for a 5.5V to 36V
regulator and provides the highest efficiency.
Rev A
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29
LTC3777
APPLICATIONS INFORMATION
3. EXTVCC connected to BVOUT the integrated switching
bias supply output.
2. It can also be used as a standalone bias to power
other supply rails in the system.
V5 Regulator
For most applications, the design process to configure the
switching bias supply is simple, summarized as follows:
An additional P-channel LDO supplies power at the V5
pin from the DRVCC pin. Whereas DRVCC powers the
gate drivers, V5 powers much of the LTC3777’s internal
circuitry. The V5 LDO regulates the voltage at the V5 pin
to 5.5V when DRVCC is at least 6V. The LDO can supply
a peak current of 20mA and must be bypassed to ground
with a minimum of 4.7μF ceramic capacitor or low
ESR electrolytic capacitor. No matter what type of bulk
capacitor is used, an additional 0.1μF ceramic capacitor
placed directly adjacent to the V5 and SGND pins is highly
recommended. V5 is also used as a pull-up to bias other
pins, such as MODE, DRVSET and SS.
Integrated Switching Bias Supply
The integrated switching bias is a 150V high efficiency
step-down regulator with internal high side and
synchronous power switches that can supply up to 85mA
load current. The 150V switching bias draws only 12µA
typical DC supply current while maintaining a regulated
output voltage at no load. Using the integrated bias for
high VIN application increases the overall efficiency of the
system, and reduces power dissipation.
1. In Table 1 find the row that has the desired input
voltage and output voltage.
2. Apply the recommended CIN, COUT, L, R1 and R2.
3. Connect the BVOUT to the EXTVCC pin to bias the buckboost controller.
The output voltage is set by an external resistive divider
according to the following equation:
⎛ R1⎞
BVOUT = 0.8V • ⎜ 1+ ⎟
⎝ R2 ⎠
The resistive divider allows the BVFB pin to sense a fraction
of the output voltage as shown in Figure 15. The output
voltage can range from 0.8V to VIN. Be careful to keep the
divider resistors very close to the BVFB pin to minimize
noise pick-up on the sensitive BVFB trace.
The switching bias supply of LTC3777 can be used for
the following purposes:
1. If the output voltage of the buck-boost controller
is higher than 36V, which exceeds the absolute
maximum voltage rating of the EXTVCC pin, then
the integrated switching bias supply can be used to
provide a 12V bias to power the buck-boost controller.
BVOUT
LTC3777
BVFB
0.8V
R1
R2
3777 F15
Figure 15. Setting the Switching Bias Supply
Output Voltage
Table 1. Switching Bias Supply Recommended Component Values and Configuration
BVIN
BVOUT
CIN
COUT
L
R1
R2
12V to 150V
12V
1µF TDK C5750X7R2E105K
2 × 22µF AVX 12103D226KAT2A
220µH SUMIDA CDRH105RNP-221NC
715k
51.1k
5V to 150V
5V
1µF TDK C5750X7R2E105K
10µF TDK C3216X7R1C106M
1000µH TDK SLF12555T-102MR34
422k
80.6k
4V to 150V
3.3V
1µF TDK C5750X7R2E105K
22µF AVX 12103D226KAT2A
150µH Coilcraft LPS6235-154ML
309k
97.6k
Rev A
30
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LTC3777
APPLICATIONS INFORMATION
To minimize the no-load supply current, resistor values in
the megohm range may be used; however, large resistor
values should be used with caution. The feedback divider
is the only load current when in shutdown. If PCB leakage
current to the output node or switch node exceeds the load
current, the output voltage will be pulled up. In normal
operation, this is generally a minor concern since the load
current is much greater than the leakage.
The switching bias supply has a low power shutdown
mode controlled by the BRUN pin. Pulling the BRUN pin
below 0.7V puts the switching bias supply into a low
quiescent current shutdown mode (IQ ~ 1.4µA). When
the BRUN pin is greater than 1.21V, switching is enabled.
Figure 16 shows examples of configurations for driving
the BRUN pin from logic.
The BRUN and BOV pins can alternatively be configured
as precise undervoltage (UVLO) and overvoltage (OVLO)
lockouts on the BVIN supply with a resistive divider from
BVIN to ground. A simple resistive divider can be used
as shown in Figure 17 to meet specific BVIN voltage
requirements.
BVIN
SUPPLY
4.7M
LTC3777
BRUN
LTC3777
BRUN
3777 F16
Figure 16. BRUN Pin Interface to Logic
R3
BRUN
1.21V
Rising BVIN OVLO Threshold
R4 = R TOTAL •
1.21V
–R5
Rising BVIN UVLO Threshold
R3 = R TOTAL –R5 –R4
For applications that do not need a precise external OVLO,
the BOV pin should be tied directly to ground. The BRUN
pin in this type of application can be used as an external
UVLO using the previous equations with R5 = 0Ω.
Similarly, for applications that do not require a precise
UVLO, the BRUN pin can be tied to BVIN. In this
configuration, the UVLO threshold is limited to the
internal BVIN UVLO thresholds as shown in the Electrical
Characteristics table. The resistor values for the BOV can
be computed using the previous equations with R3 = 0Ω.
LTC3777
BOV
R5
R5 = R TOTAL •
Be aware that the BOV pin cannot be allowed to exceed
its absolute maximum rating of 6V. To keep the voltage
on the BOV pin from exceeding 6V, the following relation
should be satisfied:
BVIN
R4
The current that flows through the R3-R4-R5 divider
will directly add to the shutdown, sleep, and active
current of the switching bias supply, and care should
be taken to minimize the impact of this current on the
overall efficiency of the application circuit. Resistor
values in the megohm range may be required to keep
the impact on quiescent shutdown and sleep currents
low. To pick resistor values, the sum total of R3 + R4
+ R5 (RTOTAL) should be chosen first based on the
allowable DC current that can be drawn from BVIN.
The individual values of R3, R4 and R5 can then be
calculated from the following equations:
3777 F17
R5
⎛
⎞
BVIN(MAX) • ⎜
< 6V
⎝ R3+R4+R5 ⎟⎠
Figure 17. Switching Bias Supply Adjustable UV and OV Lockout
Rev A
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31
LTC3777
APPLICATIONS INFORMATION
Pre-Biased Output Start-Up
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTC3777 can safely power up into a
pre-biased output without discharging it.
If the voltage on the SS pin is lower than VFB, to prevent
pulling current from the output to the input, the LTC3777
forces the part into discontinuous mode of operation
irrespective of the status of the MODE pin. If VFB is
>1.12V, or when the SS voltage crosses VFB or 1.32V,
whichever event happens first, then the MODE pin setting
determines the mode of operation.
Topside MOSFET Driver Supply
In the Block Diagram, the external bootstrap capacitors
CA and CB, connected to the BOOST1 and BOOST2 pins,
supply the gate drive voltage for the topside MOSFET
switches A and D. When the top switch A turns on, the
switch node SW1 rises to VIN and the BOOST1 pin rises
to approximately VIN + DRVCC. When the bottom switch
B turns on, the switch node SW1 is low and the boost
capacitor CA is charged through DA from DRVCC. When
the top switch D turns on, the switch node SW2 rises to
VOUT and the BOOST2 pin rises to approximately VOUT +
DRVCC. When the bottom switch C turns on, switch node
SW2 is low and the boost capacitor CB is charged through
DB from DRVCC. The boost capacitors CA and CB need to
store about 100 times the gate charge required by the top
switches A and D. In most applications, a 0.1µF to 0.47µF,
X5R or X7R dielectric capacitor is adequate.
Fault Conditions: Current Limit and Current Foldback
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the boost region, maximum sense voltage and the sense
resistance determine the maximum allowed inductor peak
current, which is:
IL(MAX,BOOST) =
140mV
R SENSE
In the buck region, maximum sense voltage and the sense
resistance determine the maximum allowed inductor
valley current, which is:
IL(MAX,BUCK) =
90mV
R SENSE
To further limit current in the event of a short circuit to
ground, the LTC3777 includes foldback current limiting.
If the output falls by more than 50%, then the maximum
sense voltage is progressively lowered to about one-third
of its full value.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. a e the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3777 circuits: 1) IC VIN current, 2) MOSFET
driver current, 3) I2R losses, 4) topside MOSFET transition
losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table. VIN current typically
results in a small (1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC.
1. Are the signal and power grounds kept separate?
The combined IC signal ground pin and the ground
return of CDRVCC must return to the combined COUT
(–) terminals. The path formed by the top N-channel
MOSFET, bottom N-channel MOSFET and the CIN
capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should
be connected as close as possible to the (–) terminals
of the input capacitor by placing the capacitors next
to each other.
2. Does the LTC3777 VFB pin’s resistive divider connect
to the (+) terminal of COUT? The resistive divider must
be connected between the (+) terminal of COUT and
signal ground. The feedback resistor connections
should not be along the high current input feeds from
the input capacitor(s).
3. Are the SENSEN and SENSEP leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing
with Kelvin connections at the SENSE resistor.
4. Is the DRVCC and decoupling capacitor connected
close to the IC, between the DRVCC and the ground
pin? This capacitor carries the MOSFET drivers’
current peaks.
5. Keep the SW, TG, and BOOST nodes away from
sensitive small-signal nodes. All of these nodes have
very large and fast moving signals and therefore
should be kept on the output side of the LTC3777
and occupy minimum PC trace area.
6. The path formed by switch A, switch B, D1 and the
CIN capacitor should have short leads and PC trace
lengths. The path formed by switch C, switch D, D2
and the COUT capacitor also should have short leads
and PC trace lengths.
7. Use a modified star ground technique: a low
impedance, large copper area central grounding point
on the same side of the PC board as the input and
output capacitors with tie-ins for the bottom of the
DRVCC decoupling capacitor, the bottom of the voltage
feedback resistive divider and the GND pin of the IC.
Design Example
VIN = 6V to 100V
VOUT = 12V
IOUT(MAX) = 5A
f = 200kHz
Maximum ambient temperature = 60°C
Rev A
34
For more information www.analog.com
LTC3777
APPLICATIONS INFORMATION
Set the frequency at 200kHz by applying 1.11V on the
FREQ pin (see Figure 9). The 20µA current flowing out
of the FREQ pin will give 1.11V across a 55.6k resistor
to GND. The inductance value is chosen first based on a
30% ripple current assumption. In the buck region, the
ripple current is:
∆IL,BUCK =
VOUT
f •L
IRIPPLE,BUCK =
⎛
V ⎞
• ⎜ 1– OUT ⎟
VIN ⎠
⎝
∆IL,BUCK • 100
IOUT
%
The highest value of ripple current occurs at the maximum
input voltage. In the boost region, the ripple current is:
∆IL,BOOST =
VIN ⎛
V ⎞
• ⎜ 1– IN ⎟
f •L ⎝
VOUT ⎠
IRIPPLE,BOOST =
∆I L,BOOST • 100
I IN
Select RB as 110k. Both RA and RB should have a tolerance
of no more than 1%.
Selecting MOSFET Switches
The MOSFETs are selected based on voltage rating and
RDS(ON) value. It is important to ensure that the part is
specified for operation with the available gate voltage
amplitude. In this case, the amplitude is 10V and MOSFETs
with an RDS(ON) value specified at VGS = 4.5V can be used.
Select QA and QB. With 100V maximum input voltage
MOSFETs with a rating of at least 150V are used. As we do
not yet know the actual thermal resistance (circuit board
design and airflow have a major impact) we assume that
the MOSFET thermal resistance from junction to ambient
is 50°C/W.
If we design for a maximum junction temperature, TJ(MAX)
= 125°C, the maximum RDS(ON) value can be calculated.
First, calculate the maximum power dissipation:
%
⎛ TJ(MAX) − TA(MAX) ⎞
PD(MAX) = ⎜
⎟
R(j−a)
⎝
⎠
The highest value of ripple current occurs at VIN = VOUT/2.
A 15µH inductor will produce 10% ripple in the boost
region (VIN = 6V) and 70% ripple in the buck region (VIN
= 100V).
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances.
RSENSE =
2 • 140mV • VIN(MIN)
2 •IOUT(MAX,BOOST) • VOUT + ∆IL,BOOST • VIN(MIN)
= 13.3mΩ
RB =
VOUT • RA
– RA
1.2
(125 − 60)
= 1.3W
50
The maximum dissipation in QA occurs at minimum input
voltage when the circuit operates in the boost region and
QA is on continuously. The input current is then:
VOUT • IOUT(MAX)
, or 10A
VIN(MIN)
We calculate a maximum value for RDS(ON):
RDS(ON) (125°C) <
Adding an additional 30% margin, choose RSENSE to be
13.3mΩ/1.3 = 10mΩ.
Output voltage is 12V. Select RA as 12.1k. RB is:
PD(MAX) =
RDS(ON) (125°C) <
PD(MAX)
IIN(MAX) 2
1.3W
(10A)2
= 0.013Ω
Rev A
For more information www.analog.com
35
LTC3777
APPLICATIONS INFORMATION
The Infineon BSC360N15NS3G has a typical RDS(ON)
of 0.036Ω at VGS = 10V. Two MOSFETs can be used in
parallel to handle the power dissipation.
The maximum dissipation in QB occurs at maximum input
voltage when the circuit is operating in the buck region.
The dissipation is:
P B,BUCK =
VIN − VOUT
• IOUT(MAX) 2 • ρτ • RDS(ON)
VIN
R DS(ON)(125°C) <
1.3W
= 0.059Ω
⎛ 100V − 12V ⎞
2
⎜⎝
⎟ • (5A)
100V ⎠
The Infineon BSC190N15NS3G with a typical RDS(ON) of
19mΩ can be used.
Select QC and QD. With 12V output voltage we need
MOSFETs with 20V or higher rating.
The highest dissipation occurs at minimum input voltage
when the inductor current is highest. For switch QC the
dissipation is:
PC,BOOST =
(VOUT − VIN )VOUT
VIN 2
IOUT(MAX)
VIN
P D,BOOST
⎛V
⎞
V
= IN • ⎜ OUT • IOUT(MAX) ⎟
VOUT ⎝ VIN
⎠
2
• ρτ • RDS(ON)
BSC050NE2LS is a possible choice for QC and QD. The
calculated power loss at 6V input voltage is then 0.392W
for QC and 0.375W for QD.
CIN is chosen to filter the square current in the buck
region. In this mode, the maximum input current peak is:
70% ⎞
⎛
IIN,PEAK(MAX,BUCK) = 5A • ⎜ 1+
= 6.75A
⎝ 2 • 100% ⎟⎠
A low ESR (10mΩ) capacitor is selected. Input voltage
ripple is 67.5mV (assuming ESR dominates the ripple).
COUT is chosen to filter the square current in the boost
region. In this mode, the maximum output current peak is:
IOUT,PEAK(MAX,BOOST) =
12
10% ⎞
⎛
• 5 • ⎜ 1+
= 10.5A
⎝ 2 • 100% ⎟⎠
6
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 53mV (assuming ESR
dominates the ripple).
• IOUT(MAX) 2 • ρτ • RDS(ON)
+ k • VOUT 3 •
The dissipation in switch QD is:
• CRSS • f
where CRSS is usually specified by the MOSFET
manufacturers. The constant k, which accounts for the
loss caused by reverse recovery current, is inversely
proportional to the gate drive current and has an empirical
value of 1.7.
Rev A
36
For more information www.analog.com
BVOUT
3.3V
85mA
10µF
125V
For more information www.analog.com
5Ω
800k
VOUT
VIN
0.1µF
2.2µF
100k
2.5M
150µH
1µF
121k
0.1µF
1k
56.2k
10k
1µF
1.21k
10µF
PLLIN
MODE
FREQ
SS
V5
PGOOD
RUN
EXTVCC
BGND
BVFB
BSW
BRUN
BOV
BVIN
VINOV
DRVCC
VIN
VINSNS
LTC3777
D1
D2
ITH
VFB
VOUTSNS
IAVGSNSN
IAVGSNSP
TG2
SW2
BOOST2
BG2
PGND
SENSEN
SGND
SENSEP
BG1
TG1
SW1
BOOST1
1k
33nF
3.32k
0.22µF
4.7µF
100pF
0.22µF
100Ω
220pF
100Ω
12.1k
100Ω
MBOTC
MTOPD
R1
10mΩ
15µH
100Ω
MBOTB
MTOPA
×2
22µF
×3
25V
8mΩ
3777 F18
110k
Figure 18. 97% Efficient 12V/5A Output Buck-Boost Converter with an Independent Always on 3.3V/ 85mA Output Switching Bias Supply
22µF
6.3V
1µF
×3
200V
PINS NOT USED IN THIS
CIRCUIT: BFBO, BISET, DRVSET
D1, D2: DFLS1200-7
MTOPA: BSC360N15NS3 G
MBOTB: BSC190N15NS3 G
MTOPD: BSC050NE2LS
MBOTC: BSC050NE2LS
VIN
6V TO 100V
270µF
25V
VOUT
12V
5A
LTC3777
APPLICATIONS INFORMATION
Rev A
37
LTC3777
PACKAGE DESCRIPTION
LXE Package
48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)
(Reference LTC DWG #05-08-1832 Rev D)
7.15 – 7.25
5.50 REF
1
48
37
36
0.50 BSC
C0.30
5.50 REF
7.15 – 7.25
0.20 – 0.30
3.60 ±0.05
3.60 ±0.05
PACKAGE OUTLINE
24
XXYY
LTCXXXX
LX-ES
Q_ _ _ _ _ _
e3
12
13
25
COMPONENT
PIN “A1”
1.30 MIN
TRAY PIN 1
BEVEL
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PACKAGE IN TRAY LOADING ORIENTATION
9.00 BSC
7.00 BSC
48
3.60 ±0.10
37
SEE NOTE: 3
1
48
37
36
36
1
C0.30
9.00 BSC
7.00 BSC
3.60 ±0.10
A
A
12
25
25
12
C0.30 – 0.50
13
24
13
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)
24
11° – 13°
R0.08 – 0.20
1.60
1.35 – 1.45 MAX
GAUGE PLANE
0.25
0° – 7°
LXE48 LQFP 0416 REV D
11° – 13°
0.09 – 0.20
1.00 REF
0.50
BSC
0.17 – 0.27
0.05 – 0.15
SIDE VIEW
0.45 – 0.75
SECTION A – A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND ON ANY
SIDE OF EXPOSED PAD, MAX 0.50mm (20 MILS) AT CORNER OF EXPOSED
PAD, IF PRESENT
3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
4. DRAWING IS NOT TO SCALE
Rev A
38
For more information www.analog.com
LTC3777
REVISION HISTORY
REV
DATE
DESCRIPTION
A
10/18
Changed Electrical Characteristics from VIN to BVIN
PAGE NUMBER
5
Added references to Note 9
5
Clarified PB,BUCK and PC,BOOST functions
25
Rev A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is
granted
implication orwww.analog.com
otherwise under any patent or patent rights of Analog Devices.
For
morebyinformation
39
LTC3777
TYPICAL APPLICATION
VIN
16V TO 120V
10µF
×2
125V
D2
1µF
×5
200V
D1
1k
DRVCC
10µF
133k
MTOPA
×2
BOOST1
VINOV
1.21k
TG1
BG1
BRUN
BOV
M BOTB
SENSEN
715k
0.22µF
EXTVCC
SW2
TG2
1µF
RUN
PGOOD
100k
PINS NOT USED IN THIS
CIRCUIT: BFBO, BISET, DRVSET
IAVGSNSP
0.1µF
100Ω
12.1k
10k
MODE
PLLIN
100Ω
1k
VOUTSNS
VFB
ITH
SS
FREQ
56.2k
4.7µF
IAVGSNSN
V5
2.2µF
475k
BG2
BOOST2
BGND
10k
R1
4mΩ
100Ω
PGND
BVFB
51.1k
220pF
SGND
BSW
M BOTC
100Ω
SENSEP
220µH
D1, D2: DFLS1200-7
MTOPA: BSC110N15NS5
MBOTB: BSC093N15NS5
MTOPD: BSC028N06NS
MBOTC: BSC066N06NS
56µF
63V
SW1
1µF
22µF
×2
25V
M TOPD
15µH
0.22µF
LTC3777
BVIN
BVOUT
12V
85mA
10µF
×3
50V
VIN
0.1µF
VOUT
48V
10A
4mΩ
VINSNS
5Ω
100pF
10nF
3777 TA02
Figure 19. 99% Efficient 480W, 48V Output Buck-Boost Converter with Integrated Switching Bias Supply
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC3779
150V VIN and VOUT Synchronous 4-Switch Buck-Boost
Controller
4.5V ≤ VIN ≤ 150V, 1.2V ≤ VOUT ≤ 150V, Up to 99% Efficiency Drives LogicLevel or STD Threshold MOSFETs, TSSOP-38
LT®8705A
80V VIN and VOUT Synchronous 4-Switch Buck-Boost
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2.8V ≤ VIN ≤ 80V, Input and Output Current Monitor, 5mm × 7mm QFN-38
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60V Low IQ Synchronous Boost+Buck Controller Low EMI 4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, Boost VOUT Up to 60V,
and Low Input/Output Ripple
0.8V ≤ Buck VOUT ≤ 60V, IQ = 29µA, 5mm × 5mm QFN-32
LTC3899
60V, Triple Output, Buck/Buck/Boost Synchronous
Controller with 29µA Burst Mode IQ
4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, Buck VOUT
Range: 0.8V to 60V, Boost VOUT Up to 60V
LTM®8056
58V Buck-Boost μModule Regulator, Adjustable Input and
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5V ≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V 15mm × 15mm × 4.92mm BGA Package
LTC3895/
LTC7801
150V Low IQ, Synchronous Step-Down DC/DC Controller
with 100% Duty Cycle
4V ≤ VIN ≤ 140V, 150V Absolute Maximum, PLL Fixed Frequency 50kHz to
900kHz, 0.8V ≤ VOUT ≤ 60V, Adjustable 5V to 10V Gate Drive, IQ = 40µA
LTC3871
Bidirectional Multiphase DC/DC Synchronous Buck or
Boost On-Demand Controller
VIN/VOUT Up to 100V, Ideal for High Power 48V/12V Automotive Battery
Applications
LTC3638
140V High Efficiency 250mA Step-Down Regulator
Integrated Power MOSFETs, 4V ≤ VIN ≤ 140V, 0.8V ≤ VOUT ≤ VIN, IQ = 12µA,
MSOP-16(12)
LTC7103
105V, 2.3A Low EMI Synchronous Step-Down Regulator
4.4V ≤ VIN ≤ 105V, 1V ≤ VOUT ≤ VIN, IQ = 2µA Fixed Frequency 200kHz to
2MHz, 5mm × 6mm QFN
Rev A
40
10/18
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