LTC6801
Independent Multicell
Battery Stack Fault Monitor
FEATURES
DESCRIPTION
Qualified for Automotive Applications
nn Monitors Up to 12 Li-Ion Cells in Series (60V Max)
nn Stackable Architecture Enables > 1000V Systems
nn 1% Maximum Overvoltage Detection Level Error
nn Adjustable Overvoltage and Undervoltage Detection
nn Self Test Features Guarantee Accuracy
nn Robust Fault Detection Using Differential Signals
nn Simple Pin-Strapped Configuration Allows Battery
Monitoring without a Microcontroller
nn 15.5ms to Monitor All Cells in a System
nn Programmable Response Time
nn Two Temperature Monitor Inputs
nn Low Power Idle Mode
nn 36-Lead SSOP Package
The LTC®6801 is a multicell battery monitoring IC incorporating a 12-bit ADC, a precision voltage reference, sampled comparator, and a high voltage input multiplexer. The
LTC6801 can monitor as many as 12 series connected
battery cells for overvoltage, undervoltage, and overtemperature conditions, indicating whether the cells are
within specified parameters. The LTC6801 generates a
clock output when no fault conditions exist. Differential
clocking provides high noise immunity and ensures that
battery stack fault conditions cannot be hidden by frozen
bits or short circuit conditions.
nn
APPLICATIONS
Redundant Battery Monitor
Hybrid Electric Vehicles
nn Battery Backup Systems
nn Power Systems Using Multiple Battery Cells
nn
nn
All registered trademarks and trademarks are the property of their respective owners.
Each LTC6801 can operate with a battery stack voltage up
to 60V and multiple LTC6801 devices can be stacked to
monitor each individual cell in a long battery string. When
multiple devices are stacked, the status signal of each
LTC6801 can be daisy-chained, without opto-couplers or
isolators, providing a single status output for the entire
battery string.
The LTC6801 is configurable by external pin strapping.
Adjustable overvoltage and undervoltage thresholds support various Li-Ion chemistries. Selectable measurement
times allow users to save power.
BLOCK DIAGRAM
2
3
12
13
14
0V Detection Level Error
LTC6801
1 V+
1.0
0.6
C11
0.4
ADC
MUX
C2
12
CONTROL
LOGIC
“CELLS GOOD”
C1
ENABLE
INPUT
ISOLATION
VTEMP1
VTEMP2
15
16
VREF
17
REFERENCE
CLOCK SIGNAL
INPUT ENABLES
THE LTC6801
STATUS
OUTPUT
0.2
0
–0.2
–0.6
–0.8
–1.0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
22
6801 TA01a
5 TYPICAL UNITS
–0.4
20
V–
NEXT LOWER
CELL PACK
+
V = 43.2V
0.8 OV = 4.116V
C12
ERROR (%)
NEXT HIGHER
CELL PACK
6801 TA01b
CLOCK SIGNAL
OUTPUT INDICATES
SYSTEM “OK”
NTC
NTC
Rev. D
Document Feedback
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1
LTC6801
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Total Supply Voltage (V+ to V–)..................................60V
Input Voltage (Relative to V–)
C1............................................................. –0.3V to 9V
C12............................................V+ –0.3V to V+ + 0.3V
All Other Pins (Not C Inputs).................... –0.3V to 7V
Voltage Between Inputs
Cn to Cn-1*............................................... –0.3V to 9V
C12 to C8................................................ –0.3V to 25V
C8 to C4.................................................. –0.3V to 25V
C4 to V–.................................................. –0.3V to 25V
Operating Temperature Range
LTC6801I..............................................–40°C to 85°C
LTC6801H........................................... –40°C to 125°C
Specified Temperature Range
LTC6801I..............................................–40°C to 85°C
LTC6801H........................................... –40°C to 125°C
Junction Temperature............................................ 150°C
Storage Temperature Range................... –65°C to 150°C
V+
1
36 OV1
C12
2
35 OV0
C11
3
34 UV1
C10
4
33 UV0
C9
5
32 HYST
C8
6
31 CC1
C7
7
30 CC0
C6
8
29 SLT
C5
9
28 SLTOK
C4 10
27 DC
C3 11
26 EOUT
C2 12
25 EOUT
C1 13
24 SIN
V– 14
23 SIN
VTEMP1 15
22 SOUT
VTEMP2 16
21 SOUT
VREF 17
20 EIN
VREG 18
19 EIN
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 70°C/W
*n = 2 to 12
ORDER INFORMATION
TUBE
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6801IG#PBF
LTC6801IG#TRPBF
LTC6801G
36-Lead Plastic SSOP
–40°C to 85°C
LTC6801IG#3ZZPBF
LTC6801IG#3ZZTRPBF
LTC6801G
36-Lead Plastic SSOP
–40°C to 85°C
LTC6801HG#PBF
LTC6801HG#TRPBF
LTC6801G
36-Lead Plastic SSOP
–40°C to 125°C
LTC6801HG#3ZZPBF
LTC6801HG#3ZZTRPBF
LTC6801G
36-Lead Plastic SSOP
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Versions of the LTC6801 models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications.
These models are available with #WTRPBF, #WPBF or #ZZPBF suffix and are listed in ADI’s ARPL.
Note that these automotive models may have specifications that differ from the commercial models; therefore designers should review the Electrical
Characteristics section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact
your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
2
Rev. D
For more information www.analog.com
LTC6801
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, V+ = 43.2V, V– = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Specifications
VERR
Overvoltage (OV) or Undervoltage (UV)
Detection Level Error
(Note 2)
2.106V ≤ VCELL ≤ 4.498V
2.106V ≤ VCELL ≤ 4.498V
1.531V ≤ VCELL < 2.106V
1.531V ≤ VCELL < 2.106V
VCELL = 0.766V
VCELL = 0.766V
l
–0.8
–1
–1
–1.3
–1.5
–2
l
10
l
l
0.8
1
1
1.3
1.5
2
%
%
%
%
%
%
50
V
VS
Supply Voltage, V+ Relative to V–
VERR Specifications Met
VCELL
Cell Voltage Range
Full Scale Voltage Range
VCM
Common Mode Voltage Range Measured
Relative to V–
VERR Specifications Met
Range of Inputs Cn, n = 3 to 11
Range of Input C2
Range of Input C1
l
l
l
1.8
1.2
0
5•n
10
5
VTV
Temperature Input Detection Level Error
(Relative to VREF /2)
10V < V+ < 50V
l
–13
17
mV
HYS
UV/OV Detection Hysteresis Error
(Relative to Selected Value)
10V < V+ < 50V
l
–25
25
%
VREF
Reference Pin Voltage
VREF Pin Loaded With 100k to V–
l
3.043
3.038
3.073
3.078
V
V
VREG
IM
IQS
3.058
3.058
V
V
V
V
Reference Voltage Temperature Coefficient
8
Reference Voltage Hysteresis
50
ppm
Reference Voltage Long Term Drift
60
ppm/√khr
Regulator Pin Voltage
10V < VS < 50V, No Load
LTC6801IG
LTC6801HG
10V < VS < 50V, ILOAD = 4mA
LTC6801IG
LTC6801HG
Regulator Pin Short Circuit Current Limit
IB
5
Input Bias Current
Supply Current, Monitor Mode
Supply Current, Idle
In/Out of Pins C1 Thru C12
When Measuring Cells During Self Test
When Measuring Cells
When Idle
l
l
4.5
4.5
5
5
l
l
4.1
4.1
4.8
4.8
l
5
9
l
–10
100
1
ppm/˚C
5.5
5.7
V
V
V
V
mA
10
µA
µA
nA
Current Into the V+ Pin While Monitoring
for UV and OV Conditions, FENA = 10kHz
Continuous Monitoring
Continuous Monitoring
Monitor Every 130ms (Note 3)
Monitor Every 500ms (Note 3)
600
500
110
50
750
750
200
100
1000
1100
320
160
µA
µA
µA
µA
l
23
20
23
20
30
30
30
30
42
45
42
48
µA
µA
µA
µA
l
13
15.5
19
ms
l
2
40
kHz
l
25
500
µs
l
40
60
%
l
l
l
Current into the V+ Pin When Idle, FENA = 0
LTC6801IG
l
LTC6801HG
LTC6801 Timing Specifications
TCYCLE
Measurement Cycle Time
FENA
Valid EIN/EIN Frequency
TENA
Valid EIN/EIN Period = 1/ FENA
DCENA
Valid EIN/EIN Duty Cycle
DC = CC1 = CC0 = VREG
FENA = 40kHz
Rev. D
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3
LTC6801
The
l denotes the specifications which apply over the full operating
ELECTRICAL
CHARACTERISTICS
temperature range, otherwise specifications are at T = 25°C, V+ = 43.2V, V– = 0V unless otherwise noted.
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LTC6801 Single Ended Digital I/O Specifications (SLT, SLTOK Pins)
VIH
Digital Input Voltage High
SLT Pin
l
VIL
Digital Input Voltage Low
SLT Pin
l
2
0.5
V
V
VODL
Digital Output Voltage Low, Open Drain
SLT Pin, 10k to VREG
l
0.3
V
VOH
Digital Output Voltage High
SLTOK Pin, 10k to V–
l
VOL
Digital Output Voltage Low
SLTOK Pin, 10k to VREG
l
IPU-ST
Pull-Up Current
SLT Pin
l
2.5
l
1.7
VREG – 0.3
V
5
0.3
V
10
µA
LTC6801 Differential Digital Input Specifications (SIN/SIN, EIN/EIN Pins) (See Figure 1)
VIDH
Minimum Differential Input Voltage High
Differential Voltage Applied Between SIN
and SIN or EIN and EIN
V
VIDL
Minimum Differential Input Voltage Low
–1.7
V
VIL
Valid Input Voltage Low
Low Side of Differential Signal, Ref. to V–
l
0
1.2
V
VIH
Valid Input Voltage High
High Side of Differential Signal, Ref. to V–
l
2.5
6
V
VDHYS
Differential Input Hysteresis
VOPEN
Open Circuit Voltage
l
2
2.5
RINCM
Input Resistance, Common Mode
l
100
150
kΩ
RINDIFF
Input Resistance, Differential
l
200
300
kΩ
l
1
Between SIN to SIN, EIN to EIN
V
3
V
LTC6801 Differential Digital Output Specifications (SOUT/SOUT, EOUT/EOUT Pins)
VODH
Digital Output Voltage High
Output Pins Loaded With 100k to V–
l VREG – 0.4
VODL
Digital Output Voltage Low
Output Pins Loaded With 100k to VREG
l
V
0.4
V
LTC6801 Three-Level Digital Input Specifications (OV0, OV1, UV0, UV1, HYST, DC, CC0 and CC1 Pins)
V3IH
Three-Level Digital Input Voltage High
l VREG – 0.3
V3IM
Three-Level Digital Input Voltage Mid
l VREF – 0.3
V
V3IL
Three-Level Digital Input Voltage Low
0.3
V
IPU
Pull-Up Current
Pins DC, CC0, CC1, UV0 and UV1
l
0.5
1
2
µA
IPD
Pull-Down Current
Pins HYST, OV0 and OV1
l
0.5
1
2
µA
VREF + 0.3
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
V
Note 2: VCELL refers to the voltage applied across the following pin
combinations: Cn to Cn – 1 for n = 2 to 12, C1 to V–.
Note 3: Guaranteed by continuous monitoring supply current
specifications, not subject to test.
EIN
VIDH
(VALID HIGH WHEN
EIN – EIN ≥ VIDH)
MAX, VIH
MAX, VIL
V– = 0V
TENA
MIN, VIH
EIN
VIDL
(VALID LOW WHEN EIN – EIN ≤ VIDL)
6801 F01
Figure 1. Differential Input Specifications
4
Rev. D
For more information www.analog.com
LTC6801
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current, Monitor Mode
Supply Current, Monitor Mode
250
800
DC PIN TIED TO VREG
780 fENA = 10kHz
85°C
760
Supply Current, Idle Mode
40
CC1 = CC0 = VREG
fENA = 10kHz
35
200
700
680
DC PIN = VREF
150
100
–40°C
660
DC PIN = V–
50
640
ISUPPLY (µA)
25°C
ISUPPLY (µA)
620
600
10
20
30
V+ (V)
40
50
0
60
10
20
30
V+ (V)
40
50
250
V+ = 60V
DC PIN = VREF
150
100
DC PIN = V–
50
6801 G04
0.8 UV = 2.106V
0.4
ERROR (%)
ERROR (%)
0.6
5 TYPICAL UNITS
60
V+ = 35V
V+ = 10V
20
15
5
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
6801 G06
Supply Current
800
V+ = 43.2V
V+ = 43.2V
780 CONTINUOUS MEAS MODE
0.8 OV = 4.116V
–0.2
50
V+ = 60V
25
0V Detection Level Error
1.0
V+ = 43.2V
0
40
6801 G05
UV Detection Level Error
0.2
V+ (V)
10
V+ = 60V
V+ = 35V
V+ = 10V
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
600
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0.4
30
Supply Current, Idle Mode
35
620
0.6
20
40
30
V+ = 10V
640
1.0
10
6801 G03
ISUPPLY (µA)
ISUPPLY (µA)
ISUPPLY (µA)
V+ = 35V
680
660
0
60
CC1 = CC0 = VREG
fENA = 10kHz
740
700
15
5
200
720
–40°C
20
Supply Current, Monitor Mode
Supply Current, Monitor Mode
800
760
25
6801 G02
6801 G01
DC PIN TIED TO VREG
780 fENA = 10kHz
85°C
10
85°C
25°C
–40°C
760
5 TYPICAL UNITS
0.2
0
–0.2
720
680
–0.4
660
–0.6
–0.6
640
–0.8
–0.8
620
–1.0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
–1.0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
600
6801 G08
25°C
700
–0.4
6801 G07
85°C
740
ISUPPLY (µA)
ISUPPLY (µA)
740
720
25°C
30
–40°C
1
10
fENA (kHz)
100
6801 G09
Rev. D
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5
LTC6801
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
25°C
85°C
–40°C
2.0
1.5
1.0
0.5
0
0
8.0
CONTINUOUS MEAS MODE
CC1 = CC0 = VREG
16.5
16.0
V+ = 10V
15.5
V+ = 60V
15.0
14.5
10
C1
0
C2 TO C11
VTEMP1, VTEMP2
–10
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
3.070
UV THRESHOLD = 2.106V
OV THRESHOLD = 4.116V
10 HYST = V
REG
6
4
UNDERVOLTAGE
DETECTED
2
3.065
VREF (V)
VREF (V)
3.065
OVERVOLTAGE DETECTED
0
1
2
3
CELL VOLTAGE (V)
4
5
6
0
50
100
150
200
ILOAD (µA)
300
6801 G20
85°C
10
20
30
V+ (V)
40
50
60
6801 G15
5.5
NO LOAD
VREG Line Regulation
IDLE MODE
5.4 NO LOAD
85°C
5.3
5 TYPICAL UNITS
5.2
3.060
25°C
5.1
5.0
–40°C
4.9
4.8
4.7
25°C
250
3.050
VREF Output Voltage
3.055
85°C
–40°C
3.055
–40°C
3.050
25°C
3.060
6801 G14
3.070
3.055
NO LOAD
0
–2
VREF Load Regulation
3.060
VREF Line Regulation
3.065
8
6801 G13
3.070
5.0
6801 G12
VREF (V)
C PIN BIAS CURRENT (nA)
C12
SOUT CLOCK FREQUENCY (kHz)
CELL INPUT = 3.6V
20
5.5
4.0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
12
30
6.0
Cell Voltage Measurement
Hysteresis
Cell Input Bias Current, Idle Mode
40
6.5
6801 G11
6801 G10
50
7.0
4.5
14.0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2
4
6
8
10
EXTERNAL SERIES RESISTANCE, RS (kΩ)
CELL INPUT = 3.6V
7.5
VREG (V)
2.5
17.0
C PIN BIAS CURRENT (µA)
RS IN SERIES WITH Cn AND Cn-1
–
3.5 10nF FROM Cn, Cn-1 TO V
Cell Input Bias Current when
Measuring
Measurement Cycle Time
MEASUREMENT CYCLE TIME (ms)
ERROR RELATIVE TO RS = 0 (%)
4.0
UV/OV Detection Level Error
4.6
3.050
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
6801 G16
4.5
10
20
30
V+ (V)
40
50
60
6801 G17
Rev. D
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LTC6801
TYPICAL PERFORMANCE CHARACTERISTICS
5.5
VREG Line Regulation
5.5
IDLE MODE
5.4 4mA LOAD TO V–
VREG Load Regulation
5.5
IDLE MODE
5.4
5.3
5.2
5.0
85°C
4.9
4.8
25°C
4.7
–40°C
VREG (V)
5.0
5.1
VREG (V)
VREG (V)
IDLE MODE
5.3
5.2
4.5
4.6
4.5
VREG Output Voltage
10
20
30
V+ (V)
40
50
4.0
60
0
6801 G18
16
100k LOAD TO V–
4.8
V+ = 60V
V+ = 10V
4.6
4.7
4
6
ILOAD (mA)
8
6801 G19
6801 G21
UV/OV Detection Level Thermal
Hysteresis
20
TA = 85°C TO 25°C
18
NUMBER OF UNITS
NUMBER OF UNITS
10
8
6
4
20µs/DIV
6801 G22
14
12
10
8
6
4
2
0
–100
TA = –40°C TO 25°C
16
12
SOUT
V+ = 60V
V+ = 35V
V+ = 10V
4.5
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
10
14
2V/DIV
4mA LOAD
4.9
UV/OV Detection Level Thermal
Hysteresis
Status Output Operating at 10kHz
SOUT
5.0
85°C
25°C
–40°C
2
NO LOAD
5.1
2
–50
0
50
100
150
CHANGE IN DETECTION LEVEL (ppm)
200
6801 G23
0
–100
–50
0
50
100
150
CHANGE IN DETECTION LEVEL (ppm)
200
6801 G24
Rev. D
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7
LTC6801
PIN FUNCTIONS
V+ (Pin 1): Supply Voltage. Tied to the most positive
potential in the battery stack. For example, the same
potential as C12 when measuring a stack of 12 cells, or
the same potential as C7 when measuring a stack of 7
cells.
C12, C11, … C1 (Pin 2 to Pin 13): Cell Voltage Inputs.
Up to 12 cells can be monitored. The lowest potential
is tied to V–. The next lowest potential is tied to C1 and
so forth. Due to internal overvoltage protection, each
C input must be tied to a potential equal to or greater
than the next lower numbered C input. See the figures
in the Applications Information section for more details
on connecting batteries to the LTC6801. See Electrical
Characteristics table for voltage range and input bias
current requirements.
V– (Pin 14): Tied to the most negative cell potential (bottom of monitored cell stack).
VTEMP1, VTEMP2 (Pin 15, Pin 16): Temperature Sensor
Inputs. The ADC will measure the voltages on VTEMP1
and VTEMP2 relative to V–. The ADC measurements are
referenced to the VREF pin voltage. Therefore a simple
thermistor and resistor combination connected to the
VREF pin can be used to monitor temperature. These pins
have a fixed undervoltage threshold equal to one half VREF.
A filtering capacitor to V– is recommended. Temperature
sensor input pins may be tied to VREF to disable.
VREF (Pin 17): Reference Output, Nominally 3.058V.
Re-quires a 1µF bypass capacitor to V–. The VREF pin can
drive a 100k resistive load connected to V–. VREF must
be buffered with an LT6003 amplifier, or similar device to
drive heavier loads. VREF becomes high impedance when
the IC is disabled or idle between monitoring events.
VREG (Pin 18): Regulator Output, Nominally 5V. Requires
a 1µF bypass capacitor to V–. The VREG pin is capable of
supplying up to 4mA to an external load and is continually
enabled.
EIN, EIN (Pin 19, Pin 20): Differential Enable Input. A
clock signal greater than 2kHz will enable the LTC6801.
8
For operation with a single-ended enable signal (up to
10kHz), drive EIN and connect a 1nF capacitor from EIN
to V–.
SOUT, SOUT (Pin 21, Pin 22): Differential Status Output.
Swings V– to VREG. This output will toggle at the same
frequency as EIN/EIN when a valid signal is detected at SIN/
SIN and the battery stack being monitored is within specified parameters, otherwise SOUT is low and SOUT high.
SIN, SIN (Pin 23, Pin 24): Differential status input from
the IC above. To indicate that the stack is good, SIN must
be the same frequency and phase as EIN. See applications
circuits for interfacing SIN to the SOUT above.
EOUT, EOUT (Pin 25, Pin 26): A Buffered Version of EIN/
EIN. Swings V– to VREG. Must be capacitively coupled to
the EIN/EIN inputs of the next higher voltage LTC6801 in a
stack, or looped to SIN/SIN of the same chip (pins 23, 24).
DC (Pin 27): Duty Cycle Three-Level Input. This pin may
be tied to VREG, VREF or V–. The DC pin selects the duty
cycle of the monitoring function and has an internal
pull-up to VREG. See Table 3.
SLTOK (Pin 28): Self Test Logic Output. SLTOK is held
HIGH (VREG voltage) upon reset or successful completion of a self test cycle. A LOW output level (V– voltage)
indicates the last self test cycle failed.
SLT (Pin 29): Self Test Open Collector Input/Output.
SLT initiates a self test cycle when it is pulled low externally. When a high to low transition is detected, the next
scheduled measurement cycle will be a self test cycle. SLT
indicates a self test cycle is in progress when pulled low
internally. A self test is automatically initiated after 1024
measurement cycles. This pin has an internal pull-up to
VREG.
CC0, CC1 (Pin 30, Pin 31): Cell Count Three-Level Inputs.
These pins may be tied to VREG, VREF or V–. CC1 and CC0
select the number of cells attached to the device and each
pin has an internal pull-up to VREG. See Table 5.
Rev. D
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LTC6801
PIN FUNCTIONS
HYST (Pin 32): Hysteresis Three-Level Input. This pin
may be tied to VREG, VREF or V–. HYST selects the amount
of hysteresis applied to the undervoltage and overvoltage
threshold settings and has an internal pull-down to V–.
See Table 4.
UV0, UV1 (Pin 33, Pin 34): Undervoltage Three-Level
Inputs. These pins may be tied to VREG, VREF or V–. UV1
and UV0 select the undervoltage threshold and each pin
has an internal pull‑up to VREG. See Table 2.
OV0, OV1 (Pin 35, Pin 36): Overvoltage Three-Level
Inputs. These pins may be tied to VREG, VREF or V–. OV1
and OV0 select the overvoltage threshold and each pin
has an internal pull‑down to V–. See Table 1.
Table 3. Duty Cycle Select
DC
NOMINAL CYCLE TIME*
VREG
15.5ms
VREF
Approximately 130ms
V–
Approximately 500ms
*Cycle time based on LTC6801 measuring 12 cells and 2 temperatures.
Table 4. Hysteresis Select
HYST
UV HYSTERESIS*
OV HYSTERESIS
VREG
500mV
200mV
VREF
250mV
100mV
V–
0mV
0mV
*UV hysteresis is disabled when the undervoltage threshold is set to 0.766V.
Table 1. Overvoltage Inputs
Table 5. Cell Count Select
OV1
OV0
OVERVOLTAGE THRESHOLD (V)
VREG
VREG
4.498
CC1
CC0
CELL COUNT
VREG
VREF
4.403
VREG
VREG
12
VREG
V–
4.307
VREG
VREF
11
VREF
VREG
4.211
VREG
V–
10
VREG
9
VREF
VREF
4.116
VREF
VREF
V–
4.020
VREF
VREF
8
V–
7
VREG
3.924
VREF
V–
V–
VREF
3.828
V–
VREG
6
V–
V–
3.733
V–
VREF
5
V–
V–
4
Table 2. Undervoltage Inputs
UV1
UV0
UNDERVOLTAGE THRESHOLD (V)
VREG
VREG
2.871
VREG
VREF
2.680
VREG
V–
2.489
VREF
VREG
2.297
VREF
VREF
2.106
VREF
V–
1.914
V–
VREG
1.723
V–
VREF
1.531
V–
V–
0.766
Rev. D
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9
LTC6801
BLOCK DIAGRAM
The LTC6801 measures between 4 and 12 cell voltages and 2 temperature inputs. If all measurements are
within an acceptable window, the LTC6801 will produce
a differential clock output signal (SOUT, SOUT). If any of
the channels exceed user set upper and lower thresholds,
a logic low signal is produced at SOUT.
V+
VREG
REGULATOR
C12
HYST
C11
CC1
C10
12
ADC
C9
C8
+
CC0
DC
–
DIGITAL
COMPARATORS
C7
C6
–
REFERENCE
MUX
C5
C4
C3
SLT
SLTOK
+
–
+
SELF TEST
REFERENCE
(REF2)
UV/OV
FLAGS AND
CONTROL
LOGIC
EIN
EIN
EOUT
EOUT
C2
C1
“GOOD”
V–
+
–
SIN
SIN
SOUT
DECODER
SOUT
VTEMP1
VTEMP2
VREF
OV0
OV1
UV0
UV1
6801 BD
10
Rev. D
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LTC6801
BLOCK DIAGRAM OF ENABLE IN/OUT AND STATUS IN/OUT
EOUT
EOUT
VREG
300k
THE FREQUENCY MATCH
DETECT OUTPUT GOES
HIGH WHEN SIN AND EIN
ARE THE SAME FREQUENCY
FREQUENCY
MATCH
DETECT
+
–
VREG
SIN
300k
300k
SIN
300k
THE SIGNAL IS
HIGH WHEN
ALL READINGS
ARE “GOOD”
SOUT
SOUT
SOUT IS ACTIVE WHEN
1) EIN IS ACTIVE
2) SIN AND EIN ARE THE SAME FREQUENCY
3) ALL READINGS ARE “GOOD”
VREG
300k
+
CLK
DETECT
–
THE CLK DETECT
OUTPUT GOES
HIGH WHEN EIN IS
2kHz TO 40kHz
VREG
EIN
300k
300k
EIN
300k
6801 BDa
Rev. D
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11
LTC6801
APPLICATIONS INFORMATION
OVERVIEW
INDEPENDENT OPERATION
The LTC6801 is designed as an easy to implement, lowcost battery stack monitor that provides a simple indication of correct battery stack operation without requiring
a microcontroller interface. For battery stack monitoring
with cell voltage read back and discharge circuitry, refer
to the LTC6802 battery stack monitor data sheet.
Figure 3 shows how three groups of 12 cells can be monitored independently.
The LTC6801 contains a 12-bit ADC, a precision voltage reference, sampled comparator, high voltage multiplexer and timer/sequencer. During normal operation, the
sequencer multiplexes the ADC inputs between each of
the channel input pins in turn, performing a single comparison to the undervoltage and overvoltage thresholds.
The VTEMP inputs are also monitored for an undervoltage
at a fixed threshold of VREF /2.
REGULATED OUTPUTS
A regulated voltage is provided at the VREG pin, biased
from the battery stack. The VREG pin can supply up to 4mA
at 5V and may be used to power small external circuits.
The regulated output remains at 5V continually, as long
as the total stack voltage is between 10V and 50V.
A low current, precision reference voltage is provided at
the VREF pin, which can drive loads of greater than 100k.
The VREF output is high impedance when the LTC6801
is idle.
The presence of a status output clock indicates the system
is “OK”. Because the status output is dynamic, it cannot
get stuck in the “OK” state.
Both the VREG and VREF pins must be bypassed to V– with
a 1µF capacitor.
STACKED OPERATION
The LTC6801 thresholds are controlled by the UV1, UV0,
OV1 and OV0 pins. These pins are designed to be tied
directly to VREG, VREF or V– in order to set the comparison
thresholds for all channels simultaneously. The pins are
not designed to be variable. In particular, changes made
to the pins while the chip is not in idle mode may result in
unpredictable behavior. See Table 1 and Table 2 for setting
and threshold information.
Each LTC6801 monitors a group of up to 12 series connected cells. Groups of cells can be connected in series
or parallel to form a large battery pack. The LTC6801s can
be daisy chained with simple capacitive or transformer
coupling. This allows every cell in a large battery pack
to be monitored with a single signal. Figure 2 illustrates
monitoring of 36 series connected cells.
CONTROL INPUTS
To cancel systematic duty cycle distortion through the
clock buffers, it is recommended that the clock lines are
cross-coupled (EOUT goes to EIN etc.) as they route up
and down the stack as shown in Figure 2.
12
Rev. D
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LTC6801
APPLICATIONS INFORMATION
ENABLE INPUTS
In order to support stacked operation, the LTC6801 is
enabled through a differential signal chain encompassing
the EIN/EIN, EOUT/EOUT, and SIN/SIN pins.
The LTC6801 will be enabled if a differential square wave
with a frequency between 2kHz and 40kHz is applied at
EIN/EIN. Otherwise, the LTC6801 will default to a low
power idle mode.
If the differential signal at SIN/SIN is not equal in frequency to the differential signal output at EOUT/EOUT,
the LTC6801 will be enabled but SOUT will be held at 0V
and SOUT will be held at VREG.
For the simplest operation in a single chip configuration,
EOUT should be connected directly to SIN and EOUT
should be connected directly to SIN, and a square wave
with a frequency between 2kHz and 40kHz should be
applied differentially to EIN and EIN. For enable clock frequencies up to 10kHz, a single-ended square wave with
a 5V swing may be used at EIN while a 1nF capacitor is
connected from EIN to V–.
STATUS OUTPUT
If the chip is properly enabled (EIN/EIN, SIN/SIN are the
same frequency), all cells are within the undervoltage
and overvoltage thresholds, and the voltage at VTEMP1
and VTEMP2 is over one half VREF, the differential output
at SOUT/SOUT will toggle at the same frequency and in
phase with the signal at EIN/EIN. Otherwise, SOUT will be
low and SOUT will be high.
The maximum delay between when a bad cell voltage
occurs and when it is detected depends on the measurement duty cycle setting. The SOUT clock turns on or off
at the end of each measurement cycle. Figure 4 shows the
maximum detection delay in continuous monitor mode
(DC pin tied to VREG).
Note: If an internal self test occurs immediately after the
fault, the maximum detection delay will be increased by
an additional measurement cycle time.
FAULT PROTECTION
Overview
Care should always be taken when using high energy
sources such as batteries. There are countless ways that
systems can be [mis-]configured during the assembly
and service procedures that can impact a battery’s long
term performance. Table 6 shows various situations to
consider when planning protection circuitry.
Battery Interconnection Integrity
Please note: The last condition shown in the FMEA table
could cause catastrophic IC failures. In this case, the battery string integrity is lost within a cell group monitored by
an LTC6801. This condition could place excessive stress
on certain cell input signal clamp-diodes and probably
lead to IC failure. If this scenario seems at all likely in a
particular application, series fuses and parallel Schottky
diodes should be connected as shown in Figure 5 to limit
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13
LTC6801
APPLICATIONS INFORMATION
TOP OF
STACK
TOP OF
STACK
V+
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
V–
LTC6801
SIN
SOUT
SOUT
VREF
VREG
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
V–
LTC6801
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
V–
EIN
EIN
VREF
VREG
OV1
V+
SIN
LTC6801
VREF
VREG
OV1
V+
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
V–
OV0
UV1
UV0
HYST
CC1
CC0
SLT
SLTOK
DC
EOUT
EOUT
SIN
SIN
SOUT
VTEMP2
SOUT
CLOCK OUT
WHEN ALL
CELLS GOOD
USER SUPPLIED
CLOCK IN
EIN
EIN
6801 F02
EIN
EIN
LTC6801
OV1
OV0
UV1
UV0
HYST
CC1
CC0
SLT
SLTOK
DC
EOUT
EOUT
SIN
SIN
SOUT
SOUT
EIN
EIN
LTC6801
OV1
OV0
UV1
UV0
HYST
CC1
CC0
SLT
SLTOK
DC
EOUT
EOUT
SIN
ALL CLOCKS
OUT WHEN ALL
CELLS GOOD
SIN
SOUT
VTEMP2
SOUT
USER SUPPLIED
CLOCK IN
EIN
EIN
6801 F03
BOTTOM
OF STACK
BOTTOM
OF STACK
Figure 2. Serial Connection of Status Lines for Multiple
LTC6801s on the Same PCB (Simplified Schematic, Not All
Components Shown)
14
SIN
SOUT
SOUT
VTEMP1
VREF
VREG
PROGRAMMED CONDITIONS:
CONTINUOUS MONITOR MODE
OV = 4.116V
UV = 2.106V
HYST = 250mV (UV), 100mV (OV)
CC = 12
OV1
OV0
UV1
UV0
HYST
CC1
CC0
SLT
SLTOK
DC
EOUT
EOUT
SIN
VTEMP1
VTEMP2
EIN
EIN
VTEMP1
VREF
VREG
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
V–
SOUT
SOUT
VREF
VREG
LTC6801
VTEMP1
VTEMP2
OV0
UV1
UV0
HYST
CC1
CC0
SLT
SLTOK
DC
EOUT
EOUT
SIN
VTEMP1
VTEMP2
V+
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
V–
OV0
UV1
UV0
HYST
CC1
CC0
SLT
SLTOK
DC
EOUT
EOUT
SIN
VTEMP1
VTEMP2
V+
V+
OV1
Figure 3. Independent Status Lines for Multiple LTC6801s on the
Same PCB (Simplified Schematic, Not All Components Shown)
Rev. D
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EXAMPLES
SOUT
C2
C3
C4
C6
C7
C8
C9
C10
WORST CASE ERROR DETECTION
DELAY ~29.7ms
C5
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C12
T2
SOUT
REMAINS
ACTIVE
T1
(SINCE NOTHING
ABNORMAL HAS
BEEN DETECTED YET)
C11
C1
C2
C4
LTC6801 READS
A BAD VOLTAGE
ON CELL 1
C3
SOUT STATUS
UPDATED
C5
C6
C7
Figure 4. Cell UV/OV Detection Delay in Continuous Monitor Mode
NOTE: SOUT IS NOT TO SCALE
SEE ELECTRICAL TABLE FOR MIN/MAX SPECIFICATIONS
CELL 1 GOES BAD
IMMEDIATELY
AFTER IT IS READ
ALL
CELLS
GOOD
C1
COMPLETE MEASUREMENT CYCLE 15.4 ms
(~1.1ms PER CELL)
C8
C9
C10
C11
C12
T1
SOUT STATUS
UPDATED
T2
C2
C3
6801 F04
SOUT STOPS
AT END OF
MEASUREMENT
CYCLE
C1
LTC6801
APPLICATIONS INFORMATION
Rev. D
15
LTC6801
APPLICATIONS INFORMATION
Table 6. Failure Mechanism Effect Analysis (FMEA)
SCENARIO
EFFECT
DESIGN MITIGATION
Cell input open-circuit (random)
Power-up sequence at IC inputs
Clamp diodes at each pin to V+ & V– (within IC)
provide alternate PowerPath.
Cell input open-circuit (random)
Differential input voltage overstress
Zener diodes across each cell voltage input pair
(within IC) limit stress.
Top cell input connection loss (V+)
Power will come from highest connected cell
input
Clamp diodes at each pin to V+ and V– (within
IC) provide alternate PowerPath. Error condition
will be indicated by all upstream and downstream
units (no clock on SOUT/ SOUT).
Bottom cell input connection loss (V–)
Power will come from lowest connected cell input Clamp diodes at each pin to V+ and V– (within
IC) provide alternate PowerPath. Error condition
will be indicated by all upstream and downstream
units (no clock on SOUT/ SOUT).
Power input disconnection
(amongst stacked units)
Loss of supply connections
Clamp diodes at each pin to V+ and V– (within
IC) provide alternate PowerPath. Error condition
will be indicated by all upstream and downstream
units (no clock on SOUT/ SOUT).
Status link disconnection
(between stacked units)
Break of “daisy chain” communication
(no stress to ICs)
Daisy chain will be broken and error condition
will be indicated by all upstream and downstream
units (no clock on SOUT/ SOUT).
Short between any two configuration inputs
Power supplies connected to pins will be shorted If VREF or VREG is shorted to V–, supply will
be removed from internal circuitry and error
condition will be indicated by all upstream and
downstream units (no clock on SOUT/ SOUT). If
VREF is shorted to VREG, a self test error will be
flagged.
Open connection on configuration input
Control input will be pulled towards positive or
negative potential depending on pin
Control input will be pulled to a more stringent
condition (larger number of channels, higher UV
threshold, lower OV threshold, shorter duty cycle,
etc. ensuring either more stringent monitoring or
error condition will be indicated by all upstream
and downstream units (no clock on SOUT/
SOUT).
Cell-pack integrity, break between stacked units
Daisy-chain voltage reversal up to full stack
potential
Full stack potential may appear across status/
enable isolation devices, but will not be seen by
the IC. isolation capacitors should therefore be
rated to withstand the full stack potential.
Cell-pack integrity, break within stacked unit
Cell input reverse overstress
Add battery tap fuses and Schottky diodes in
parallel with the cell inputs to limit stress on
IC. Diode and connections must handle current
sufficient to open fuse
16
Rev. D
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LTC6801
APPLICATIONS INFORMATION
V+
Cn
PROTECT
AGAINST
BREAKS
HERE
LTC6801
C12
EOUT
Cn – 1
C11
6801 F05
Figure 5. Using Fuses and Diodes for Cell Input
Protection (One Cell Connection Shown)
stress on the IC inputs. The diodes used in this situation
need current ratings sufficient to open the protective fuse
in the battery tap signal.
EOUT
SIN
C10
ZCLAMP
SIN
SOUT
C9
SOUT
EIN
C8
EIN
Internal Protection Structure
The LTC6801 incorporates a number of protective structures, including parasitic diodes, Zener-like overvoltage
suppressors, and other internal features that provide
protection against ESD and certain overstress conditions
that could arise in practice. Figure 6 shows a simplified
internal schematic that indicates the significant protective structures and their connectivity. The various diodes
indicate the approximate current versus voltage characteristics that are intrinsic to the part, which is useful in
analyzing responses to certain external stresses, such as
during a hot-start scenario.
SELF TEST CIRCUITRY
The LTC6801 has internal circuitry that performs a periodic self test of all measurement functions. The LTC6801
self test circuitry is intended to prevent undetectable
failure modes. Accuracy and functionality of the voltage
reference and comparator are verified, as well as functionality of the high voltage multiplexer and ADC decimation
VTEMP1
C7
VTEMP2
C6
ZCLAMP
VREF
VREG
C5
OV1
OV0
C4
UV1
UV0
C3
HYST
CC1
C2
ZCLAMP
CC0
SLT
C1
SLTOK
V–
DC
6801 F06
Figure 6. Internal Protection Structures
Rev. D
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17
LTC6801
APPLICATIONS INFORMATION
filter. Additionally, open connections on the cell input pins
C1 to C11 are detected (Open connections on V– or C12/
V+ will cause an undervoltage failure during the normal
measurement cycle).
Self Test Pins
The SLT pin is used to initiate a self test. It is configured
as an open collector input/output. The pin should be normally tied to VREG with a resistor greater than or equal to
100k or floated. The pin may be pulled low at any time to
initiate a self test cycle.
The device will automatically initiate a self test if SLT
has not been externally activated for 1024 measurement
cycles, and pull down the SLT pin internally to indicate
that it is in self test mode.
The SLTOK pin is a simple logic output. If the previous self
test failed the output is held low, otherwise the output will
be high. The SLTOK pin is high upon power-up. The SLTOK
output can be connected to a microcontroller through an
isolation path.
The LTC6801 status output will remain active while the
SLTOK pin is low. The LTC6801 will continue to monitor
cells if the self test fails. If the next self test passes, the
SLTOK output returns high.
Reference and Comparator Verification
A secondary internal bandgap voltage reference (REF2)
is included in the LTC6801 to aid in verification of the
reference and comparator. During the self test cycle, the
comparator and main reference are used to measure the
REF2 voltage.
To verify the comparator functionality, the upper and
lower thresholds are first set in a close window around
18
the expected REF2 voltage and the comparator output is
verified. Then the upper threshold is set below the REF2
voltage and the comparator output is verified again. Lastly,
the lower threshold is set above the REF2 voltage and the
comparator output is verified a third time.
The self test guarantees that VREF is within 5% of the
specified nominal value. Also, this test guarantees the
analog portion of the ADC is working.
High Voltage Multiplexer Verification
The most dangerous failure mode of the high voltage
multiplexer would be a stuck bit condition in the address
decoder. Such a fault would cause some channels to be
measured repeatedly while other channels are skipped.
A skipped channel could mean a bad cell reading is not
detectable. Other multiplexer failures, like the simultaneous selection of multiple channels, or shorts in the signal
path, would result in an undervoltage or overvoltage condition on at least one of the channels.
The LTC6801 incorporates circuitry to ensure that
all requested channels are measured during each
measurement cycle and none are skipped. If a channel
is skipped, an error is flagged during the self test cycle.
ADC Decimation Filter Verification
The ADC decimation filter test verifies that the digital circuits in the ADC are working, i.e. there are no stuck bits
in the ADC output register. During each self test cycle,
the LTC6801 feeds two test waveforms into the ADC.
The internally generated waveforms were designed to
generate complementary zebra patterns (alternating 0’s
and 1’s) at the ADC output. If either of the waveforms
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LTC6801
APPLICATIONS INFORMATION
generates an incorrect output value, an error is flagged
during the self test cycle.
Open Cell Connection Detection
The open connection detection algorithm ensures that an
open circuit is not misinterpreted as a valid cell reading.
In the absence of external noise filtering, the input resistance of the ADC will cause open wires to produce a near
zero reading. This reading will cause an undervoltage
failure during the normal measurement cycle.
Some applications may include external noise filtering to
improve the quality of the voltage comparisons. When
an RC network is used to filter noise, an open wire may
not produce a zero reading because the comparator input
resistance is too large to discharge the capacitors on the
input pin. Charge may build up on the open pin during
successive measurement cycles to the extent that it could
indicate a valid cell voltage reading.
During each self test cycle, the LTC6801 will sink 100µA
to V– from each side of the cell being measured. The
undervoltage threshold is not checked during the self test
because the 100µA pull-down current would cause false
failures in some cases. If an input is open, this current will
discharge any filtering capacitors and cause the input to
C12
C11
C10
C9
C8
C7
C6
C5
C4
CSBO
CSBI
SDOI
SDO
SCKO
SDI
+
V
SCKI
C12
VMODE
S12
GPIO2
C11
GPIO1
S11
WDTB
C10
MMB
LTC6802-1 TOS
S10
C9
VREG
S9
VREF
C8
VTEMP2
S8
VTEMP1
C7
NC
S7
V–
C6
S1
S6
C1
C5
S2
S5
C2
C4
S3
S4
C3
IN
float down to approximately 0.7V below the next lower cell
input. In most cases, the cell voltage of the cell above the
open input will exceed the overvoltage threshold and flag
a self test error. During the normal measurement cycle,
the LTC6801 will sink 1µA to V– from each side of the cell
being measured. If the cell voltages are low enough that
an open wire is not detected as an overvoltage during
self test, this current will cause the cell input to settle to
a voltage low enough to trigger an undervoltage condition
during the normal measurement cycle.
Note, an open cell connection may not be detected when
the UV = 0.766V setting is used. For all other UV settings,
an open cell connection will result in either a self test error
or no SOUT clock.
Using The LTC6801 with Other Battery Monitors
When used in combination with an LTC6802-1, it is
possible to check the LTC6801 self test result via the
LTC6802-1 and its isolated SPI. As shown in Figure 7, the
SLTOK output is tied to the GPIO2 pin on the LTC6802-1.
SLTOK will remain high as long as it is passing the self
test. A self test will occur automatically every 1024 measurement cycles (17 seconds to 9 minutes, depending
on measurement duty cycle). A self test can be initiated
by a falling edge on SLT, via the LTC6802-1 GPIO1 line.
A self test will start after the current measurement cycle
CMPD6263
OUT
100k
1M
1µF
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
VREF
1µF
OV1
V+
OV0
C12
UV1
C11
UV0
C10
HYST
C9
CC1
C8
LTC6801
CC0
C7
SLT
C6
SLTOK
C5
DC
C4
EOUT
C3
EOUT
C2
SIN
C1
SIN
V–
SOUT
VTEMP1
SOUT
VTEMP2
EIN
VREF
EIN
VREG
6801 F07
C3
C2
C1
Figure 7. Interconnection of an LTC6802-1 and LTC6801 for Self Test.
Rev. D
For more information www.analog.com
19
LTC6801
APPLICATIONS INFORMATION
is complete, and the SLTOK status will be valid when the
self test completes. The worst case delay before SLTOK is
valid in continuous monitor mode is approximately 15ms
for the current cycle to complete plus 17ms for the self
test to complete.
Series resistors of 1k may be inserted in the input paths
without introducing measurement error. Shunt capacitors
may be added from the cell inputs to V–, creating RC filtering as shown in Figure 8. The combination of 1k and 10nF
is recommended as a robust, cost effective noise filter.
The 6802-1 can measure the LTC6801 reference, which
will independently test the analog circuitry of the LTC6802.
CELL-VOLTAGE FILTERING
The LTC6801 employs a sampling system to perform its
analog-to-digital conversions and provides a conversion
result that is essentially an average over the 0.5ms conversion window. If there is significant noise at frequencies near 500kHz there may be aliasing in the delta-sigma
modulator. A lowpass filter with 30dB attenuation at
500kHz may be beneficial. Since the delta-sigma integration bandwidth is about 1kHz, the filter corner need not
be lower than this to assure accurate conversions.
1k
500k
NTC
B = 4567
500k
NTC
B = 4567
100k
1µF
1µF
100k
6801 F09
Figure 9. Driving Thermistors Directly from VREF.
Two Independent Probes With a +60°C Trip Point
C3
1k
10nF
1k
10nF
C2
10k
NTC
B = 3380
10k
NTC
B = 3380
0.5µF
0.5µF
C1
2.2k
2.2k
V+
OV1
C12
OV0
C11
UV1
C10
UV0
C9
HYST
C8
CC1
LTC6801
C7
CC0
C6
SLT
C5
SLTOK
C4
DC
C3
EOUT
C2
EOUT
C1
SIN
–
V
SIN
VTEMP1
SOUT
VTEMP2
SOUT
VREF
EIN
VREG
EIN
6801 F10
V–
+
10nF
V+
OV1
C12
OV0
C11
UV1
C10
UV0
C9
HYST
C8
CC1
LTC6801
C7
CC0
C6
SLT
C5
SLTOK
C4
DC
C3
EOUT
C2
EOUT
C1
SIN
V–
SIN
VTEMP1
SOUT
VTEMP2
SOUT
VREF
EIN
VREG
EIN
6801 F08
LT6003
Figure 8. Adding RC Filtering to the Cell inputs
–
Figure 10. Buffering VREF for Higher-Current Sensors.
Two Independent Probes With a +70°C Trip Point
20
Rev. D
For more information www.analog.com
LTC6801
APPLICATIONS INFORMATION
MEASURING VARIOUS CELL COUNTS
The LTC6801 is designed to measure up to 12 cells
depending on the state of the CC pins (See Table 5). When
using an LTC6801 configured for measuring less than 12
cells, for instance choosing to measure 8 cells by tying
both CC1 and CC0 to the VREF pin, the highest cell potential (in this case C8) must be connected to the V+ pin for
proper operation. Unused cell connection pins (in this
case C9 to C12) may be left floating or may also be tied
to the highest cell potential.
READING EXTERNAL TEMPERATURE PROBES
The LTC6801 includes two channels of ADC input, VTEMP1
and VTEMP2, that are intended to monitor thermistors
(tempco about –4%/°C generally) or diodes (–2.2mV/°C
typical) located within the cell array. Sensors can be powered directly from VREF as shown in Figure 9 (up to 30µA
typical).
The temperature measurement inputs (VTEMP1, VTEMP2)
of the LTC6801 are comparator input channels with a
voltage threshold of one-half VREF. Input voltages above
half VREF are considered good. Voltages below the onehalf VREF threshold are considered a fault condition. The
inputs may be used in combination with resistors, thermistors, or diodes to sense both an upper and lower temperature limit. Figure 9, Figure 10 and Figure 11 illustrate
some possibilities. To ignore these inputs simply connect VTEMP1 and VTEMP2 to VREF. A filtering capacitor to
V– is recommended to minimize the error caused by the
approximately 700k input impedance of the ADC.
For sensors that require higher drive currents, a buffer
amplifier may be used as shown in Figure 10. Power for
the sensor is actually sourced indirectly from the VREG pin
in this case. Probe loads up to about 1mA maximum are
500k
NTC
B = 4567
100k
1µF
1150k
100k
NTC
B = 4250
1µF
V+
OV1
C12
OV0
C11
UV1
C10
UV0
C9
HYST
C8
CC1
LTC6801
C7
CC0
C6
SLT
C5
SLTOK
C4
DC
C3
EOUT
C2
EOUT
C1
SIN
V–
SIN
VTEMP1
SOUT
VTEMP2
SOUT
VREF
EIN
VREG
EIN
6801 F11
Figure 11. Sensing Both Upper and Lower Temperature
Thresholds. This Example Monitors a –20°C to +60°C Window
Detector. The Thermistors Should Be in Close Proximity
supported in this configuration. Since VREF is shut down
while the LTC6801 is idle between measurement cycles,
the thermistor drive is also shut off and thus power dissipation is minimized. Since VREG remains always-on, the
buffer op amp (LT6003 shown) is selected for its ultralow
current consumption (10µA).
For circuits that include filtering capacitance, note that
only the fastest DC setting (VREG connection) will keep
VREF steady and allow the VTEMP voltages to settle. To use
the lower power DC settings, VREF must be buffered (see
Figure 10), so that a low impedance is presented to the
ADC, with a time constant of no more than about 1ms.
ADVANTAGES OF DELTA-SIGMA ADCs
The LTC6801 employs a delta-sigma analog to digital
converter for voltage measurement. The architecture of
delta-sigma converters can vary considerably, but the
common characteristic is that the input is sampled many
times over the course of a conversion and then filtered or
averaged to produce the digital output code.
Rev. D
For more information www.analog.com
21
LTC6801
APPLICATIONS INFORMATION
For a given sample rate, a delta-sigma converter can
achieve excellent noise rejection while settling completely
in a single conversion. This is particularly important for
noisy automotive systems. Other advantages of delta-sigma converters are that they are inherently monotonic, meaning they have no missing codes, and they have
excellent DC specifications.
The LTC6801’s ADC has a second order delta-sigma
modulator followed by a SINC2, finite impulse response
(FIR) digital filter, with a lowpass bandwidth of 1kHz. The
front-end sample rate is 512ksps, which greatly reduces
input filtering requirements. A simple 16kHz, 1 pole filter
composed of a 1k resistor and a 10nF capacitor at each
input will provide adequate filtering for most applications.
These component values will not degrade the DC accuracy
of the ADC.
Each conversion consists of two phases – an autozero
phase and a measurement phase. The ADC is autozeroed
at each conversion, greatly improving CMRR.
USING TRANSFORMERS FOR GALVANIC ISOLATION
As shown in Figure 12, small gate-drive signal transformers can be used to interconnect devices and transport
the enable and sense signals safely across an isolation
barrier. Driving a transformer with a squarewave requires
transient currents of several mA and frequency of operation at 20kHz or higher. Since the output pins of the
LTC6801 are current limited at
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