Data Sheet
LTC7891
100 V, Low IQ, Synchronous Step-Down Controller for GaN FETs
FEATURES
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TYPICAL APPLICATION CIRCUIT
GaN drive technology fully optimized for GaN FETs
Wide VIN range: 4 V to 100 V
Wide output voltage range: 0.8 V ≤ VOUT ≤ 60 V
No catch, clamp, or bootstrap diodes needed
Internal smart bootstrap switches prevent overcharging of highside driver supplies
Internally optimized, smart near zero dead times or resistor
adjustable dead times
Split output gate drivers for adjustable turn on and turn off driver
strengths
Accurate adjustable driver voltage and UVLO
Low operating IQ: 5 μA (48 VIN to 5 VOUT)
Programmable frequency (100 kHz to 3 MHz)
Phase lockable frequency (100 kHz to 3 MHz)
Spread spectrum frequency modulation
28-lead (4 mm × 5 mm) side wettable QFN package
Figure 1. Typical Application Circuit
APPLICATIONS
Industrial power systems
Military avionics and medical systems
► Telecommunications power systems
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GENERAL DESCRIPTION
The LTC7891 is a high performance, step-down, dc-to-dc switching
regulator controller that drives all N-channel synchronous gallium
nitride (GaN) field effect transistor (FET) power stages from input
voltages up to 100 V. The LTC7891 solves many of the challenges
traditionally faced when using GaN FETs. The LTC7891 simplifies
the application design while requiring no protection diodes and no
other additional external components compared to a silicon metaloxide semiconductor field effect transistor (MOSFET) solution.
The internal smart bootstrap switch prevents overcharging of the
BOOST pin to SW pin high-side driver supplies during dead times,
protecting the gate of the top GaN FET. The LTC7891 internally
optimizes the gate driver timing on both switching edges to achieve
smart near zero dead times, significantly improving efficiency and
allowing for high frequency operation, even at high input voltages.
Alternatively, the user can adjust the dead times with external
resistors for margin or to tailor the application.
The gate drive voltage of the LTC7891 can be precisely adjusted
from 4 V to 5.5 V to optimize performance, and to allow the use of
different GaN FETs, or even logic level MOSFETs.
Figure 2. Efficiency and Power Loss vs. Load Current
Note that throughout this data sheet, multifunction pins, such as
PLLIN/SPREAD, are referred to either by the entire pin name or
by a single function of the pin, for example, PLLIN, when only that
function is relevant.
Rev. 0
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Data Sheet
LTC7891
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Typical Application Circuit .....................................1
General Description...............................................1
Specifications........................................................ 3
Electrical Characteristics.................................... 3
Absolute Maximum Ratings...................................6
ESD Caution.......................................................6
Pin Configuration and Function Descriptions........ 7
Typical Performance Characteristics..................... 9
Theory of Operation.............................................15
Functional Diagram.......................................... 15
Main Control Loop............................................ 15
Power and Bias Supplies (VIN, EXTVCC,
DRVCC, and INTVCC)......................................15
High-Side Bootstrap Capacitor.........................15
Dead Time Control (DTCA and DTCB Pins).... 16
Startup and Shutdown (RUN and
TRACK/SS Pins)............................................ 16
Light Load Operation: Burst Mode
Operation, Pulse Skipping Mode, or
Forced Continuous Mode (MODE Pin)...........16
Frequency Selection, Spread Spectrum,
and Phase-Locked Loop (FREQ and
PLLIN/SPREAD Pins).................................... 17
Output Overvoltage Protection......................... 17
Foldback Current..............................................17
Power Good..................................................... 17
Applications Information...................................... 18
Inductor Value Calculation................................18
Inductor Core Selection....................................18
Current Sense Selection.................................. 18
Low Value Resistor Current Sensing................19
Inductor DCR Current Sensing.........................19
Setting the Operating Frequency..................... 20
Selecting the Light Load Operating Mode........ 21
Dead Time Control (DTCA and DTCB Pins).... 21
CIN and COUT Selection.................................... 23
Setting the Output Voltage............................... 23
RUN Pin and Undervoltage Lockout................ 24
Soft Start and Tracking (TRACK/SS Pin)......... 24
INTVCC Regulators (OPTI-DRIVE)...................25
Topside FET Driver Supply (CB).......................26
Minimum On Time Considerations................... 26
Fault Conditions: Current Limit and Foldback.. 26
Fault Conditions: Overvoltage Protection.........27
Fault Conditions: Overtemperature
Protection....................................................... 27
Phase-Locked Loop and Frequency
Synchronization..............................................27
Efficiency Considerations................................. 27
Checking Transient Response......................... 28
Design Example............................................... 28
PCB Layout Checklist.......................................29
PCB Layout Debugging....................................30
Typical Applications..........................................32
Related Products..............................................35
Outline Dimensions............................................. 36
Ordering Guide.................................................36
Evaluation Boards............................................ 36
REVISION HISTORY
5/2022—Revision 0: Initial Version
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Rev. 0 | 2 of 36
Data Sheet
LTC7891
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
TJ = −40°C to +150°C for the minimum and maximum values, TA = 25°C for the typical values, VIN = 12 V, RUN = 12 V, VPRG = floating,
EXTVCC = 0 V, DRVSET = 0 V, DRVUV = 0 V, TGUP = TGDN = TGxx, BGUP = BGDN = BGxx, and DTCA and DTCB = 0 V, unless otherwise
noted.
Table 1. Electrical Characteristics
Parameter
Symbol
INPUT SUPPLY
Input Supply Operating Range
Total Input Supply Current in Regulation
VIN
IVIN
CONTROLLER OPERATION
Regulated Output Voltage Set Point
Regulated Feedback Voltage 2
VOUT
VFB
Feedback Current2
Feedback Overvoltage Threshold
Transconductance Amplifier2
Maximum Current Sense Threshold
SENSE+ Pin Current
SENSE− Pin Current
Soft Start Charge Current
RUN Pin On Threshold
RUN Pin Hysteresis
DC SUPPLY CURRENT
VIN Shutdown Current
VIN Sleep Mode Current
Sleep Mode Current3
Pulse Skipping (PS) or Forced Continuous Mode
(FCM), VIN or EXTVCC Current3
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gM
VSENSE(MAX)
ISENSE+
ISENSE−
Test Conditions/Comments
Min
Typ
Max
Unit
100
V
μA
μA
60
V
0.8
0.8
5.0
12
0
1
10
1.8
0.808
0.812
5.075
12.18
+50
2
13
V
V
V
V
nA
µA
%
mMho
26
50
75
31
55
83
+1
mV
mV
mV
μA
μA
μA
μA
μA
V
mV
4
48 V to 5 V, no load1
14 V to 3.3 V, no load1
5
14
0.8
VIN = 4 V to 100 V, ITH voltage = 0.6 V to 1.2 V
VPRG = floating, TA = 25°C
VPRG = floating
VPRG = 0 V
VPRG = INTVCC
VPRG = floating, TA = 25°C
VPRG = 0 V or INTVCC, TA = 25°C
Relative to VFB, TA = 25°C
ITH = 1.2 V, sink and source current = 5 μA
VFB = 0.7 V, SENSE− = 3.3 V
ILIM = 0 V
ILIM = floating
ILIM = INTVCC
SENSE+ = 3.3 V, TA = 25°C
SENSE− < 3 V
3.2 V ≤ SENSE– < INTVCC – 0.5 V
SENSE– > INTVCC + 0.5 V
TRACK/SS = 0 V
RUN rising
RUN = 0 V
SENSE− < 3.2 V, EXTVCC = 0 V
VIN current, SENSE– ≥ 3.2 V, EXTVCC = 0 V
VIN current, SENSE– ≥ 3.2 V, EXTVCC ≥ 4.8 V
EXTVCC current, SENSE– ≥ 3.2 V, EXTVCC ≥ 4.8 V
SENSE– current, SENSE– ≥ 3.2 V
0.792
0.788
4.925
11.82
−50
7
21
45
67
−1
9.5
1.15
1
75
725
12
1.20
120
1
15
5
1
6
10
2
14.5
1.25
μA
µA
µA
µA
µA
µA
mA
Rev. 0 | 3 of 36
Data Sheet
LTC7891
SPECIFICATIONS
Table 1. Electrical Characteristics
Parameter
Symbol
GATE DRIVERS
TGxx or BGxx On-Resistance
Pull-Up
Pull-Down
BOOST to DRVCC Switch On-Resistance
TGxx or BGxx Transition Time4
Rise Time
Fall Time
TGxx Off to BGxx On Delay4
Synchronous Switch On Delay Time
BGxx Off to TGxx On Delay4
Top Switch On Delay Time
BGxx Falling to SW Rising Delay5
DRVCC Falling
EXTVCC LDO Switchover Voltage
EXTVCC Rising
EXTVCC Switchover Hysteresis
EXTVCC Falling
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Typ
Max
Unit
2.0
1.0
7
Ω
Ω
Ω
25
15
ns
ns
DTCA = 0 V
20
ns
DTCB = 0 V
DTCA = INTVCC, DTCB = INTVCC or resistor
DTCA = 50 kΩ, DTCB = INTVCC or resistor
DTCA = 100 kΩ, DTCB = INTVCC or resistor
DTCB = INTVCC, DTCA = INTVCC or resistor
DTCB = 50 kΩ, DTCA = INTVCC or resistor
DTCB = 100 kΩ, DTCA = INTVCC or resistor
20
2
25
40
0.5
25
40
40
99
ns
ns
ns
ns
ns
ns
ns
ns
%
DRVSET = INTVCC
tON(MIN)
Output in dropout, FREQ = 0 V
DRVCC Load Regulation
Undervoltage Lockout
DRVCC Rising
Min
DRVSET = INTVCC
SW Falling to BGxx Rising Delay5
TGxx Minimum On-Time6
Maximum Duty Cycle
INTVCC LOW DROPOUT (LDO)
LINEAR REGULATORS
INTVCC Voltage for VIN and EXTVCC LDOs
Test Conditions/Comments
EXTVCC = 0 V for VIN LDO, 12 V for EXTVCC LDO
DRVSET = INTVCC
5.2
DRVSET = 0 V
4.8
DRVSET= 64.9 kΩ
4.5
DRVCC load current (ICC) = 0 mA to 100 mA, TA =
25°C
5.5
5.0
4.75
1
5.7
5.2
5.0
3
V
V
V
%
DRVUV = INTVCC
DRVUV = 0 V
DRVUV = floating
DRVUV = INTVCC
DRVUV = 0 V
DRVUV = floating
4.8
3.6
4.2
4.55
3.4
4.0
5.0
3.8
4.4
4.75
3.6
4.18
5.2
4.0
4.6
4.95
3.8
4.4
V
V
V
V
V
V
DRVUV = INTVCC or floating, TA = 25°C
DRVUV = 0 V, TA = 25°C
5.75
4.6
5.95
4.76
6.15
4.9
V
V
UVLO
DRVUV = INTVCC or floating
DRVUV = 0 V
390
220
mV
mV
Rev. 0 | 4 of 36
Data Sheet
LTC7891
SPECIFICATIONS
Table 1. Electrical Characteristics
Parameter
SPREAD SPECTRUM OSCILLATOR AND
PHASE-LOCKED LOOP
Fixed Frequency
Low Fixed Frequency
High Fixed Frequency
Programmable Frequency
Synchronizable Frequency Range
PLLIN Input High Level
PLLIN Input Low Level
Spread Spectrum Frequency Range
(Relative to fOSC)
Minimum Frequency
Maximum Frequency
PGOOD OUTPUT
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
VFB with Respect to Set Regulated Voltage
Symbol
Test Conditions/Comments
fOSC
PLLIN/SPREAD = 0 V
FREQ voltage (VFREQ) = 0 V, TA = 25°C
VFREQ = INTVCC
FREQ = 374 kΩ
FREQ = 75 kΩ, TA = 25°C
FREQ = 12.5 kΩ
PLLIN/SPREAD = external clock
fSYNC
Min
Typ
Max
Unit
320
2.0
370
2.25
100
500
3
420
2.5
kHz
MHz
kHz
kHz
MHz
MHz
V
V
450
0.1
2.2
550
3
0.5
PLLIN/SPREAD = INTVCC
0
20
PGOOD current (IPGOOD) = 2 mA, TA = 25°C
PGOOD = 5 V
VFB rising, TA = 25°C
Hysteresis
VFB falling, TA = 25°C
Hysteresis
PGOOD Delay for Reporting a Fault
0.2
7
–13
10
1.6
–10
1.6
25
%
%
0.4
±1
13
–7
V
µA
%
%
%
%
µs
1
This specification is not tested in production.
2
The LTC7891 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB.
3
SENSE− bias current is reflected to the input supply by the formula IVIN = ISENSE− × VOUT/(VIN × η), where η is the efficiency.
4
Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels.
5
SW falling to BGxx rising and BGxx falling to SW rising delay times are measured at the rising and falling thresholds on SW and BGxx of approximately 1 V. See Figure 41
and Figure 42.
6
The minimum on-time condition specified for inductor peak-to-peak ripple current is >40% of the maximum load current (IMAX) (see the Minimum On Time Considerations
section).
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Rev. 0 | 5 of 36
Data Sheet
LTC7891
ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings
Parameter
Rating
Input Supply (VIN)
RUN
BOOST
SW
BOOST to SW
BGUP, BGDN, TGUP, TGDN1
EXTVCC
DRVCC, INTVCC, BSTVCC
VFB
PLLIN/SPREAD, FREQ
TRACK/SS, ITH
DRVSET, DRVUV
MODE, ILIM, VPRG
PGOOD
DTCA, DTCB
SENSE+, SENSE–
SENSE+ to SENSE–
Continuous
20 V, the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device with
lower CMILLER provides higher efficiency. The synchronous FET
losses are greatest at high input voltage when the top switch duty
factor is low or during a short-circuit when the synchronous switch
is on close to 100% of the period.
CIN AND COUT SELECTION
The selection of the input capacitance (CIN) is usually based on the
worst case rms current drawn through the input network (battery,
fuse, or capacitor). The highest VOUT × IOUT product needs to
be used in Equation 14 to determine the maximum rms capacitor
current requirement.
In continuous mode, the source current of the top FET is a square
wave of duty cycle VOUT/VIN. To prevent large voltage transients,
use a low effective series resistance (ESR) capacitor sized for the
maximum rms current (IRMS). At IMAX, the maximum rms capacitor
current is given by Equation 14, as follows:
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CIN Required IRMS
∆ VOUT ≈ ∆ IL ESR +
1
8fCOUT
(15)
where:
f is the operating frequency.
ΔIL is the ripple current in the inductor.
The output ripple is highest at the maximum input voltage because
ΔIL increases with the input voltage.
SETTING THE OUTPUT VOLTAGE
The LTC7891 output voltages are set by an external feedback resistor divider carefully placed across the output, as shown in Figure
44 and Figure 45. The regulated output voltage is determined by
Equation 16, as follows:
VOUT = 0 . 8V 1 +
RB
RA
(16)
Place the RA and RB resistors close to the VFB pin to minimize PCB
trace length and noise on the sensitive VFB node. Take care to route
the VFB trace away from noise sources, such as the inductor or the
SW trace. To improve frequency response, a feedforward capacitor
(CFF) can be used.
The LTC7891 can be programmed to a fixed 12 V or 5 V output
through control of the VPRG pin. Figure 45 shows how the VFB
pin is issued to sense the output voltage in fixed output mode.
Tying VPRG to INTVCC or GND programs VOUT to 12 V or 5 V,
respectively. Floating VPRG sets VOUT to adjustable output mode
using external resistors.
Rev. 0 | 23 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
The current that flows through the R1 and R2 divider adds to the
shutdown, sleep, and active current of the LTC7891. Take care to
minimize the impact of this current on the overall efficiency of the
application circuit. Resistor values in the MΩ range can be required
to keep the impact on quiescent shutdown and sleep currents low.
SOFT START AND TRACKING (TRACK/SS PIN)
The startup of VOUT is controlled by the voltage on the TRACK/SS
pin. When the voltage on the TRACK/SS pin is less than the internal 0.8 V reference, the LTC7891 regulates the VFB pin voltage to
the voltage on the TRACK/SS pin instead of the internal reference.
The TRACK/SS pin can be used to program an external soft start
function, or to allow VOUT to track another supply during startup.
Figure 44. Setting Adjustable Output Voltage
Soft start is enabled by connecting a capacitor from the TRACK/SS
pin to GND. An internal 12 μA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin. The
LTC7891 regulates its feedback voltage (and hence VOUT) according to the voltage on the TRACK/SS pin, allowing VOUT to rise
smoothly from 0 V to its final regulated value. For a desired soft
start time (tSS), select a soft start capacitor (CSS) = tSS × 15 nF/ms.
Figure 45. Setting Fixed 12 V or 5 V Voltage
RUN PIN AND UNDERVOLTAGE LOCKOUT
The LTC7891 is enabled using the RUN pin. The RUN pin has a
rising threshold of 1.2 V with 100 mV of hysteresis. Pulling the RUN
pin below 1.08 V shuts down the main control loop and resets the
soft start. Pulling the RUN pin below 0.7 V disables the controller
and most internal circuits, including the INTVCC LDO regulators. In
this state, the LTC7891 draws only ≈1 μA of quiescent current.
The RUN pin is high impedance, must be externally pulled up or
pulled down, and is driven directly by logic. The RUN pin can
tolerate up to 100 V (the absolute maximum). Therefore, the pin
can be conveniently tied to VIN in always on applications where the
controller is enabled continuously and never shut down. Do not float
the RUN pin.
Alternatively, the TRACK/SS pin can be used to track another
supply during startup, as shown qualitatively in Figure 47 and
Figure 48. To track another supply, connect a resistor divider from
the leader supply (VX) to the TRACK/SS pin of the follower supply
(VOUT), as shown in Figure 49. During startup, VOUT tracks VX,
according to the ratio set by the resistor divider in Equation 19:
VX
VOUT
=
RA
RTRACKA
×
RTRACKA + RTRACKB
RA + RB
(19)
Set RTRACKA = RA and RTRACKB = RB for coincident tracking (VOUT =
VX during startup).
The RUN pin can also be configured as a precise UVLO on the
input supply with a resistor divider from VIN to GND, as shown in
Figure 46.
Figure 46. Using the RUN Pin as a UVLO
Figure 47. Coincident Tracking
The VIN UVLO thresholds can be computed by Equation 17 and
Equation 18, as follows:
UVLO Rising = 1 . 2V 1 +
R1
R2
UVLO Falling = 1 . 08V 1 +
analog.com
(17)
R1
R2
(18)
Rev. 0 | 24 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
to INTVCC programs INTVCC to 5.5 V. Tying the DRVSET pin
to GND programs INTVCC to 5.0 V. Place a 43 kΩ to 100 kΩ
resistor between DRVSET and GND to program the INTVCC voltage
between 4 V to 5.5 V, as shown in Figure 50.
Figure 48. Ratiometric Tracking
Figure 50. Relationship Between INTVCC Voltage and Resistor Value at the
DRVSET Pin
Table 6. DRVSET Pin Configurations and Voltage Settings
Figure 49. Using the TRACK/SS Pin for Tracking
INTVCC REGULATORS (OPTI-DRIVE)
The LTC7891 features two separate internal LDO linear regulators
that supply power at the INTVCC pin from either the VIN pin or
the EXTVCC pin, depending on the EXTVCC pin voltage and connections to the DRVSET and DRVUV pins. The DRVCC pin is the
supply pin for the FET gate drivers and must be connected to the
INTVCC pin. The VIN LDO regulator and the EXTVCC LDO regulator
regulate INTVCC between 4 V and 5.5 V, depending on how the
DRVSET pin is set. Each LDO regulator can provide a peak current
of at least 100 mA.
Bypass the INTVCC pin to GND with a minimum of 4.7 μF ceramic
capacitor, and place it as close as possible to the pin. It is recommended to place an additional 1 μF ceramic capacitor next to the
DRVCC pin and GND pin to supply the high frequency transient
currents required by the FET gate drivers.
The DRVSET pin programs the INTVCC supply voltage, and the
DRVUV pin selects the different INTVCC UVLO and EXTVCC
switchover threshold voltages. Table 6 summarizes the different
DRVSET pin configurations along with the voltage settings that go
with each configuration. Table 7 summarizes the different DRVUV
pin configurations and voltage settings. Tying the DRVSET pin
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DRVSET Pin
INTVCC Voltage (V)
GND
INTVCC
Resistor to GND, 43 kΩ to 100 kΩ
5.0
5.5
4 to 5.5
Table 7. DRVUV Pin Configurations and Voltage Settings
DRVUV INTVCC UVLO Rising and
Pin
Falling Thresholds (V)
EXTVCC Switchover Rising and
Falling Thresholds (V)
GND
3.8 and 3.6
Floating 4.4 and 4.18
INTVCC 5 and 4.75
4.76 and 4.54
5.95 and 5.56
5.95 and 5.56
High input voltage applications in which large FETs are driven at
high frequencies can exceed the maximum junction temperature
rating for the LTC7891. The INTVCC current, which is dominated
by the gate charge current, can be supplied by either the VIN LDO
regulator or the EXTVCC LDO regulator. When the voltage on the
EXTVCC pin is less than its switchover threshold (4.76 V or 5.95
V, as determined by the DRVUV pin), the VIN LDO regulator is
enabled. In this case, power dissipation for the IC is equal to VIN
× INTVCC current (IINTVCC). The gate charge current is dependent
on the operating frequency, as discussed in the Efficiency Considerations section. To estimate the junction temperature, use the
equation detailed in Table 2. For example, the LTC7891 INTVCC
current is limited to less than 39 mA from a 48 V supply when not
using the EXTVCC supply at an ambient temperature of 70°C, as
shown in Equation 20:
T J = 70°C + 39mA 48V 43°C/W = 150°C
(20)
Rev. 0 | 25 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
To prevent the maximum junction temperature from exceeding,
check the input supply current while operating in continuous conduction mode (MODE = INTVCC) at maximum VIN.
When the voltage applied to EXTVCC rises above its rising switchover threshold, the VIN LDO regulator turns off and the EXTVCC
LDO regulator enables. The EXTVCC LDO regulator remains on
as long as the voltage applied to EXTVCC remains above its
falling switchover threshold. The EXTVCC LDO regulator attempts to
regulate the INTVCC voltage to the voltage as programmed by the
DRVSET pin. Therefore, while EXTVCC is less than 5 V, the LDO
regulator is in dropout and the INTVCC voltage is approximately
equal to EXTVCC. When EXTVCC is greater than the programmed
voltage (up to an absolute maximum of 30 V), INTVCC is regulated
to the programmed voltage. Using the EXTVCC LDO regulator
allows the FET driver and control power to be derived from the
switching regulator output of the LTC7891 (4.7 V ≤ VOUT ≤ 30 V)
during normal operation, and from the VIN LDO regulator when the
output is out of regulation (for example, startup or short-circuit). If
more current is required through the EXTVCC LDO regulator than
is specified, add an external Schottky diode between the EXTVCC
and INTVCC pins. In this case, do not apply more than 6 V to the
EXTVCC pin.
Significant efficiency and thermal gains can be realized by powering
INTVCC from an output, because the VIN current resulting from the
driver and control currents is scaled by a factor of VOUT/(VIN ×
efficiency). For 5 V to 30 V regulator outputs, connect the EXTVCC
pin to VOUT. Tying the EXTVCC pin to an 8.5 V supply reduces the
junction temperature in Equation 20 from 125°C to the results given
by Equation 21, as follows:
T J = 70°C + 39mA 8 . 5V 43°C/W = 84°C
(21)
However, for 3.3 V and other low voltage outputs, additional circuitry is required to derive INTVCC power from the output.
The following list summarizes the four possible connections for
EXTVCC:
1. EXTVCC grounded. This connection causes the internal VIN
LDO regulator to power INTVCC, resulting in an efficiency penalty of up to 10% or more at high input voltages.
2. EXTVCC connected directly to the regulator output. This connection is the normal connection for an application with an
output range of 5 V to 30 V and provides the highest efficiency.
3. EXTVCC connected to an external supply. If an external supply
is available, it can be used to power EXTVCC, provided that it
is compatible with the FET gate drive requirements. This supply
can be higher or lower than VIN. However, a lower EXTVCC
voltage results in higher efficiency.
4. EXTVCC connected to an output derived boost or charge pump.
For regulators where outputs are below 5 V, efficiency gains
can still be realized by connecting EXTVCC to an output
derived voltage that is boosted to greater than the EXTVCC
switchover threshold.
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TOPSIDE FET DRIVER SUPPLY (CB)
An external bootstrap capacitor (CB) connected to the BOOST pin
supplies the gate drive voltage for the topside FET. CB in Figure 35
is charged through an internal switch from DRVCC when the SW pin
is low and the bottom FET is tuned on. The on resistance of the
internal switch is approximately 7 Ω. To deliver more charge current
to CB under certain operating conditions, place an external Schottky
diode between BSTVCC and BOOST to bypass most of the internal
switch resistance between DRVCC and BOOST.
When the topside FET turns on, the driver places the CB voltage
across the gate source of the desired FET, which enhances the
FET and turns on the topside switch. The switch node voltage,
SW, rises to VIN and the BOOST pin follows. With the topside FET
on, the boost voltage is above the input supply: VBOOST = VIN +
VINTVCC. The value of CB needs to be 100 times that of the total
input capacitance of the topside FETs. For a typical application, a
value of CB = 0.1 μF is sufficient.
MINIMUM ON TIME CONSIDERATIONS
The minimum on time (tON(MIN)) is the smallest time duration that
the LTC7891 is capable of turning on the top FET. tON(MIN) is
determined by internal timing delays and the gate charge required
to turn on the FET. Low duty cycle applications can approach this
minimum on time limit. Take care to ensure the results in Equation
22, as follows:
tON
MIN
<
VOUT
VIN × f
(22)
If the duty cycle falls below what can be accommodated by the
minimum on time, the controller begins to skip cycles. The output
voltage continues to be regulated, but the ripple voltage and current
increases. The minimum on time for the LTC7891 is approximately
40 ns. However, as the peak sense voltage decreases, the minimum on time gradually increases up to about 60 ns. This change
is of particular concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below the
minimum on time limit in this situation, a significant amount of cycle
skipping can occur with correspondingly larger current and voltage
ripple.
FAULT CONDITIONS: CURRENT LIMIT AND
FOLDBACK
The LTC7891 includes current foldback to reduce the load current
when the output is shorted to GND. If the output voltage falls below
70% of its regulation point, the maximum sense voltage is progressively lowered from 100% to 40% of its maximum value. Under
short-circuit conditions with low duty cycles, the LTC7891 begins
cycle skipping to limit the short-circuit current. In this situation, the
bottom FET dissipates most of the power, but less than in normal
operation. The short-circuit ripple current (ΔIL(SC)) is determined by
tON(MIN) ≈ 40 ns, the input voltage, and the inductor value given by
Equation 23, as follows:
Rev. 0 | 26 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
∆ IL
SC
= tON
MIN
× VIN /L
(23)
The resulting average short-circuit current (ISC) is given by Equation
24, as follows:
ISC = 40 % × ILIM
MAX
− ∆ IL
SC
/2
(24)
where ILIM(MAX) is the maximum peak inductor current.
FAULT CONDITIONS: OVERVOLTAGE
PROTECTION
If the output voltage rises 10% above the set regulation point, the
top FET turns off and the inductor current is not allowed to reverse
until the overvoltage condition clears.
FAULT CONDITIONS: OVERTEMPERATURE
PROTECTION
At higher temperatures, or in cases where the internal power
dissipation causes excessive self heating (such as a short from
INTVCC to GND), internal overtemperature shutdown circuitry shuts
down the LTC7891. When the internal die temperature exceeds
180°C, the INTVCC LDO regulator and gate drivers disable. When
the die cools to 160°C, the LTC7891 enables the INTVCC LDO
regulator and resumes operation, beginning with a soft start startup.
Avoid long-term overstress (TJ > 125°C) because it can degrade
the performance or shorten the life of the device.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTC7891 has an internal PLL that allows the turn on of the
top FET to be synchronized to the rising edge of an external clock
signal applied to the PLLIN/SPREAD pin.
Rapid phase locking can be achieved by using the FREQ pin to set
a free running frequency near the desired synchronization frequency. Before synchronization, the PLL is prebiased to the frequency
set by the FREQ pin. Consequently, the PLL only needs to make
minor adjustments to achieve phase lock and synchronization.
Although it is not required, placing the free running frequency near
the external clock frequency prevents the oscillator from passing
through a large range of frequencies as the PLL locks.
When synchronized to an external clock, the LTC7891 operates
in pulse skipping mode if it is selected by the MODE pin, or in
forced continuous mode otherwise. The LTC7891 is guaranteed to
synchronize to an external clock applied to the PLLIN/SPREAD pin
that swings up to at least 2.2 V and down to 0.5 V or less. Note
that the LTC7891 can only be synchronized to an external clock
frequency within the range of 100 kHz to 3 MHz.
EFFICIENCY CONSIDERATIONS
The percent efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. Analyzing individual losses is useful for determining what is limiting the efficiency
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and which change produces the most improvement. The percent
efficiency can be expressed by Equation 25, as follows:
%Efficiency = 100% − (L1 + L2 + L3 + …)
(25)
where L1, L2, L3, and so on, are the individual losses as a
percentage of input power.
Although all dissipative elements in the circuit produce losses, four
main sources usually account for most of the losses in LTC7891
circuits: IC VIN current, INTVCC regulator current, I2R losses, and
topside FET transition losses.
The VIN current is the dc supply current given in Table 1, which
excludes FET driver and control currents. Other than at light loads
in Burst Mode operation, VIN current typically results in a small
(1 μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing
a rapid drop in VOUT. No regulator can alter its delivery of current
quickly enough to prevent this sudden step change in output voltage, if the load switch resistance is low and it is driven quickly.
If the ratio of CLOAD to COUT is greater than 1:50, the switch rise
time must be controlled so that the load rise time is limited to
approximately CLOAD × 25 μs/μF. Therefore, a 10 μF capacitor
requires a 250 μs rise time, limiting the charging current to about
200 mA.
DESIGN EXAMPLE
As a design example, assume the nominal input voltage (VIN(NOMINAL)) = 12 V, VIN(MAX) = 22 V, VOUT = 3.3 V, IOUT = 20 A, and fSW = 1
MHz.
Take the following steps to design an application circuit:
1. Set the operating frequency. The frequency is not one of the
internal preset values. Therefore, a resistor from the FREQ pin
to GND is required, with a value given by Equation 27, as
follows:
(27)
RFREQ in kΩ = 37MHz
1MHz = 37kΩ
2. Determine the inductor value. Initially, select a value based on
an inductor ripple current of 30%. The inductor value can then
be calculated using Equation 28, as follows:
L=
VOUT
fSW ∆ IL
1−
VOUT
VIN NOMINAL
= 0 . 4μH
(28)
The highest value of the ripple current occurs at the maximum
input voltage. In this case, the ripple at VIN = 22 V is 35%.
3. Verify that the minimum on time of 40 ns is not violated. The
minimum on time occurs at VIN(MAX), as shown in Equation 29:
tON
MIN
=
VOUT
VIN MAX fSW
= 150ns
(29)
This time is sufficient to satisfy the minimum on time requirement. If the minimum on time is violated, the LTC7891 skips
pulses at high input voltage, resulting in lower frequency operaRev. 0 | 28 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
tion and higher inductor current ripple than desired. If undesirable, this behavior can be avoided by decreasing the frequency
(with the inductor value accordingly adjusted) to avoid operation
near the minimum on time.
4. Select the RSENSE resistor value. The peak inductor current is
the maximum dc output current plus half of the inductor ripple
current, or 20 A × (1 + 0.30/2) = 23 A in this case. The RSENSE
resistor value can then be calculated based on the minimum
value for the maximum current sense threshold (45 mV for ILIM
= float), given by Equation 30, as follows:
RSENSE ≤
45mV
23A
≅ 2mΩ
(30)
To allow for additional margin, a lower value RSENSE can be
used (for example, 1.8 mΩ). However, be sure that the inductor saturation current has sufficient margin above VSENSE(MAX)/
RSENSE, where the maximum value of 55 mV is used for
VSENSE(MAX).
5. Select the feedback resistors. If light load efficiency is required,
high value feedback resistors can be used to minimize the current due to the feedback divider. However, in most applications,
a feedback divider current in the range of 10 μA to 100 μA or
more is acceptable. For a 50 μA feedback divider current, RA =
0.8 V/50 μA = 16 kΩ. RB can then be calculated as RB = RA(3.3
V/0.8 V – 1) = 50 kΩ.
6. Select the FETs. The best way to evaluate FET performance
in a particular application is to build and test the circuit on the
bench, facilitated by an LTC7891 evaluation board. However,
an educated guess about the application is helpful to initially
select FETs. Because this is a high current, low voltage application, I2R losses likely dominate over transition losses for
the top FET. Therefore, choose a FET with lower RDS(ON) as
opposed to lower gate charge to minimize the combined loss
terms. The bottom FET does not experience transition losses,
and its power loss is generally dominated by I2R losses. For
this reason, the bottom FET is typically chosen to be of lower
RDS(ON) and higher gate charge than the top FET.
Due to the high current in this application, two FETs may be
needed in parallel to more evenly balance the dissipated power
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and to lower the RDS(ON). When using silicon MOSFETs, be
sure to select logic level threshold MOSFETs, because the gate
drive voltage is limited to 5.5 V (INTVCC).
7. Select the input and output capacitors. CIN is chosen for an
rms current rating of at least 10 A (IOUT/2, with margin) at
temperature. COUT is chosen with an ESR of 3 mΩ for low
output ripple. Multiple capacitors connected in parallel may be
required to reduce the ESR to this level. The output ripple in
continuous mode is highest at the maximum input voltage. The
output voltage ripple (VORIPPLE) due to ESR is approximately
given by Equation 31, as follows:
VORIPPLE = ESR × ΔIL = 3mΩ × 6A = 18mVp-p
(31)
On the 3.3 V output, 18 mVp-p is equal to 0.55% of the
peak-to-peak voltage ripple.
8. Determine the bias supply components. Because the regulated
output is not greater than the EXTVCC switchover threshold,
it cannot be used to bias INTVCC. However, if another 5 V
supply is available, connect that supply to EXTVCC to improve
the efficiency. For a 6.7 ms soft start, select a 0.1 μF capacitor
for the TRACK/SS pin. As a first pass estimate for the bias
components, select the INTVCC capacitance (CINTVCC) = 4.7 μF
and CB = 0.1 μF.
9. Determine and set application specific parameters. Set the
MODE pin based on the trade-off of light load efficiency and
constant frequency operation. Set the PLLIN/SPREAD pin
based on whether a fixed, spread spectrum, or phase-locked
frequency is desired. The RUN pin can be used to control
the minimum input voltage for regulator operation, or it can
be tied to VIN for always on operation. Use ITH compensation
components from the typical applications as a first guess, check
the transient response for stability, and modify as necessary.
PCB LAYOUT CHECKLIST
Figure 51 shows the current waveforms present in the various
branches of the synchronous regulators operating in the continuous
mode.
Rev. 0 | 29 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
Figure 51. Branch Current Waveform
When laying out the PCB, use the following checklist to ensure
proper operation of the IC.
1. Route the BGUP and BGDN traces together and connect them
as close as possible to the bottom FET gate. If using gate
resistors, connect the resistor connections to the FET gate as
close as possible to the FET. Connecting BGUP and BGDN
further away from the bottom FET gate can cause inaccuracies
in the dead time control circuit of the LTC7891. Route the
TGUP and TGDN traces together and connect them as close as
possible to the top FET gate.
2. The combined IC GND pin and the GND return of CINTVCC
must return to the combined COUT negative terminals. The path
formed by the top N-channel FET and the CIN capacitor must
have short leads and PCB trace lengths. Connect the output capacitor negative terminals as close as possible to the negative
terminals of the input capacitor by placing the capacitors next to
each other and away from the loop.
3. Connect the LTC7891 VFB pin resistive dividers to the positive
terminals of COUT and the signal GND. Place the divider close
to the VFB pin to minimize noise coupling into the sensitive VFB
node. The feedback resistor connections must not be along the
high current input feeds from the input capacitors.
4. Route the SENSE− and SENSE+ leads together with minimum
PCB trace spacing. Route these traces away from the high
frequency switching nodes on an inner layer, if possible. The
filter capacitor between SENSE+ and SENSE− must be as close
as possible to the IC. Ensure accurate current sensing with
Kelvin connections at the sense resistor.
5. Connect the INTVCC decoupling capacitor close to the IC,
between the INTVCC and the power GND pin. This capacitor
carries the current peaks of the FET drivers. Place an additional
1 μF ceramic capacitor next to the DRVCC and GND pins to
help improve noise performance.
6. Keep the switching node (SW), top gate nodes (TGUP and
TGDN), and boost node (BOOST) away from sensitive small
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signal nodes, especially from the voltage and current sensing
feedback pins. All of these nodes have large and fast moving
signals. Therefore, keep the nodes on the output side of the
LTC7891 and ensure they occupy the minimum PCB trace area.
7. Use a modified star ground technique: a low impedance, large
copper area central grounding point on the same side of the
PCB as the input and output capacitors, with tie ins for the
bottom of the INTVCC decoupling capacitor, the bottom of the
voltage feedback resistive divider, and the GND pin of the IC.
PCB LAYOUT DEBUGGING
Use a dc to 50 MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output switching node
(the SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper
performance over the operating voltage and current range expected
in the application. The frequency of operation is maintained over
the input voltage range down to dropout and until the output load
drops below the low current operation threshold, typically 25% of
the maximum designed current level in Burst Mode operation.
The duty cycle percentage is maintained from cycle to cycle in
a well designed, low noise PCB implementation. Variation in the
duty cycle at a subharmonic rate can suggest noise pickup at the
current or voltage sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame an improper
PCB layout if regulator bandwidth optimization is not required.
Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout
circuit by further lowering VIN while monitoring the outputs to
verify operation. Investigate whether any problems exist only at
higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents, look for
capacitive coupling between the BOOST, SW, TGxx, and possibly
BGxx connections and the sensitive voltage and current pins. Place
the capacitor across the current sensing pins next to the pins of the
Rev. 0 | 30 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
IC. This capacitor helps to minimize the effects of differential noise
injection due to high frequency capacitive coupling. If problems
are encountered with high current output loading at lower input
voltages, look for inductive coupling between CIN, the top FET, and
the bottom FET components to the sensitive current and voltage
sensing traces. In addition, investigate the common GND path
voltage pickup between these components and the GND pin of the
IC.
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A problem that can be missed in an otherwise properly working
switching regulator, results when the current sensing leads are
hooked up backwards. The output voltage under this improper
hookup is maintained, but the advantages of current mode control
are not realized. Compensation of the voltage loop is more sensitive to component selection. This behavior can be investigated by
temporarily shorting out the current sensing resistor. The regulator
maintains control of the output voltage.
Rev. 0 | 31 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
TYPICAL APPLICATIONS
Figure 52. High Efficiency, 12 VOUT, 12 A, 1 MHz, Step-Down Regulator Using GaN FETs
Figure 53. VOUT Efficiency and Power Loss vs. Load Current for Figure 52
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Rev. 0 | 32 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
Figure 54. High Efficiency 12 VOUT, 10 A, 2 MHz, Step-Down Regulator Using GaN FETs
Figure 55. VOUT Efficiency vs. Load Current for Figure 54
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Rev. 0 | 33 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
Figure 56. High Efficiency, 24 VOUT, 1 MHz, Step-Down Regulator Using GaN FETs
Figure 57. VOUT Efficiency vs. Load Current for Figure 56
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Rev. 0 | 34 of 36
Data Sheet
LTC7891
APPLICATIONS INFORMATION
Figure 58. High Efficiency, 24 V, 500 kHz, Step-Down Regulator Using GaN FETs
RELATED PRODUCTS
Table 8. Related Products
Model
Description
LTC7803
40 V, low IQ, 3 MHz, synchronous step-down controller with
spread spectrum
LTC7805
LTC7802
LTC7800
LTC7804
LTC3866
LTC3833
LTC7801
analog.com
Comments
PLL fixed frequency of 100 kHz to 3 MHz, 4.5 V ≤ VIN ≤ 40 V, IQ = 12 µA, 0.8 V ≤ VOUT ≤
40 V, 3 mm × 3 mm, 16-lead quad flat no lead (QFN) package, 16-lead mini small outline
package (MSOP)
40 V, dual, low IQ, two phase, synchronous step-down
PLL fixed frequency of 100 kHz to 3 MHz, 4.5 V ≤ VIN ≤ 40 V, IQ = 14 µA, VOUT up to 40 V, 4
controller with 100% duty cycle
mm × 5 mm, 28-lead QFN package
40 V, dual, low IQ, 3 MHz, two phase, synchronous step4.5 V ≤ VIN ≤ 40 V, VOUT up to 40 V, IQ = 12 µA, PLL fixed frequency of 100 kHz to 3 MHz, 4
down controller with spread spectrum
mm × 5 mm, 28-lead QFN package
60 V, low IQ, high frequency, synchronous step-down
4 V ≤ VIN ≤ 60 V, 0.8 V ≤ VOUT ≤ 24 V, IQ = 50 µA, PLL fixed frequency of 320 kHz to 2.25
controller
MHz, 3 mm × 4 mm, 20-lead QFN package
40 V, low IQ, 3 MHz, synchronous boost controller, 100% duty 4.5 V (down to 1 V after startup) ≤ VIN ≤ 40 V, VOUT up to 40 V, IQ = 14 µA, PLL fixed
cycle capable
frequency of 100 kHz to 3 MHz, 3 mm × 3 mm, 16-lead QFN package, 16-lead MSOP
38 V, synchronous step-down controller with sub mΩ DCR
4.5 V ≤ VIN ≤ 38 V, 0.6 V ≤ VOUT ≤ 3.5 V, PLL fixed frequency of 250 kHz to 770 kHz, 4 mm ×
sensing and differential output sense
4 mm, 24-lead QFN package, 24-lead thin shrink small outline package (TSSOP)
38 V, synchronous step-down controller with differential
4.5 V ≤ VIN ≤ 38 V, 0.6 V ≤ VOUT ≤ 5.5 V, PLL fixed frequency of 200 kHz to 2 MHz, 3 mm × 4
output voltage sensing
mm, 20-lead QFN package, 20-lead TSSOP
150 V, low IQ, synchronous step-down dc-to-dc controller
4.5 V ≤ VIN ≤ 140 V, 150 VPK, 0.8 V ≤ VOUT ≤ 60 V, IQ = 40 µA, PLL fixed frequency of 50 kHz
to 900 kHz, 4 mm × 5 mm, 24-lead QFN package, 24-lead TSSOP
Rev. 0 | 35 of 36
Data Sheet
LTC7891
OUTLINE DIMENSIONS
Figure 59. 28-Lead Plastic Side Wettable QFN
4 mm × 5 mm
(05-08-1682)
Dimensions shown in millimeters
Updated: March 16, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package Option
LTC7891RUFDM#PBF
LTC7891RUFDM#TRPBF
-40°C to +150°C
-40°C to +150°C
28-Lead QFN (4mm x 5mm, Plastic Side Wettable)
28-Lead QFN (4mm x 5mm, Plastic Side Wettable)
Tube, 73
Reel, 2500
05-08-1682
05-08-1682
1
All models are RoHS compliant parts.
EVALUATION BOARDS
Model1
Description
DC2995A
Evaluation Board
1
The DC2995A is an RoHS compliant part.
©2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. 0 | 36 of 36
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