19-2740; Rev 1; 6/09
KIT
ATION
EVALU
E
L
B
A
AVAIL
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
The MAX1960/MAX1961/MAX1962 high-current, highefficiency voltage-mode step-down DC-DC controllers
operate from a 2.35V to 5.5V input and generate output
voltages down to 0.8V at up to 20A. An on-chip charge
pump generates a regulated 5V for MOSFET drive.
Additionally, adaptive dead-time drivers allow a
wide variety of MOSFETs to be used without risking
shoot-through.
Fixed-frequency PWM operation and external synchronization make these controllers suitable for telecom
and datacom applications. The operating frequency is
programmable to either 500kHz or 1MHz, or from
450kHz to 1.2MHz with an external clock. A clock output
is provided to synchronize another converter for 180°
out-of-phase operation. A high closed-loop bandwidth
provides excellent transient response for applications
with dynamic loads.
Lossless current sensing in the MAX1960 and
MAX1961 is achieved by monitoring the drain-to-source
voltage of the low-side external FET. The current limit is
scalable to accommodate a wide variety of MOSFETs
and load currents. The MAX1962 has 10% accurate
sense-resistor-based current limiting.
The MAX1960 and MAX1962 have an adjustable output
voltage from 0.8V to 4.95V. The MAX1961 and
MAX1962 have four preset output voltages (1.5V, 1.8V,
2.5V, and 3.3V) and feature 0.5% voltage accuracy
over temperature, line, and load variations. The
MAX1960 and MAX1961 also feature voltage-margining
control inputs that shift the output voltage up or down
by 4% for system testing.
Features
0.5% Accurate Output
Operates from 2.35V to 5.5V Supply
Generates Low Output Voltage Down to 0.8V
On-Chip Charge Pump Provides 5V Gate Drive
Ceramic or Electrolytic Capacitors
94% Efficiency
External Synchronization from 450kHz to 1.2MHz
500kHz/1MHz Fixed-Frequency PWM Operation
Fast Transient Response
Two Converters Can Operate 180° Out-of-Phase
±4% Voltage Margining for System Test
10% Accurate Current Sensing (MAX1962)
Adaptive Dead Time Prevents Shoot-Through
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX1960EEP
PART
-40°C to +85°C
20 QSOP
MAX1961EEP
-40°C to +85°C
20 QSOP
MAX1962EEP
-40°C to +85°C
20 QSOP
Typical Operating Circuit
C+
INPUT
2.35V TO 5.5V
CAVDD
VCC
MAX1960
VDD
Applications
VOLTAGE
MARGINING
AND ON/OFF
ASIC, FPGA, DSP, and CPU Core and I/O Voltages
Cellular Base Stations
CTL1
BST
CTL2
COMP
DH
REF
LX
Telecom and Network Equipment
OUTPUT
0.8 TO 0.87 ✕ VIN
UP TO 20A
DL
Server and Storage Systems
GND
PGND
ILIM
OPTIONAL
SYNCHRONIZATION
Pin Configurations and Selector Guide appear at the end
of the data sheet.
CLKOUT
180° OUT-OF-PHASE
FSET/SYNC
CLKOUT
FB
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1960/MAX1961/MAX1962
General Description
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
ABSOLUTE MAXIMUM RATINGS
VCC, CTL_, CS, FSET/SYNC, SEL, EN,
OUT to GND ..........................................................-0.3V to +6V
ILIM, COMP, REF, FB, CLKOUT,
C- to GND ..............................................-0.3V to VAVDD + 0.3V
C+ to GND.............-0.3V to higher of VVCC + 1V or VVDD + 0.3V
VDD, AVDD to GND ..............-0.3V to higher of VVCC - 0.3V or 6V
DL to PGND ................................................-0.3V to VVDD + 0.3V
BST to GND ............................................................-0.3V to +12V
DH to LX ...................................................................-0.3V to +6V
LX to BST..................................................................-6V to +0.3V
PGND to GND, or VDD to AVDD ............................-0.3V to +0.3V
Continuous Power Dissipation (TA = +70°C)
20-Pin QSOP (derate up to +70°C)..............................727mW
20-Pin QSOP (derate above +70°C) ........................9.1mW/°C
Operating Temperature Range (Extended).........-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VVCC = 3.3V, Circuits of Figures 9–12, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
VCC Input Voltage Range
MIN
TYP
MAX
UNITS
2.35
5.5
V
VCC Input Voltage UVLO
Rising or falling, hysteresis = 33mV (typ)
1.95
2.3
V
VDD Input Voltage UVLO
Rising or falling, hysteresis = 44mV (typ)
3.9
4.45
V
Output Voltage
0.8
MAX1960/MAX1962 (measured at FB)
0.796
V
0.800
0.804
SEL = GND
MAX1961/
SEL = REF
MAX1962 (FB = VDD),
SEL not connected
measured at output
SEL = VDD
Positive Voltage-Margining Shift
MAX1960/MAX1961
Negative Voltage-Margining Shift
MAX1960/MAX1961
Load Regulation Error
0V to full load
0.08
%
Line Regulation Error
VVCC = 2.7V to 5.5V
0.1
%
DC Output Accuracy
FB Input Bias Current
1.500
1.508
1.800
1.809
2.487
2.500
2.514
3.272
3.300
3.336
+3.8
+4
+4.2
%
-3.8
-4
-4.2
%
1
In shutdown
DC-DC Soft-Start Time
Switching Frequency
+0.2
µA
3
mS
10
100
Ω
1280
cycles
FSET/SYNC = GND
450
500
550
FSET/SYNC = VCC
880
1000
1120
SYNC Frequency Range
V
2
-0.2
Feedback Transconductance
COMP Discharge Resistance
1.492
1.791
450
1200
kHz
kHz
Maximum Duty Cycle
f = 1MHz
80
83
%
Maximum Duty Cycle
f = 500kHz
90
92
%
Quiescent Supply Current
11
Shutdown Supply Current
2
_______________________________________________________________________________________
15
mA
15
µA
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
(VVCC = 3.3V, Circuits of Figures 9–12, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
VDD Output Voltage
Reference Voltage (No Load)
Reference Load Regulation
MAX
UNITS
2.7V ≤ VVCC ≤ 5.5V, ILOAD = 1mA to 50mA
CONDITIONS
4.75
MIN
5.25
V
2.35V ≤ VVCC ≤ 2.7V, ILOAD = 1mA to 35mA, C1
= 4.7µF, C6 = 22µF (Note 1)
4.45
5.25
V
2.35V ≤ VVCC ≤ 3.6V with tripler, ILOAD = 1 to
50mA (circuit of Figure 12) (Note 1)
4.75
5.25
V
1.291
V
mV
1.269
TYP
VOUT = 0.8V
44
1.280
3
53
VOUT = 2.0V
45
50
55
VOUT = 3.3V
38
48
58
38
50
68
mV
-50µA to +50µA
Positive Current-Limit Threshold
(VPGND - VLX)
MAX1962
Negative Current-Limit Threshold
(VLX - VPGND)
MAX1962, VOUT = 0.8V to 3.3V
62
mV
CS Bias Current
MAX1962, VCS = 3.3V
20
50
µA
OUT Bias Current
MAX1961/MAX1962, VOUT = 3.3V
30
50
µA
Current-Limit Threshold (Positive
Direction, Fixed, VPGND - VLX)
MAX1960/MAX1961, ILIM = VDD
58
74
90
mV
Current-Limit Threshold (Negative
Direction, Fixed, VLX - VPGND)
MAX1960/MAX1961, ILIM = VDD
50
67
85
mV
Current-Limit Threshold (Positive
Direction, Adjustable, VPGND - VLX)
MAX1960/MAX1961, RILIM = 160kΩ
100
114
135
RILIM = 400kΩ
250
279
306
Current-Limit Threshold (Negative
Direction, Adjustable, VLX - VPGND)
MAX1960/MAX1961, RILIM = 160kΩ
90
107
125
RILIM = 400kΩ
245
271
296
Thermal-Shutdown Threshold
DH Gate-Driver On-Resistance
DL Gate-Driver On-Resistance (Pullup)
DL Gate-Driver On-Resistance (Pulldown)
15°C hysteresis
VBST - VLX = 5V, pulling up or down
DL high state
DL low state
DH falling to DL rising
+160
1.8
1.8
0.5
35
3.5
3.5
1.6
Minimum Adaptive Dead Time
FSET/SYNC Pulse Width
FSET/SYNC Rise/Fall Time
DH rising to DL falling
200
Minimum low time (Note 1)
200
VVCC = 2.35V to 5.5V
CTL_, FSET/SYNC, EN Input Low Voltage
VVCC = 2.35V to 5.5V
CTL_, FSET/SYNC, EN Input Current
CLKOUT VOL
100
2.0
CLKOUT VOH
Sourcing 1mA
CLKOUT Rise/Fall Time
CLOAD = 100pF (Note 1)
0.01
VVCC 0.2V
ns
V
-1
Sinking 1mA
°C
Ω
Ω
Ω
ns
(Note 1)
CTL_, FSET/SYNC, EN Input High Voltage
mV
ns
26
Minimum high time (Note 1)
mV
0.8
V
+1
µA
0.1
V
VVCC 0.01V
V
40
ns
_______________________________________________________________________________________
3
MAX1960/MAX1961/MAX1962
ELECTRICAL CHARACTERISTICS (continued)
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
ELECTRICAL CHARACTERISTICS
(VVCC = 3.3V, Circuits of Figures 9–12, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
VCC Input Voltage Range
MAX
UNITS
2.35
MIN
TYP
5.50
V
VCC Input Voltage UVLO
Rising or falling
1.95
2.3
V
VDD Input Voltage UVLO
Rising or falling
3.90
4.45
V
Output Voltage
0.8
MAX1960/MAX1962 (measured at FB)
DC Output Accuracy
MAX1961/MAX1962
(FB = VDD),
measured at output
Positive Voltage-Margining Shift
MAX1960/MAX1961
Negative Voltage-Margining Shift
MAX1960/MAX1961
SEL = GND
1.508
SEL = REF
1.789
1.809
SEL not connected
2.482
2.517
SEL = VDD
3.272
3.339
3.8
4.2
V
%
-3.8
-4.2
%
+0.2
µA
1
3
mS
100
Ω
FSET/SYNC = GND
450
550
FSET/SYNC = VCC
880
1120
450
1200
Feedback Transconductance
Switching Frequency
0.805
-0.2
FB Input Bias Current
COMP Discharge Resistance
V
0.795
1.492
In shutdown
SYNC Frequency Range
kHz
kHz
Maximum Duty Cycle
f = 1MHz
80
%
Maximum Duty Cycle
f = 500kHz
90
%
Quiescent Supply Current
15
mA
Shutdown Supply Current
15
µA
VDD Output Voltage
2.7V ≤ VVCC ≤ 5.5V, ILOAD = 1mA to 50mA
4.75
5.25
2.35V ≤ VVCC ≤ 2.7V, ILOAD = 1mA to 35mA,
C1 = 4.7µF, C6 = 22µF
4.45
5.25
2.35V ≤ VVCC ≤ 3.6V with tripler, ILOAD = 1mA
to 50mA (circuit of Figure 12)
4.75
5.25
1.267
1.291
V
Reference Voltage (No Load)
V
Positive Current-Limit Threshold
(VCS - VOUT)
MAX1962, VOUT = 2V
45
56
mV
Negative Current-Limit Threshold
(VOUT - VCS)
MAX1962, VOUT = 2V
42
64
mV
CS Bias Current
MAX1962, VCS = 3.3V
50
µA
OUT Bias Current
MAX1961/MAX1962, VOUT = 3.3V
50
µA
Current-Limit Threshold (Positive
Direction, Fixed, VPGND - VLX)
MAX1960/MAX1961, ILIM = VDD
58
90
mV
Current-Limit Threshold (Negative
Direction, Fixed, VLX - VPGND)
MAX1960/MAX1961, ILIM = VDD
50
85
mV
Current-Limit Threshold (Positive
Direction, Adjustable, VPGND - VLX)
4
MAX1960/MAX1961, RILIM = 160kΩ
100
135
RILIM = 400kΩ
250
306
_______________________________________________________________________________________
mV
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
(VVCC = 3.3V, Circuits of Figures 9–12, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current-Limit Threshold (Negative
Direction, Adjustable, VLX - VPGND)
MAX1960/MAX1961, RILIM = 160kΩ
90
125
RILIM = 400kΩ
245
296
DH Gate-Driver On-Resistance
VBST - VLX = 5V, pulling up or down
3.5
Ω
DL Gate-Driver On-Resistance (Pullup)
DL high state
3.5
Ω
DL Gate-Driver On-Resistance (Pulldown)
DL low state
1.6
Ω
FSET/SYNC Pulse Width
Minimum high time
200
Minimum low time
200
FSET/SYNC Rise/Fall Time
CTL_, FSET/SYNC, EN Input High Voltage
VVCC = 2.35V to 5.5V
CTL_, FSET/SYNC, EN Input Low Voltage
VVCC = 2.35V to 5.5V
CTL_, FSET/SYNC, EN Input Current
CLKOUT VOL
Sinking 1mA
CLKOUT VOH
Sourcing 1mA
CLKOUT Rise/Fall Time
CLOAD = 100pF
ns
100
ns
0.8
V
+1
µA
0.1
V
2.0
-1
mV
V
VVCC 0.2V
V
40
ns
Note 1: Guaranteed by design.
Note 2: Specifications at -40°C are guaranteed by design, and not production tested.
_______________________________________________________________________________________
5
MAX1960/MAX1961/MAX1962
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(Circuit of Figure 9, TA = +25°C, unless otherwise noted.)
80
VOUT = 1.8V
70
80
VOUT = 2.5V
VOUT = 1.8V
70
VOUT = 1.5V
100
90
VOUT = 1.8V
VOUT = 1.5V
70
60
60
50
50
100
10
0.1
1
0.1
100
10
1
100
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT WITH
15A 500kHz CIRCUIT, 5V INPUT
OUTPUT VOLTAGE
vs. INPUT VOLTAGE, 1MHz
OUTPUT VOLTAGE
vs. INPUT VOLTAGE, 500kHz
VOUT = 1.8V
VOUT = 1.5V
2.5
2.5V OUTPUT
DROPOUT
2.0
1.5
1.8V OUTPUT
1.5V OUTPUT
1.0
1.2V OUTPUT
3.5
3.3V OUTPUT
3.0
OUTPUT VOLTAGE (V)
VOUT = 2.5V
70
3.0
OUTPUT VOLTAGE (V)
90
3.3V OUTPUT
MAX1960 toc05
VOUT = 3.3V
80
3.5
MAX1960 toc04
100
2.5
MAX1960 toc06
50
1
80
VOUT = 1.5V
60
0.1
VOUT = 2.5V
MAX1960 toc03
90
EFFICIENCY (%)
90
VOUT = 3.3V
EFFICIENCY (%)
VOUT = 2.5V
EFFICIENCY (%)
100
MAX1960 toc01
100
EFFICIENCY vs. LOAD CURRENT WITH
15A 500kHz CIRCUIT, 3.3V INPUT
EFFICIENCY vs. LOAD CURRENT WITH
15A 1MHz CIRCUIT, 5V INPUT
MAX1960 toc02
EFFICIENCY vs. LOAD CURRENT WITH
15A 1MHz CIRCUIT, 3.3V INPUT
EFFICIENCY (%)
2.5V OUTPUT
DROPOUT
2.0
1.5
1.8V OUTPUT
1.5V OUTPUT
1.0
1.2V OUTPUT
60
0.5
0.5
15A LOAD
15A LOAD
0
0
0.1
1
100
10
2.7
3.1
LOAD CURRENT (A)
3.5
3.9
4.3
4.7
5.1
2.7
5.5
3.1
3.5
FB REGULATION VOLTAGE
vs. LOAD CURRENT
0.802
4.3
4.7
FREQUENCY
vs. INPUT VOLTAGE
1200
MAX1960 toc07
0.803
3.9
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1100
FSET/SYNC = VCC
MAX1960 toc08
50
1000
0.801
FREQUENCY (kHz)
FB VOLTAGE (V)
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
0.800
0.799
900
800
700
600
FSET/SYNC = GND
0.798
500
0.797
0
5
10
LOAD CURRENT (A)
6
15
20
400
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
_______________________________________________________________________________________
5.5
5.1
5.5
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
600
500
400
300
FSET/SYNC = GND
200
5.0
4.9
VIN = 3.3V
4.8
4.7
VIN = 2.5V
4.6
C1 = 1µF
C6 = 4.7µF
5.1
MAX1960 toc11
5.1
5.2
CHARGE-PUMP OUTPUT VOLTAGE (V)
700
C1 = 0.47µF
C6 = 2.2µF
MAX1960 toc10
FSET/SYNC = VCC
800
5.0
4.9
4.8
4.7
VIN = 2.5V
4.6
VIN = 3.3V
100
4.5
4.5
-15
10
35
60
0
85
50
100
0
200
150
C10, C11, C12 = 0.47µF
C6 = 2.2µF
5.1
5.0
4.9
VIN = 2.5V
4.8
4.7
4.6
100
150
200
TRIPLER CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 500kHz
5.2
CHARGE-PUMP OUTPUT VOLTAGE (V)
5.2
MAX1960 toc12
TRIPLER CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 1MHz
50
CHARGE-PUMP LOAD CURRENT (mA)
CHARGE-PUMP LOAD CURRENT (mA)
TEMPERATURE (°C)
CHARGE-PUMP OUTPUT VOLTAGE (V)
C10, C11, C12 = 1µF
C6 = 4.7µF
5.1
5.0
4.9
VIN = 2.5V
4.8
4.7
4.6
CIRCUIT OF FIGURE 12
CIRCUIT OF FIGURE 12
4.5
4.5
10
20
30
40
50
0
10
20
30
40
CHARGE-PUMP LOAD CURRENT (mA)
CHARGE-PUMP LOAD CURRENT (mA)
MAX1960/MAX1961
CURRENT-LIMIT THRESHOLD
VOLTAGE vs. TEMPERATURE
MAX1962
CURRENT-LIMIT THRESHOLD
VOLTAGE vs. TEMPERATURE
RILIM = 390kΩ
300
250
200
150
ILIM = VDD
100
50
0
52.0
50
MAX1960 toc15
350
CURRENT-LIMIT THRESHOLD VOLTAGE (mV)
0
MAX1960 toc14
-40
MAX1960 toc13
0
CURRENT-LIMIT THRESHOLD VOLTAGE (mV)
FREQUENCY (kHz)
900
5.2
CHARGE-PUMP OUTPUT VOLTAGE (V)
1000
MAX1960 toc09
1100
CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 500kHz
CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 1MHz
FREQUENCY vs. TEMPERATURE
51.5
51.0
50.5
50.0
49.5
49.0
48.5
48.0
47.5
47.0
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX1960/MAX1961/MAX1962
Typical Operating Characteristics (continued)
(Circuit of Figure 9, TA = +25°C, unless otherwise noted.)
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Typical Operating Characteristics (continued)
(Circuit of Figure 9, TA = +25°C, unless otherwise noted.)
VOLTAGE-MARGINING STEP RESPONSE
7.5A TO 15A TO 7.5A LOAD TRANSIENT
MAX1960 toc17
MAX1960 toc16
CTL1
5V/div
5V/div
CTL2
50mV/div
VOUT
IIN
ILOAD
5A/div
200mA/div
VOUT
200mV/div
CIRCUIT OF FIGURE 13
50µs/div
20µs/div
MAX1960/MAX1961
SHORT-CIRCUIT WAVEFORMS
STARTUP/SHUTDOWN WAVEFORMS
MAX1960 toc19
MAX1960 toc18
VOUT
IIN
10A/div
IL
10A/div
VOUT
CIRCUIT OF FIGURE 13
2V/div
IL
20A/div
IIN
5A/div
1V/div
50µs/div
1ms/div
MAX1962
SHORT-CIRCUIT WAVEFORMS
SYNC TIMING WAVEFORMS
MAX1960 toc21
MAX1960 toc20
DH
MASTER
IIN
10A/div
10A/div
IL
VOUT
VIN = 5V
VOUT = 3.3V
50µs/div
8
2V/div
DL
MASTER
CLKOUT
MASTER/
SYNC
SLAVE
DH
SLAVE
DL
SLAVE
200ns/div
_______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
PIN
NAME
FUNCTION
Clock Output. Connect to FSET/SYNC of a second converter to operate 180° out-ofphase. CLKOUT swings from VCC to GND. CLKOUT is low in shutdown (see the
Operating Frequency and Synchronization section).
MAX1960 MAX1961 MAX1962
1
1
1
CLKOUT
2
2
2
FSET/SYNC
3
3
—
ILIM
—
—
3
EN
Enable. Drive high for normal operation. Drive low or connect to GND for shutdown mode.
—
4
4
SEL
Preset Output Voltage Select. Allows the output to be set to one of four preset
voltages (1.5V, 1.8V, 2.5V, and 3.3V). For the MAX1962, FB must be connected to
VDD if SEL is to be used (see the Setting the Output Voltage section).
4
—
—
N.C.
No Connection. Not internally connected.
—
8
5
OUT
Output. Connect to the output. Used to sense the output voltage for internal
feedback and current sense.
5
5
—
CTL1
6
6
—
CTL2
—
—
6
CS
7
7
7
AVDD
8
—
8
FB
Frequency Set and Synchronization. Connect to GND for 500kHz operation,
connect to VCC for 1MHz operation, or drive with clock signal to synchronize
(between 450kHz and 1200kHz).
Current Limit. Connect a resistor from ILIM to GND to set the current-sense
threshold voltage. Connect ILIM to VDD to select the default threshold of 75mV.
Control Pins. Controls voltage margining and shutdown. Connect both CTL1 and
CTL2 high for normal operation. Connect both CTL1 and CTL2 low for shutdown.
Connect CTL1 high and CTL2 low for +4% voltage margining. Connect CTL1 low
and CTL2 high for -4% voltage margining. If voltage margining is not to be used,
connect CTL1 and CTL2 together and use to enable/shutdown the device.
Current-Sense Input. Connect to the junction of the current-sense resistor and the
inductor. The MAX1962 current-sense threshold is 50mV measured from CS to OUT.
Filtered Supply from VDD. Connect a 1µF bypass capacitor. AVDD is forced to VCC
in shutdown. Do not apply an external load to AVDD.
Feedback Input. The feedback threshold is 0.8V. Connect to the center of a resistive
voltage-divider from the output to GND to set the output voltage to 0.8V or greater. On
the MAX1962, connect FB to VDD to select preset output voltages (see SEL).
9
9
9
COMP
10
10
10
REF
Reference Output. VREF = 1.28V. Bypass with a 0.22µF capacitor to GND.
11
11
11
GND
Analog Ground. Connect to the PC board analog ground plane. Connect the PC
board analog ground plane and power ground planes with a single connection.
Charge-Pump Output. Provides regulated 5V to power the IC and gate drivers.
Bypass with a 4.7µF ceramic capacitor for operating frequencies between 450kHz
and 950kHz. Bypass with a 2.2µF ceramic capacitor for 1MHz operation. VDD is
internally forced to VCC in shutdown. Do not apply an external load to VDD.
12
12
12
VDD
13
13
13
DL
14
14
14
PGND
Compensation Pin. COMP is forced to GND in shutdown, UVLO, or thermal fault.
Low-Side MOSFET Synchronous Rectifier Gate-Driver Output. DL is high in
shutdown.
Power Ground. Connect to the PC board power ground plane.
_______________________________________________________________________________________
9
MAX1960/MAX1961/MAX1962
Pin Description
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1960 MAX1961 MAX1962
15
15
15
C-
Charge-Pump Flying Capacitor Negative Connection. Use a 0.47µF ceramic
capacitor at 1MHz, and 1µF between 450kHz and 950kHz.
16
16
16
C+
Charge-Pump Flying Capacitor Positive Connection. Use a 0.47µF ceramic
capacitor at 1MHz and 1µF between 450kHz and 950kHz.
17
17
17
VCC
Input Supply to Charge Pump
18
18
18
BST
Boost Capacitor Connection. Connect a 0.1µF ceramic capacitor from BST to LX.
19
19
19
DH
High-Side MOSFET Gate-Driver Output. DH is low in shutdown.
20
20
20
LX
Inductor Connection
Detailed Description
The MAX1960/MAX1961/MAX1962 are high-current,
high-efficiency voltage-mode step-down DC-DC controllers that operate from 2.35V to 5.5V input and generate adjustable voltages down to 0.8V at up to 20A. An
on-chip charge pump generates a regulated 5V for driving a variety of external N-channel MOSFETs.
Constant frequency PWM operation and external synchronization make these controllers suitable for telecom
and datacom applications. The operating frequency is
programmed externally to either 500kHz or 1MHz, or
from 450kHz to 1.2MHz with an external clock. A clock
output is provided to synchronize another converter for
180° out-of-phase operation.
A high closed-loop bandwidth provides excellent transient response for applications with dynamic loads.
Internal Charge Pump
An on-chip regulated charge pump develops 5V at
50mA (max) with input voltages as low as 2.35V. The
output of this charge pump provides power for the
internal circuitry, bias for the low-side driver (DL), and
the bias for the boost diode, which supplies the highside MOSFET gate driver (DH). The charge pump is
synchronized with the DL driver signal and operates at
1/2 the PWM frequency.
The external MOSFET gate charge is the dominant load
for the charge pump and is proportional to the PWM
switching frequency. The charge pump must supply
chip-operating current plus adequate gate current for
both MOSFETs at the selected operating frequency.
The required charge-pump output current is given by
the formula:
ITOTAL = IAVDD + fOSC (QG1 + QG2)
10
where IAVDD is the current supplied to the IC through
AV DD (typically 2mA), f OSC is the PWM switching
frequency, Q G1 is the gate charge of the high-side
MOSFET, and QG2 is the gate charge of the low-side
MOSFET. The MOSFETs must be chosen such that
ITOTAL does not exceed 50mA. For example, with 1MHz
operation, QG1 + QG2 should be less than 48nC.
Voltage Margining and Shutdown
The voltage-margining feature on the MAX1960/
MAX1961 shifts the output voltage up or down by 4%.
This is useful for the automatic testing of systems at high
and low supply conditions to find potential hardware failures. CTL1 and CTL2 control voltage margining as outlined in Table 1.
A shutdown feature is included on all three parts, which
stops switching the output drivers and the charge
pump, reducing the supply current to less than 15µA.
For the MAX1962, drive EN high for normal operation,
or low for shutdown. For the MAX1960/MAX1961, drive
both CTL1 and CTL2 high for normal operation, or drive
CTL1 and CTL2 low for shutdown. For a simple
enable/shutdown function with no voltage margining,
connect CTL1 and CTL2 together and drive as one
input.
Table 1. Voltage Margining Truth Table
CTL1
CTL2
High
High
Normal operation
FUNCTION
High
Low
+4% output-voltage shift
Low
High
-4% output-voltage shift
Low
Low
Shutdown
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
OUT
MAX1960/MAX1961/MAX1962
ILIM
(MAX1960/MAX1961)
CS
(MAX1962)
CURRENT
SENSE
LX
PGND
BST
CLKOUT
S
OSC
DH
Q
FSET/SYNC
UVLO
LX
OSC
VDD
COMP
R
Q
DL
COMP
PGND
OUT
(MAX1961/MAX1962)
SOFT-START
DAC
REF
ERROR
AMP
FB
(MAX1960/MAX1962)
AVDD
REF
FEEDBACK
SELECT
VDD
C+
VSEL
(MAX1961/MAX1962)
CTL1
(MAX1960/MAX1961)
CTL2
(MAX1960/MAX1961)
MAX1960/
MAX1961/
MAX1962
SHUTDOWN
AND VOLTAGE
MARGINING
OSC
CHARGE
PUMP
CVCC
GND
EN
(MAX1962)
Figure 1. Functional Diagram
MOSFET Gate Drivers
Undervoltage Lockout and Soft-Start
The DH and DL drivers are designed to drive logic-level
N-channel MOSFETs to optimize system cost and efficiency. MOSFETs with RDSON rated at VGS 4.5V are
recommended. An adaptive dead-time circuit monitors
the DL output and prevents the high-side MOSFET from
turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the
MOSFET gate for the adaptive dead-time circuit to work
properly. Otherwise, the internal sense circuitry could
interpret the MOSFET gate as “off” while there is actually
still charge left on the gate. Use very short, wide traces
measuring no more than 20 squares (50mils to 100mils
wide if the MOSFET is 1in from the IC).
There are two undervoltage lockout (UVLO) circuits on
the MAX1960/MAX1961/MAX1962. The first UVLO circuit monitors VCC, which must be above 2.15V (typ) in
order for the charge pump to operate. The second
UVLO circuit monitors the output of the charge pump.
The charge-pump output, VDD, must be above 4.2V
(typ) in order for the PWM converter to operate. Both
UVLO circuits inhibit switching and force DL high and DH
low when either VCC or VDD are below their threshold.
When the monitored voltages are above their thresholds, an internal soft-start timer ramps up the erroramplifier reference voltage. The ramp occurs in eighty
10mV steps. Full output voltage is reached 1.28ms after
activation with a 1MHz operating frequency.
______________________________________________________________________________________
11
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Operating Frequency and Synchronization
The MAX1960/MAX1961/MAX1962 operating frequency
is set externally to either 500kHz or 1MHz. For 500kHz
operation, connect FSET/SYNC to GND, or for 1MHz
operation, connect FSET/SYNC to VDD. Alternately, an
external clock from 450kHz to 1.2MHz can be applied
to SYNC.
A clock output (CLKOUT) that is 180° out-of-phase with
the internal clock is also provided. This allows a second
converter to be synchronized, and operate 180° out-ofphase with the first. To do this, simply connect CLKOUT
of the first converter to FSET/SYNC of the second converter. The first converter can be set internally to 500kHz
or 1MHz for this mode of operation. When the first converter is synchronized to an external clock, CLKOUT is
the inverse of external clock. See the SYNC Timing
Waveform in the Typical Operating Characteristics.
Lossless Current Limit
(MAX1960/MAX1961)
increases until it reaches its maximum value, where the
part enters dropout. With a switching frequency of
1MHz, the maximum duty cycle is about 83%. At
500kHz, the duty cycle can increase to about 92%,
resulting in a lower dropout voltage. The duty cycle is
dependent on the input voltage (VIN), the output voltage (V OUT ), and the parasitic voltage drops in the
MOSFETs and the inductor (V DROP(N1), V DROP(N2),
V DROP(L)). Note that V DROP(L) includes the voltage
drop due to the inductor’s resistance, the drop across
the current-sense resistor (if used), and any other resistive voltage drop from the LX switching node to the
point where the output voltage is sensed. The duty
cycle is found from:
D=
VOUT + VDROP(L)
VIN - VDROP(N1) - VDROP(N2)
Adaptive Dead Time
To prevent damage in the case of excessive load current or a short circuit, the MAX1960/MAX1961 use the
low-side MOSFET’s on-resistance (RDS(ON)) for current
sensing. The current is monitored during the on-time of
the low-side MOSFET. If the current-sense voltage
(VPGND - VLX) rises above the current-limit threshold for
more than 128 clock cycles, the controller turns off. The
controller remains off until the input voltage is removed
or the device is re-enabled with CTL1 and CTL2 (see
the Setting the Current Limit section).
The MAX1960/MAX1961/MAX1962 DL and DH MOSFET
drivers have an adaptive dead-time circuit to prevent
shoot-through current caused by high- and low-side
MOSFET overlap. This allows a wide variety of MOSFETs
to be used without matching FET dynamic characteristics. The DL driver will not go high until DH drives the
high-side MOSFET gate to within 1V of its source (LX).
The DH output will not go high until DL drives the low-side
MOSFET gate to within 1V of ground.
Current-Sense Resistor (MAX1962)
Component selection is primarily dictated by the following
criteria:
Input voltage range. The maximum value
(VIN(MAX)) must accommodate the worst-case high
input voltage. The minimum value (VIN(MIN)) must
account for the lowest input voltage after drops due
to connectors, fuses, and selector switches are considered.
Maximum load current. There are two values to consider: The peak load current (ILOAD(MAX)) determines
the instantaneous component stresses and filtering
requirements and is key in determining output capacitor requirements. ILOAD(MAX) also determines the
inductor saturation rating and the design of the current-limit circuit. The continuous load current (ILOAD)
determines the thermal stresses and is key in determining input capacitor requirements, MOSFET
requirements, as well as those of other critical heatcontributing components.
The MAX1962 uses a standard current-sense resistor in
series with the inductor for a 10% accurate current-limit
measurement. The current-sense threshold is 50mV. This
provides accurate current sensing at all duty cycles without relying on MOSFET on-resistance. CS connects to
the high-side (inductor side) of the current-sense resistor
and OUT connects to the low-side (output side) of the
current-sense resistor.
The current-sense resistor for the MAX1962 may also be
replaced with a series RC network across the inductor.
This method uses the parasitic resistance of the inductor
for current sensing. This method is less accurate than
using a current-sense resistor, but is lower cost and provides slightly higher efficiency. See the Design
Procedure section for instructions on using this method.
Dropout Performance
The MAX1960/MAX1961/MAX1962 enter dropout when
the input voltage is not sufficiently high to maintain output
regulation. As input voltage is lowered, the duty cycle
12
Design Procedure
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
MAX1960/MAX1961/MAX1962
Inductor operating point. This choice provides
tradeoffs between size, transient response, and efficiency. Choosing higher inductance values results
in lower inductor ripple current, lower peak current,
lower switching losses, and, therefore, higher efficiency at the cost of slower transient response and
larger size. Choosing lower inductance values
results in large ripple currents, smaller size, and
poorer efficiency, but have faster transient response.
Table 2. Preset Voltages—
MAX1961/MAX1962
PRESET OUTPUT VOLTAGE
SEL
1.5V
GND
1.8V
REF
2.5V
No connection
3.3V
VDD
Setting the Output Voltage
The MAX1961 has four output voltage presets selected
by SEL. Table 2 shows how each of the preset voltages
are selected. The MAX1962 also has four preset output
voltages, but also is adjustable down to 0.8V. To use the
preset voltages on the MAX1962, FB must be connected
to VDD. SEL then selects the output voltage as shown in
Table 2.
Both the MAX1960/MAX1962 feature an adjustable output that can be set down to 0.8V. To set voltages greater
than 0.8V, Connect FB to a resistor-divider from the output (Figures 9 and 11). Use a resistor up to 10kΩ for R2
and select R1 according to the following equation:
D2
Input Voltage Range
The MAX1960/MAX1961/MAX1962 have an input voltage range of 2.35V to 5.5V but cannot operate at both
extremes with one application circuit. The standard
charge-pump doubler application circuit operates with
an input range of 2.7V to 5.5V (Figures 9, 10, and 11).
In order to operate down to 2.35V, the charge pump
must be configured as a tripler. This circuit, however,
limits the maximum input voltage to 3.6V. The schematic
for the tripler charge pump is shown in Figure 2. Note
that the flying capacitor between C+ and C- has been
removed and C+ is not connected.
D4
D5
C11
C10
C12
VCC
C-
MAX1960/
MAX1961/
MAX1962
C+
VDD
C6
R5
10Ω
AVDD
C4
1µF
⎛V
⎞
R1 = R2 × ⎜ OUT - 1⎟
⎝ VFB
⎠
where the feedback threshold, VFB = 0.8V, and VOUT is
the output voltage.
D3
C10, C11, C12
500kHz
1µF
1MHz
0.47µF
C6
4.7µF
2.2µF
Figure 2. Tripler Charge-Pump Configuration.
vides a good compromise between efficiency and
economy. Choose a low-loss inductor having the lowest
possible DC resistance. Ferrite core type inductors are
often the best choice for performance. The inductor
saturation current rating must exceed IPEAK:
⎛ LIR ⎞
IPEAK = ILOAD(MAX) + ⎜
⎟ × ILOAD(MAX)
⎝ 2 ⎠
Inductor Selection
Determine an appropriate inductor value with the following equation:
L = VOUT ×
VIN - VOUT
VIN × fOSC × LIR × ILOAD(MAX)
The inductor current ripple, LIR, is the ratio of peak-topeak inductor ripple current to the average continuous
inductor current. An LIR between 20% and 40% pro-
Setting the Current Limit
Lossless Current Limit (MAX1960/MAX1961)
The MAX1960/MAX1961 use the low-side MOSFET’s onresistance (RDS(ON)) for current sensing. This method of
current limit sets the maximum value of the inductor’s
“valley” current (Figure 3). If the inductor current is higher
than the valley current-limit setting at the end of the
clock period, the controller skips the DH pulse. When
the first current-limit event is detected, the controller initi-
______________________________________________________________________________________
13
DH
0.22µH, 2.8mW,
ILIMIT = 18A
RL
IPEAK
L
LX
ILOAD
INDUCTOR CURRENT
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
MAX1962
DL
R
R = 33Ω
C
C = 4.7µF
IVALLEY
CS
TIME
OUT
Figure 3. Inductor Current Waveform
Figure 4. Using the Inductor Resistance as a Current-Sense
Resistor with the MAX1962
ates a 128 clock cycle counter. If the current limit is present at the end of this count, the controller remains off
until the input voltage is removed and re-applied, or the
device is re-enabled with CTL1 and CTL2. The 128-cycle
counter is reset when four successive DH pulses are
observed, without activating the current limit.
At maximum load, the low excursion of inductor current,
IVALLEY(MAX), is:
accuracy is needed, use the MAX1962 with a currentsense resistor.
⎛ LIR ⎞
IVALLEY(MAX) = ILOAD(MAX) - ⎜
⎟ × ILOAD(MAX)
⎝ 2 ⎠
The current-limit threshold (VCLT) is set by connecting a
resistor (RILIM) from ILIM to GND. The range for this
resistor is 100kΩ to 400kΩ. Set current-limit threshold as
follows:
VCLT = RILIM × 0.714µA
Connecting ILIM to VDD sets the threshold to a default
value of 75mV.
To prevent the current limit from falsely triggering, VCLT
divided by the low-side MOSFET RDS(ON) must exceed
the maximum value of IVALLEY. The maximum value of
low-side MOSFET RDS(ON) should be used:
VCLT > RDS(ON)MAX x IVALLEY(MAX)
A limitation of sensing current across MOSFET on-resistance is that the MOSFET on-resistance varies significantly from MOSFET to MOSFET and over temperature.
Consequently, this current-sensing method may not be
suitable if a precise current limit is required. If better
14
Current-Sense Resistor (MAX1962)
The MAX1962 uses a current-sense resistor connected
from the inductor to the output with Kelvin sense connections. The current-sense voltage is measured from CS to
OUT, and has a fixed threshold of 50mV. The MAX1962
current limit is triggered when the peak voltage across
the current-sense resistor, IPEAK × RSENSE, exceeds
50mV. Once current sense is triggered, the controller
does not turn off, but continues to operate at the current
limit. This method of current sensing is more precise due
to the accuracy of the current-sense resistor. The cost of
this precision is that it requires an extra component and
is slightly less efficient due to the loss in the currentsense resistance.
Inductor Resistance Current Sense (MAX1962)
Alternately, the inductor resistance can be used to
sense current in place of a current-sense resistor. To
do this, connect a series RC network in parallel with the
inductor (Figure 4). Choose a resistor value less than
40Ω to avoid offsets due to CS input current. Calculate
the capacitor value from the formula C = 2L / (RL × R).
The effective current-sense resistance (RSENSE) equals
RL. Current-sense accuracy then depends on the accuracy of the inductor resistance. Note that the currentsense signal is delayed due to the RC filter time
constant. Consequently, inductor current may overshoot (by as much as 2x) when a fast short occurs.
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
VDIP
RESR ≤
ILOADSTEP(MAX)
In applications with less severe load steps, maximum
ESR may be governed by what is needed to maintain
acceptable output voltage ripple:
VRIPPLE(P−P)
RESR ≤
LIR × ILOAD(MAX)
To satisfy both load step and ripple requirements,
select the lowest value from the above two equations.
The capacitor is usually selected by physical size, ESR,
and voltage rating, rather than by capacitance value.
With current tantalum, electrolytic, and polymer capacitor technology, the bulk capacitance will also be sufficient once the ESR requirement is satisfied.
When using low-capacity filter capacitors such as
ceramic, capacitor size is usually determined by the
capacitance needed to prevent voltage undershoot
and overshoot during load transients. The overshoot
voltage (VSOAR) is given by:
VSOAR =
L × (IPEAK )
2
2 × VOUT × COUT
Generally, once enough capacitance is in place to meet
the overshoot requirement, undershoot at the rising load
edge is no longer a problem.
Input Capacitor Selection
The input capacitor (CIN) reduces the current peaks
drawn from the input supply and reduces noise injection. The source impedance to the input supply largely
determines the value of CIN. High source impedance
requires high input capacitance. The input capacitor
must meet the ripple current requirement (I RMS )
imposed by the switching currents.
The RMS input ripple current is given by:
IRMS = ILOAD ×
VOUT × (VIN - VOUT )
VIN
For optimal circuit reliability, choose a capacitor that
has less than 10°C temperature rise at the peak ripple
current.
Compensation and Stability
Compensation with Ceramic Output Capacitors
The high switching frequency range of the
MAX1960/MAX1961/MAX1962 allows the use of ceramic
output capacitors. Since the ESR of ceramic capacitors
is very low typically, the frequency of the associated
transfer function zero is higher than the unity-gain
crossover frequency and the zero cannot be used to
compensate for the double pole created by the output
inductor and capacitor. The solution is Type 3 compensation (Figure 5), which takes advantage of local feedback to create two zeros and three poles (Figure 6). The
frequency of the poles and zeros are described below:
fP1 = 0
fP2 =
1
2π × R2 × C3
1
fP3 =
fLC =
fZ1 =
fZ2 =
C1 × C2
C1 + C2
2π × R1 ×
1
2π L 0 × C 0
1
2π × R1 × C1
1
2π × (R2 + R3) × C3
fZESR =
1
2π × RESR × C0
Unity-gain crossover frequency:
f0 = R1 × C3 ×
VIN(MAX)
VRAMP
×
1
2π × L 0 × C 0
______________________________________________________________________________________
15
MAX1960/MAX1961/MAX1962
Output Capacitor Selection
The output filter capacitor must have low enough effective
series resistance (ESR) to meet output ripple and load
transient requirements. In addition, the capacitance value
must be high enough to absorb the inductor energy
during load steps.
In applications where the output is subject to large load
transients, low ESR is needed to prevent the output
from dipping too low (VDIP) during a load step:
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
VIN
GAIN (dB)
DH
LO
VOUT
LX
DL
C0
MAX1960
R3
FB
R2
C3
R4
R1
COMP
fz1
fp1
C2
fz2
fp2
fp3
FREQUENCY
C1
Figure 5. Type 3 Compensation Network
Figure 6. Transfer Function for Type 3 Compensation
where:
VIN(MAX) = Maximum input voltage
VRAMP = Oscillator ramp voltage = 0.85 x 106/fS,
where fS = switching frequency
LO = Output inductance
If C2 < 10pF, it can be omitted.
CO = Output capacitance
The goal is to place the two zeros below crossover and
the two poles above crossover so that crossover
occurs with a single-pole slope. The compensation procedure is as follows:
Select the crossover frequency such that:
f0 < fZESR and f0 >
2
gmEA
C3 ≤
2π × f0 × L 0 × C0 × VRAMP
R1 × VIN
Place the second pole after the ESR zero:
R2 ≤
If:
R2 <
C1 ≥
1
2π × 0.75 × fLC × R1
Place the third pole at half the switching frequency:
C2 ≥
16
1
,
gmEA
where gmEA = 2mS
increase R1 and recalculate C1, C2, and C3.
Place the second zero at the double-pole frequency:
where gmEA = 2mS.
Place the first zero before the double pole:
1
2π × fZESR × C3
R3 ≥
1
- R2
2π × fLC × C3
Set the output voltage:
R4 =
VFB
× R3, VFB = 0.8V
VOUT - VFB
1
2π × 0.5 × fS × R1
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
GMOD(DC) =
VIN
VRAMP
where VRAMP = 0.85 × 106 / fS. The pole frequency due
to the inductor and output capacitor is:
fPMOD =
fPEA =
fZEA =
f
fZESR < fC ≤ S
5
The loop-gain equation at the crossover frequency is:
VFB
× GEA(fC ) × GMOD(fC ) = 1
VOUT
where:
GEA(fC ) = gmEA × RC
1
The output capacitor is usually comprised of several
same value capacitors connected in parallel. With n
capacitors in parallel, the output capacitance is:
CO = n × CEACH
and:
GMOD(fC ) = GMOD(DC) ×
RESR =
RESR(EACH)
n
The ESR zero (f ZESR ) for a parallel combination of
capacitors is the same as for an individual capacitor.
(fPMOD )2
fESR × fC
The compensation resistor, RC, is calculated from:
RC =
The total ESR is:
1
2π × CC × RC
The total closed-loop gain must equal to unity at the
crossover frequency, where the crossover frequency
should be higher than fZESR, so that the -1 slope is
used to cross over at unity gain. Also, the crossover
frequency should be less than or equal to 1/5 the
switching frequency.
1
2π × RESR × CO
1
2π × CC × (R0 + RC )
A zero is set by the compensation resistor and the
compensation capacitor:
2π LOCO
The zero frequency due to the output capacitor’s ESR
is:
fZESR =
The transconductance error amplifier has DC gain
GEA(dc) of 80dB. A dominant pole is set by the compensation capacitor (CC), the amplifier output resistance (RO), and the compensation resistor (RC):
VOUT
gmEA × VFB × GMOD(fC )
where gmEA = 2mS.
Due to the under-damped (Q > 1) nature of the output
LC double pole, the error-amplifier compensation zero
should be approximately 0.2fPMOD to provide good
phase boost. CC is calculated from:
______________________________________________________________________________________
17
MAX1960/MAX1961/MAX1962
Compensation with Electrolytic Output Capacitors
The MAX1960/MAX1961/MAX1962 use a voltage-mode
control scheme that regulates the output voltage by
comparing the error-amplifier output (COMP) with a
fixed internal ramp to produce the required duty cycle.
The inductor and output capacitor create a double pole
at the resonant frequency, which has gain drop of 40dB
per decade, and phase shift of 180°. The error amplifier
must compensate for this gain drop and phase shift in
order to achieve a stable high-bandwidth, closed-loop
system.
The basic regulator loop consists of a power modulator,
an output feedback divider and an error amplifier. The
power modulator has DC gain set by VIN/VRAMP, with a
double pole set by the inductor and output capacitor,
and a single zero set by the output capacitor (CO) and
its equivalent series resistance (ESR). Below are equations that define the power modulator:
The DC gain of the power modulator is:
The feedback divider has a gain of GFB = VFB/VOUT,
where VFB is 0.8V.
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
5
CC =
2π × RC × fPMOD
A small capacitor CF, can also be added from COMP to
GND to provide high-frequency decoupling. CF will add
another high-frequency pole (fPHF) to the error-amplifier
response. This pole should be greater than 100 times
the error-amplifier zero frequency to have negligible
impact on the phase margin. This pole should also be
less than half the switching frequency for effective
decoupling:
100fZEA < fPHF < 0.5fS
Select a value for fPHF in the range given above, then
solve for CF using the following equation:
CF =
1
2π × RC × fPHF
Below is a numerical example to calculate compensation values:
VIN = 3.3V
VRAMP = 0.85V
VOUT = 1.8V
VFB = 0.8V
IOUT(max) = 15A
CO = 2 x 680µF = 1360µF
ESR = 0.008Ω / 2 = 0.004Ω
LO = 0.22µH
gmEA = 2mS
fS = 1MHz
fPMOD =
1
2π ×
L O × CO
1
=
2π × 0.22 × 10−6 × 1360 × 10−6
= 9.201kHz
fZESR =
=
1
2π × CO × RESR
1
2π × 1360 × 10−6 × 0.004
= 29.3kHz
18
Choose the crossover frequency (fC) in the range fZESR
< fC < fS/5:
29.3kHz < fC < 200kHz
Select fC = 100kHz, this meets the criteria above, and the
bandwidth is high enough for good transient response.
The power modulator gain at fC is:
GMOD(fc) =
VIN
VRAMP
=
×
(fPMOD )2
fZESR × fC
3
(9201)2
×
= 0.102
0.85
29.3kΩ × 100kΩ
Choose R1 = 8.06kΩ, then R2 = 10kΩ (see the Setting
the Output Voltage section):
C=
VOUT
1.8
=
gmEA × VFB × GMOD(fC ) 0.002 × 0.8 × 0.102
= 11kΩ
CC =
5
5
=
= 7863pF
2π × RC × fPMOD 2π × 11kΩ × 9201
Select C C = 8200pF (nearest standard capacitor
value).
Select fPHF in the range 100fZEA < fPHF < 0.5fS.
184kHz < fPHF < 500kHz
Select fPHF = 250kHz, then solve for CF:
CF =
1
1
=
= 58pF
2π × RC × fPHF 2π × 11kΩ × 250kHz
Select the nearest standard capacitor value CF = 56pF.
Summary of feedback divider and compensation components:
R1 = 8.06kΩ
R2 = 10kΩ
RC = 11kΩ
CC = 8200pF
CF = 56pF
Power MOSFET Selection
When selecting a MOSFET, essential parameters
include:
(1) Total gate charge (QG)
(2) Reverse transfer capacitance (CRSS)
(3) On-resistance (RDS(ON))
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
ERROR AMPLIFIER
MODULATOR
OUTPUT FILTER
V1
0.8V
R1
VIN/VRAMP
Gm
RS
R2
R3
L1
C9
V2
RESR
RLOAD
COUT
Figure 7. Open-Loop Transfer Model
(4) Gate threshold voltage (VTH(MIN))
(5) Turn-on/turn-off times
(6) Turn-on/turn-off delays
At high switching rates, dynamic characteristics (parameters 1, 2, 5, and 6) that predict switching losses may
have more impact on efficiency than RDS(ON), which predicts DC losses. QG includes all capacitance associated
with charging the gate, and best performance is
achieved with a low total gate charge. QG also helps
predict the current needed to drive the gate at the
selected operating frequency. This is very important
because the output current from the charge pump is
finite (50mA, max) and is used to drive the gates of the
MOSFETs as well as provide bias for the IC. RDS(ON) is
important as well, as it is used for current sensing in the
MAX1960/MAX1961. RDS(ON) also causes power dissipation during the on-time of the MOSFET.
Choose QG to be as low as possible. Ensure that:
QG1 + QG2 ≤
50mA
fS
Choose RDS(ON) to provide the desired ILOAD(MAX) at
the desired current-limit threshold voltage (see the
Setting the Current Limit section).
MOSFET RC Snubber Circuit
Fast-switching transitions can cause ringing due to resonating circuit parasitic inductance and capacitance at
the switching nodes. This high-frequency ringing
occurs at LX rising and falling transitions, and may
introduce current-sensing errors and generate EMI. To
dampen this ringing, a series RC snubber circuit can
be added across each MOSFET switch (Figure 8).
Typical values for the snubber components are CSNUB
= 4700pF and RSNUB = 1Ω, however, the ideal values
for snubber components will depend on circuit parasitics. Below is the procedure for selecting the component values of the series RC snubber circuit:
1) Connect a scope probe to measure VLX to GND,
and observe the ringing frequency, fR.
2) Find the capacitor value (connected from LX to
GND) that reduces the ringing frequency by half.
3) The circuit parasitic capacitance, CPAR, at LX is then
equal to 1/3 of the value of the added capacitance
above.
______________________________________________________________________________________
19
MAX1960/MAX1961/MAX1962
FEEDBACK DIVIDER
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
where VIN(MAX) is the maximum value of the input voltage, tFALL and tRISE are the fall and rise time of the
MOSFET, I L(PEAK) and I L(VALLEY) are the maximum
peak and valley inductor current, and fS is the PWM
switching frequency:
IL(PEAK) = IOUT(MAX) × (1 + 0.5 × LIR) and IL(VALLEY) =
IOUT(MAX) × (1 - 0.5 × LIR)
where LIR is the peak-to-peak inductor ripple current
divided by the load current.
The total power dissipation in the high-side MOSFET is
the sum of these two power losses:
PD(N1) = PD(N1RESISTIVE) + PD(N1SWITCHING)
For the low-side MOSFET, the worst-case power dissipation occurs at maximum input voltage:
INPUT
RSNUB
DH
MAX1960
N1
CSNUB
L1
LX
RSNUB
DL
N2
CSNUB
PGND
Figure 8. RC Snubber Circuit
4) The circuit parasitic inductance, LPAR, is calculated
by:
LPAR =
1
Applications Information
(2π × fR )2 × CPAR
5) The resistor for critical dampening, RSNUB = 2π x
fR x LPAR. The resistor value can be adjusted up
or down to tailor the desired damping and the
peak voltage excursion.
6) The capacitor, CSNUB, should be at least 2 to 4
times the value of the CPAR to be effective.
7) The snubber circuit power loss is dissipated in the
resistor, PRSNUB, and can be calculated as:
PRSNUB = CSNUB × (VIN )2 × fS
where V IN is the input voltage, and f S is the
switching frequency. Choose RSNUB power rating
that exceeds the calculated power dissipation.
MOSFET Power Dissipation
Worst-case power dissipation occurs at duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
input voltage (VIN(MIN)):
PD(N1RESISTIVE) =
VOUT
× ILOAD2 × RDS(ON)
VIN(MIN)
The following formula calculates switching losses for
the high-side MOSFET, but is only an approximation
and not a substitute for evaluation:
PD(N1SWITCHING) =
(IL(PEAK) ×
20
⎛
VOUT ⎞
PD(N2RESISTIVE) = ⎜1 ⎟ × ILOAD2 × RDS(ON)
VIN(MAX) ⎠
⎝
)
tFALL + IL(VALLEY) × tRISE ×
VIN(MAX)
2
PC Board Layout Guidelines
A properly designed PC board layout is important in
any switching DC-DC converter circuit. If possible,
mount the MOSFETs, inductor, input/output capacitors,
and current-sense resistor on the top side. Connect the
ground for these devices close together on a powerground trace. Make all other ground connections to a
separate analog ground plane. Connect the analog
ground plane to power ground at a single point.
To help dissipate heat, place high-power components
(MOSFETs, inductor, and current-sense resistor) on a
large PC board area. Keep high-current traces short and
wide to reduce the resistance in these traces. Also make
the gate drive connections (DH and DL) short and wide,
measuring 10 to 20 squares (50mils to 100mils wide if the
MOSFET is 1in from the controller IC).
For the MAX1960/MAX1961, connect LX and PGND to
the low-side MOSFET using Kelvin sense connections.
For the MAX1962, connect CS and OUT to the currentsense resistor using Kelvin sense connections.
Place the REF capacitor, the BST diode and capacitor,
and the charge-pump components as close as possible
to the IC. If the IC is far from the input capacitors, bypass
VCC to GND with a 0.1µF or greater ceramic capacitor
close to the VCC pin.
For an example PC board layout, see the MAX1960
evaluation kit.
× fS
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
MAX1960/MAX1961/MAX1962
Table 3. Component List for Application Circuits
PART
APP. CIRCUIT
C1
1, 2, 3
C2
1, 2, 3, 4
15A OUTPUT 1MHz
15A OUTPUT 500kHz
0.47µF ceramic capacitor
1µF ceramic capacitor
5 × 10µF ceramic capacitors
5 × 10µF ceramic capacitors
C3
1, 2, 3, 4
2 x 680µF POSCAPs Sanyo 2R5TPD680M8
2 x 680µF POSCAPs Sanyo 2R5TPD680M8
C4
1, 2, 3, 4
1µF ceramic capacitor
1µF ceramic capacitor
C5
1, 2, 3, 4
0.1µF ceramic capacitor
0.1µF ceramic capacitor
C6
1, 2, 3, 4
2.2µF ceramic capacitor
4.7µF ceramic capacitor
C8
1, 2, 3, 4
0.22µF ceramic capacitor
0.22µF ceramic capacitor
C9
1, 2, 3, 4
(Table 4)
(Table 5)
C10, C11, C12
4
0.47µF ceramic capacitors
1µF ceramic capacitors
C13, C14
1, 2, 3, 4
4700pF ceramic capacitors
4700pF ceramic capacitors
D1
1, 2, 3, 4
Schottky diode
Central CMSSH-3
Schottky diode
Central CMSSH-3
D2–D5
4
Schottky diodes
Central CMHSH5-2L
Schottky diodes
Central CMHSH5-2L
L1
1, 2, 3, 4
0.22µH, 1.7mΩ inductor
Sumida CDEP1040R2NC-50
0.45µH inductor
Sumida CDEP1040R4MC-50
N1
1, 2, 3, 4
N-channel MOSFET
International Rectifier IRLR7821
N-channel MOSFET
International Rectifier IRLR7821
N2
1, 2, 3, 4
N-channel MOSFET
International Rectifier IRLR7833
N-channel MOSFET
International Rectifier IRLR7833
R1
1, 3
Sets output voltage
Sets output voltage
R2
1, 3
10kΩ ±1% resistor
10kΩ ±1% resistor
R3
1, 2, 3, 4
(Table 4)
(Table 5)
390kΩ ±5% resistor
390kΩ ±5% resistor
10Ω ±5% resistor
10Ω ±5% resistor
1.5mΩ ±5%, 1W resistor
Panasonic ERJM1WTJ1M5U
1.5mΩ ±5%, 1W resistor
Panasonic ERJM1WTJ1M5U
1Ω ±5% resistors
1Ω ±5% resistors
R4
1, 2
R5
1, 2, 3, 4
R6
3, 4
R7, R8
1, 2, 3, 4
______________________________________________________________________________________
21
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Table 4. R1, R3, and C9 Component Values for 1MHz Operation
VIN
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
R1 (kΩ)
R3 (kΩ)
C9 (µF)
R1 (kΩ)
R3 (kΩ)
C9 (µF)
R1 (kΩ)
R3 (kΩ)
C9 (µF)
R1 (Ω)
R3 (kΩ)
5V
3.12
1.2
0.0068
2.13
9.1
0.01
1.24
6.8
0.01
876
5.5
C9 (µF)
0.01
3.3V
—
—
—
—
—
—
1.24
2.7
0.01
876
2.4
0.01
2.5V
—
—
—
—
—
—
1.24
3.9
0.01
876
3.3
0.01
Table 5. R1, R3, and C9 Component Values for 500kHz Operation
VIN
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
R1 (kΩ)
R3 (kΩ)
C9 (µF)
R1 (kΩ)
R3 (kΩ)
C9 (µF)
R1 (kΩ)
R3 (kΩ)
C9 (µF)
R1 (Ω)
R3 (kΩ)
C9 (µF)
5V
3.12
36
0.0033
2.13
27
0.0047
1.24
20
0.0068
876
16
0.0068
3.3V
—
—
—
2.13
47
0.0033
1.24
30
0.0047
876
27
0.0047
2.5V
—
—
—
—
—
—
1.24
39
0.0033
876
33
0.0033
Table 6. Component Suppliers
Selector Guide
SUPPLIER
PHONE
WEBSITE
Central Semiconductor
631-435-1110
www.centralsemi.com
International Rectifier
310-322-3331
www.irf.com
MAX1960
Kamaya
260-489-1533
www.kamaya.com
MAX1961
Murata
814-237-1431
www.murata.com
Panasonic
714-373-7939
www.panasonic.com
Sanyo
619-661-6835
www.sanyo.com
Sumida
847-956-0666
www.sumida.com
Taiyo Yuden
408-573-4150
www.t-yuden.com
22
PART
MAX1962
VOLTAGE
MARGINING
CURRENT
LIMIT
OUTPUT
VOLTAGE
±4%
FET VDS
Sensing
Adjustable
No
±10% with
RSENSE
4 Presets or
Adjustable
______________________________________________________________________________________
4 Presets
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
MAX1960/MAX1961/MAX1962
C1
INPUT
2.7V TO 5.5V
C+
C4
C-
VCC
AVDD
C2
R5
CTL1
VDD
CTL2
BST
D1
COMP
MAX1960
C6
R7
DH
N1
C5
C9
REF
C13
OUTPUT
DOWN TO 0.8V
L1
LX
C3
R8
DL
C8
R3
N2
C14
GND
FSET/SYNC
CLKOUT
PGND
ILIM
R4
CLKOUT
N.C.
R1
FB
R2
Figure 9. Application Circuit 1—MAX1960 Adjustable Output Voltage
______________________________________________________________________________________
23
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
C1
INPUT
2.7V TO 5.5V
C+
C4
C-
VCC
AVDD
C2
R5
CTL1
VDD
D1
BST
CTL2
COMP
C6
MAX1961
R7
DH
N1
C5
C9
REF
C13
L1
OUTPUT 2.5V
LX
C3
R8
DL
C8
R3
N2
C14
GND
FSET/SYNC
CLKOUT
PGND
ILIM
R4
CLKOUT
VSEL
OUT
Figure 10. Application Circuit 2—MAX1961 Preset Output Voltage
24
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
MAX1960/MAX1961/MAX1962
C1
INPUT
2.7V TO 5.5V
C+
C4
C-
VCC
AVDD
C2
R5
VDD
D1
COMP
C6
BST
EN
MAX1962
R7
DH
N1
C5
C9
REF
C13
L1
R6
OUTPUT
DOWN TO 0.8V
LX
C3
R8
DL
C8
R3
N2
C14
GND
FSET/SYNC
CLKOUT
CLKOUT
PGND
CS
OUT
R1
VSEL
FB
R2
Figure 11. Application Circuit 3—MAX1962 Adjustable Output Voltage
______________________________________________________________________________________
25
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
D3
D2
D4
C11
C10
INPUT
2.35V TO 3.6V
C+
C12
C4
C-
VCC
D5
AVDD
C2
R5
VDD
D1
BST
EN
COMP
C6
MAX1962
R7
DH
N1
C5
C9
REF
C13
LX
L1
R6
OUTPUT 1.5V
C3
R8
DL
C8
R3
N2
C14
GND
FSET/SYNC
CLKOUT
CLKOUT
VSEL
PGND
CS
OUT
FB
VDD
Figure 12. Application Circuit 4—MAX1962 Tripler Configuration, Preset Output
26
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
MAX1960/MAX1961/MAX1962
C1
0.47µF
INPUT
2.7V TO 5.5V
C+
C2
5 x 10µF
C4
1µF
C-
VCC
AVDD
R5
10Ω
CTL1
VDD
CTL2
BST
C6
2.2µF
D1
COMP
C10
33pF
C9
820pF
R3
10kΩ
MAX1960
REF
C8
0.22µF
C5
0.1µF
N1
C13
4700pF L1
OUTPUT 2.5V, 15A
LX
DL
N2
C3
4 x 47µF
TAIYO-YUDEN
JMK325BJ476MN
R8
1Ω
C14
4700pF
GND
FSET/SYNC
CLKOUT
DH
R7
1Ω
PGND
ILIM
R4
390kΩ
CLKOUT
N.C.
R9
680Ω
C7
560pF
R1
6.84kΩ
FB
R2
3.22kΩ
N1 – IRLR7821
N2 – IRLR7833
Figure 13. Application Circuit—Ceramic Output Capacitors with Type 3 Compensation
______________________________________________________________________________________
27
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Pin Configurations
TOP VIEW
TOP VIEW
CLKOUT 1
20 LX
CLKOUT 1
20 LX
FSET/SYNC 2
19 DH
FSET/SYNC 2
19 DH
N.C. (SEL) 4
CTL1 5
CTL2 6
MAX1960
MAX1961
AVDD 7
17 VCC
SEL 4
16 C+
OUT 5
15 C-
CS 6
17 VCC
MAX1962
14 PGND
FB 8
13 DL
16 C+
15 C-
AVDD 7
14 PGND
FB (OUT) 8
18 BST
EN 3
18 BST
ILIM 3
13 DL
COMP 9
12 VDD
COMP 9
12 VDD
REF 10
11 GND
REF 10
11 GND
QSOP
QSOP
( ) ARE FOR MAX1961.
Package Information
Chip Information
TRANSISTOR COUNT: 4476
PROCESS: BiCMOS
28
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
20 QSOP
E20-1
21-0055
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
REVISION
NUMBER
REVISION
DATE
0
1/03
Initial release
1
6/09
Updated Electrical Characteristics and Compensation with Ceramic Output
Capacitors sections.
DESCRIPTION
PAGES
CHANGED
—
4, 16
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX1960/MAX1961/MAX1962
Revision History
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