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Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Product Highlights
•
•
•
•
•
Ultra-Low Power Consumption
• 11.4μA per Channel at DC with VDD = 3.3V
• 15.4μA per Channel at 100kbps with VDD = 3.3V
• 54.7μA per Channel at 1Mbps with VDD = 3.3V
Wide Supply Range Supports from 1.71V to 5.5V
Reinforced Galvanic Isolation for Digital Signals
• 8-NSOIC with 4mm Creepage and Clearance
Withstands 3kVRMS for 60s (VISO) and
Continuously Withstands 445VRMS (VIOWM)
• 8-WSOIC with 8mm Creepage and Clearance
Withstands 5kVRMS for 60s (VISO) and
Continuously Withstands 848VRMS (VIOWM)
• Withstands ±10kV Surge Between GNDA and
GNDB with 1.2/50μs Waveform
• High CMTI (200kV/μs, min)
Low Propagation Delay and Low Jitter
• Maximum Data Rate Up to 10Mbps
• Low Propagation Delay 51ns (typ) at VDD = 3.3V
• Clock Jitter RMS 15.4ps (typ)
Safety Regulatory Approvals
• UL According to UL1577
• cUL According to CSA Bulletin 5A
• VDE 0884-11 Reinforced Insulation (Pending)
• IECEx and ATEX Intrinsic Safety (IS): Sira 0518
II 1G Ex ia IIC Ga (Pending)
Key Applications
• 4-20mA Loop Process Control
• Battery Management
• Compact Micro PLC
• Parasitically Powered Applications
The MAX22420/1, MAX22820/1 are a family of 2channel, reinforced, ultra-low-power digital galvanic
isolators using Analog Devices’ proprietary process
technology. The MAX22420/1 feature reinforced
isolation with a withstand voltage rating of 3kV RMS for
60 seconds. The MAX22820/1 feature reinforced
isolation with a withstand voltage rating of 5kV RMS for
60 seconds. Devices are rated for operation at ambient
temperature from -40°C to +125°C.
MAX22420, MAX22421
MAX22820, MAX22821
Simplified Application Diagram
5V
0.1μF
VDD
VCC
FIELD
SENSOR
MI CRO
CONTROLLER
GND
GND
VDDA
MAX22820
3.3V
VDDB
OUT1
IN1
24V
0.1μF
VCCI
VCC
4-20mA
DRIVER
OUT2
IN2
GND
GNDA
GNDB
Pin Configurations
TOP VIEW
VDDA
1
IN1
2
IN2
3
GNDA
4
+
MAX22420
MAX22820
8
VDDB
VDDA
1
7
OUT1
OUT1
2
6
OUT2
IN2
3
5
GNDB
GNDA
4
+
MAX22421
MAX22821
8
VDDB
7
IN1
6
OUT2
5
GNDB
IN BOTH NARROW AND WIDE SOIC
These devices transfer digital signals between circuits
with different power domains, using as little as 90.7μW
per channel at 1Mbps (1.8V supply). The ultra-lowpower feature reduces system dissipation, increases
reliability, and enables compact designs.
Devices are available with a glitch rejection filter of either
29ns or 70ns (typ) and with default-high or default-low
outputs. The devices feature low propagation delay and
low clock jitter, which reduces system latency.
Independent 1.71V to 5.5V supplies on each side also
make the devices suitable for use as level translators.
The MAX22420/MAX22820 feature two channels
transferring data in the same direction. The two channels
of the MAX22421/MAX22821 transfer data in opposite
directions.
Ordering Information appears at end of data sheet.
19-101281; Rev 1; 3/22
O n e A n al o g Way , W il mi ng ton , MA 0 1 8 87 U.S.A. | T el: 781.329. 4700 | © 2022 A nal og Devic es, I nc. Al l ri ghts reserved.
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Absolute Maximum Ratings
VDDA to GNDA ..................................................... -0.3V to +6V
Continuous Power Dissipation (TA = +70°C)
VDDB to GNDB ..................................................... -0.3V to +6V
__Narrow SOIC (derate 5.79mW/°C above +70°C) 462.96mW
IN_ on Side A to GNDA ........................................ -0.3V to +6V
__Wide SOIC (derate 11.35mW/°C above +70°C) .. 908.06mW
IN_ on Side B to GNDB ........................................ -0.3V to +6V
Temperature Ratings
OUT_ on Side A to GNDA ................... -0.3V to (VDDA + 0.3)V
__Operating Temperature Range .................. -40°C to +125°C
OUT_ on Side B to GNDB ................... -0.3V to (VDDB + 0.3)V
__Maximum Junction Temperature .............................. +150°C
Short-Circuit Continuous Current
__OUT_ on Side A to GNDA ........................................ ±30mA
__OUT_ on Side B to GNDB ........................................ ±30mA
__Storage Temperature Range ..................... -60°C to +150°C
__Lead Temperature (soldering, 10s) .......................... +300°C
__Soldering Temperature (reflow)................................ +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
8 Narrow SOIC
Package Code
Outline Number
Land Pattern Number
Thermal Resistance, Four Layer Board:
S8MS+24
Junction-to-Ambient (θJA)
172.80ºC/W
Junction-to-Case Thermal Resistance (θJC)
67.60ºC/W
21-0041
90-0096
8 Wide SOIC
Package Code
Outline Number
W8MS+7
Land Pattern Number
Thermal Resistance, Four Layer Board:
90-100146
Junction-to-Ambient (θJA)
Junction-to-Case Thermal Resistance (θJC)
88.10ºC/W
21-100415
42.40ºC/W
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed
information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-”
in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
www.analog.com
Analog Devices | 2
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
DC Electrical Characteristics
(VDDA - VGNDA = 1.71V to 5.5V, VDDB - VGNDB = 1.71V to 5.5V, CL = 15pF, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDDA - VGNDA = 3.3V, VDDB - VGNDB = 3.3V, VGNDA = VGNDB, TA = +25°C, unless otherwise noted.) (Notes 1, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGE
Supply Voltage
VDDA
Relative to GNDA
1.71
5.5
VDDB
Relative to GNDB
1.71
5.5
VDD_ rising
1.5
Undervoltage-Lockout
Threshold
VUVLO_
Undervoltage-Lockout
Threshold Hysteresis
VUVLO_HYST
1.59
1.69
30
V
V
mV
MAX22420, MAX22820 SUPPLY CURRENT (Note 2)
DC, CL = 0pF
5kHz square wave,
CL = 0pF
Side A Supply Current
IDDA
50kHz square
wave, CL = 0pF
500kHz square
wave, CL = 0pF
DC, CL = 0pF
Side B Supply Current
IDDB
5kHz square wave,
CL = 0pF
50kHz square
wave, CL = 0pF
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VDDA = 5V
6.9
21.6
VDDA = 3.3V
6.7
20.8
VDDA = 2.5V
6.6
20.6
VDDA = 1.8V
6.6
20.0
VDDA = 5V
7.6
21.6
VDDA = 3.3V
7.4
21.8
VDDA = 2.5V
7.3
20.6
VDDA = 1.8V
6.6
20.0
VDDA = 5V
13.4
31.5
VDDA = 3.3V
12.9
30.3
VDDA = 2.5V
12.7
29.9
VDDA = 1.8V
12.5
29.0
VDDA = 5V
75.1
129.5
VDDA = 3.3V
72.1
126.1
VDDA = 2.5V
70.6
124.1
VDDA = 1.8V
70.3
117.3
VDDB = 5V
16.1
31.4
VDDB = 3.3V
16.0
30.6
VDDB = 2.5V
15.9
30.3
VDDB = 1.8V
15.9
29.7
VDDB = 5V
16.4
31.6
VDDB = 3.3V
16.2
30.7
VDDB = 2.5V
16.1
30.4
VDDB = 1.8V
15.9
29.8
VDDB = 5V
18.9
34.7
VDDB = 3.3V
17.9
32.9
VDDB = 2.5V
17.6
32.3
VDDB = 1.8V
17.3
31.3
VDDB = 5V
44.7
65.5
µA
µA
Analog Devices | 3
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
(VDDA - VGNDA = 1.71V to 5.5V, VDDB - VGNDB = 1.71V to 5.5V, CL = 15pF, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDDA - VGNDA = 3.3V, VDDB - VGNDB = 3.3V, VGNDA = VGNDB, TA = +25°C, unless otherwise noted.) (Notes 1, 3)
PARAMETER
SYMBOL
CONDITIONS
VDDB = 3.3V
500kHz square
VDDB = 2.5V
wave, CL = 0pF
VDDB = 1.8V
MIN
TYP
MAX
37.2
56.4
33.9
52.3
30.5
46.8
VDDA = 5V
11.4
26.5
VDDA = 3.3V
11.3
25.7
VDDA = 2.5V
11.2
25.4
VDDA = 1.8V
11.1
24.9
VDDA = 5V
12.0
26.6
VDDA = 3.3V
11.8
25.8
VDDA = 2.5V
11.7
25.5
VDDA = 1.8V
11.3
24.9
VDDA = 5V
16.1
33.1
VDDA = 3.3V
15.4
31.6
VDDA = 2.5V
15.1
31.1
VDDA = 1.8V
14.9
30.1
VDDA = 5V
60.1
97.2
VDDA = 3.3V
55.3
91.1
VDDA = 2.5V
53.0
88.1
VDDA = 1.8V
50.4
81.9
VDDB = 5V
11.4
26.5
VDDB = 3.3V
11.3
25.7
VDDB = 2.5V
11.2
25.4
VDDB = 1.8V
11.1
24.9
VDDB = 5V
12.0
26.6
VDDB = 3.3V
11.8
25.8
VDDB = 2.5V
11.7
25.5
VDDB = 1.8V
11.3
24.9
VDDB = 5V
16.1
33.1
VDDB = 3.3V
15.4
31.6
VDDB = 2.5V
15.1
31.1
VDDB = 1.8V
14.9
30.1
VDDB = 5V
60.1
97.2
VDDB = 3.3V
55.3
91.1
VDDB = 2.5V
53.0
88.1
VDDB = 1.8V
50.4
81.9
UNITS
MAX22421, MAX22821 SUPPLY CURRENT (Note 2)
DC, CL = 0pF
5kHz square wave,
CL = 0pF
Side A Supply Current
IDDA
50kHz square
wave, CL = 0pF
500kHz square
wave, CL = 0pF
DC, CL = 0pF
5kHz square wave,
CL = 0pF
Side B Supply Current
IDDB
50kHz square
wave, CL = 0pF
500kHz square
wave, CL = 0pF
µA
µA
LOGIC INTERFACE (IN_, OUT_)
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Analog Devices | 4
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
(VDDA - VGNDA = 1.71V to 5.5V, VDDB - VGNDB = 1.71V to 5.5V, CL = 15pF, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDDA - VGNDA = 3.3V, VDDB - VGNDB = 3.3V, VGNDA = VGNDB, TA = +25°C, unless otherwise noted.) (Notes 1, 3)
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIL
VHYS
Input Leakage Current
ILEAK
CIN
0.7 x
VDD_
1.71V ≤ VDD_ < 2.25V
0.76 x
VDD_
0.7
410
-1
fSW = 1MHz
source
VDD_ -
3.0V ≤ VDD_ ≤ 3.6V
VDD_ -
2.25V ≤ VDD_ ≤
VDD_ -
IOUT = -1mA
2.75V
source
1.71V ≤ VDD_ ≤
1.89V
0.4
0.3
V
0.2
VDD_ 0.2
0.4
IOUT = 2mA sink
3.0V ≤ VDD_ ≤ 3.6V
0.3
2.25V ≤ VDD_ ≤
2.75V
1.71V ≤ VDD_ ≤
1.89V
µA
pF
4.5V ≤ VDD_ ≤ 5.5V
IOUT = 1mA sink
www.analog.com
+1
IOUT = 4mA sink
VOL
V
mV
2
4.5V ≤ VDD_ ≤ 5.5V
UNITS
V
0.8
IOUT = -2mA
Output Voltage Low
MAX
1.71V ≤ VDD_ < 2.25V
source
Output Voltage High
TYP
2.25V ≤ VDD_ ≤ 5.5V
IOUT = -4mA
VOH
MIN
2.25V ≤ VDD_ ≤ 5.5V
VIH
Input Hysteresis
Input Capacitance
CONDITIONS
0.2
V
0.2
Analog Devices | 5
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Dynamic Characteristics—MAX22_2_C/F
(VDDA - VGNDA = 1.71V to 5.5V, VDDB - VGNDB = 1.71V to 5.5V, CL = 15pF, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDDA - VGNDA = 3.3V, VDDB - VGNDB = 3.3V, VGNDA = VGNDB, TA = +25°C, unless otherwise noted.) (Notes 2, 4)
PARAMETER
Common-Mode
Transient Immunity
SYMBOL
CMTI
Maximum Data Rate
DRMAX
Minimum Pulse Width
PWMIN
CONDITIONS
(Note 5)
Glitch Rejection
tPLH
Mbps
46
52
63
47
53
65
50
58
72
4.5V ≤ VDD_ ≤ 5.5V
45
50
61
3.0V ≤ VDD_ ≤ 3.6V
46
51
63
47
52
65
50
56
72
2.75V
IN_ to OUT_, CL =
2.25V ≤ VDD_ ≤
15pF
2.75V
4.5V ≤ VDD_ ≤ 5.5V
6
3.0V ≤ VDD_ ≤ 3.6V
6
2.25V ≤ VDD_ ≤
6
2.75V
4.5V ≤ VDD_ ≤ 5.5V
16
3.0V ≤ VDD_ ≤ 3.6V
17
2.25V ≤ VDD_ ≤ 2.75V
18
1.71V ≤ VDD_ ≤ 1.89V
22
4.5V ≤ VDD_ ≤ 5.5V
16
3.0V ≤ VDD_ ≤ 3.6V
17
2.25V ≤ VDD_ ≤ 2.75V
18
1.71V ≤ VDD_ ≤ 1.89V
22
Propagation Delay
Skew Channel-toChannel (Same
Direction) (Figure 1)
tSCSLH
1.71V ≤ VDD_ ≤ 5.5V
6
tSCSHL
1.71V ≤ VDD_ ≤ 5.5V
6
Propagation Delay
Skew Channel-toChannel (Opposite
Direction)
tSCOLH
1.71V ≤ VDD_ ≤ 5.5V
6
tSCOHL
1.71V ≤ VDD_ ≤ 5.5V
6
Peak Eye Diagram Jitter
tJIT(PK)
1Mbps
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ns
ns
6.5
1.89V
tSPHL
ns
61
1.71V ≤ VDD_ ≤
Propagation Delay
Skew Part-to-Part
(Same Channel)
ns
51
1.89V
tSPLH
100
45
15pF
|tPLH - tPHL|
10
3.0V ≤ VDD_ ≤ 3.6V
1.89V
PWD
kV/μs
37
2.25V ≤ VDD_ ≤
UNITS
200
29
1.71V ≤ VDD_ ≤
Pulse Width Distortion
MAX
24
1.71V ≤ VDD_ ≤
tPHL
TYP
4.5V ≤ VDD_ ≤ 5.5V
IN_ to OUT_, CL =
Propagation Delay
(Figure 1)
MIN
ns
ns
ns
130
ps
Analog Devices | 6
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
(VDDA - VGNDA = 1.71V to 5.5V, VDDB - VGNDB = 1.71V to 5.5V, CL = 15pF, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDDA - VGNDA = 3.3V, VDDB - VGNDB = 3.3V, VGNDA = VGNDB, TA = +25°C, unless otherwise noted.) (Notes 2, 4)
PARAMETER
Clock Jitter RMS
Rise Time (Figure 1)
SYMBOL
tJCLK(RMS)
tR
CONDITIONS
MIN
500kHz clock input, rising/falling edges
TYP
15.4
5
3.0V ≤ VDD_ ≤ 3.6V
5
5
2.75V
1.71V ≤ VDD_ ≤
tF
4.5V ≤ VDD_ ≤ 5.5V
5
3.0V ≤ VDD_ ≤ 3.6V
5
2.25V ≤ VDD_ ≤
CL = 15pF
5
2.75V
1.71V ≤ VDD_ ≤
tUVLO_EN
CL = 15pF, VDD_ rising
Input UVLO to Output
Default (Figure 2)
tUVLO_DE
CL = 15pF, VDD_ falling
Refresh Rate
ns
8
1.89V
Output UVLO to Output
Data Valid (Figure 2)
ns
8
1.89V
Fall Time (Figure 1)
UNITS
ps
4.5V ≤ VDD_ ≤ 5.5V
2.25V ≤ VDD_ ≤
CL = 15pF
MAX
1.1
FR
1.7
ms
0.5
ms
10
kHz
Dynamic Characteristics—MAX22_2_B/E
(VDDA - VGNDA = 1.71V to 5.5V, VDDB - VGNDB = 1.71V to 5.5V, CL = 15pF, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDDA - VGNDA = 3.3V, VDDB - VGNDB = 3.3V, VGNDA = VGNDB, TA = +25°C, unless otherwise noted.) (Notes 2, 4)
PARAMETER
Common-Mode
Transient Immunity
SYMBOL
CMTI
Maximum Data Rate
DRMAX
Minimum Pulse Width
PWMIN
CONDITIONS
(Note 5)
Glitch Rejection
tPLH
kV/μs
10
Mbps
100
ns
ns
80
109
122
136
3.0V ≤ VDD_ ≤ 3.6V
110
123
138
110
124
140
115
129
145
4.5V ≤ VDD_ ≤ 5.5V
109
120
136
3.0V ≤ VDD_ ≤ 3.6V
110
121
138
110
122
140
115
126
145
2.25V ≤ VDD_ ≤
15pF
2.75V
1.89V
IN_ to OUT_, CL =
2.25V ≤ VDD_ ≤
15pF
2.75V
1.89V
UNITS
200
70
1.71V ≤ VDD_ ≤
www.analog.com
MAX
60
1.71V ≤ VDD_ ≤
tPHL
TYP
4.5V ≤ VDD_ ≤ 5.5V
IN_ to OUT_, CL =
Propagation Delay
(Figure 1)
MIN
ns
Analog Devices | 7
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
(VDDA - VGNDA = 1.71V to 5.5V, VDDB - VGNDB = 1.71V to 5.5V, CL = 15pF, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDDA - VGNDA = 3.3V, VDDB - VGNDB = 3.3V, VGNDA = VGNDB, TA = +25°C, unless otherwise noted.) (Notes 2, 4)
PARAMETER
Pulse Width Distortion
SYMBOL
PWD
tSPLH
Propagation Delay
Skew Part-to-Part
(Same Channel)
tSPHL
|tPLH - tPHL|
CONDITIONS
1.71V ≤ VDD_ ≤
MIN
TYP
5.5V
MAX
UNITS
15
ns
4.5V ≤ VDD_ ≤ 5.5V
27
3.0V ≤ VDD_ ≤ 3.6V
28
2.25V ≤ VDD_ ≤ 2.75V
30
1.71V ≤ VDD_ ≤ 1.89V
30
4.5V ≤ VDD_ ≤ 5.5V
27
3.0V ≤ VDD_ ≤ 3.6V
28
2.25V ≤ VDD_ ≤ 2.75V
30
1.71V ≤ VDD_ ≤ 1.89V
30
ns
Propagation Delay
Skew Channel-toChannel (Same
Direction) (Figure 1)
tSCSLH
1.71V ≤ VDD_ ≤ 5.5V
10
tSCSHL
1.71V ≤ VDD_ ≤ 5.5V
10
Propagation Delay
Skew Channel-toChannel (Opposite
Direction)
tSCOLH
1.71V ≤ VDD_ ≤ 5.5V
10
tSCOHL
1.71V ≤ VDD_ ≤ 5.5V
10
Peak Eye Diagram Jitter
tJIT(PK)
1Mbps
220
ps
500kHz clock input, rising/falling edges
26.5
ps
Clock Jitter RMS
Rise Time (Figure 1)
tJCLK(RMS)
tR
CL = 15pF
ns
4.5V ≤ VDD_ ≤ 5.5V
5
3.0V ≤ VDD_ ≤ 3.6V
5
2.25V ≤ VDD_ ≤
5
2.75V
1.71V ≤ VDD_ ≤
tF
CL = 15pF
4.5V ≤ VDD_ ≤ 5.5V
5
3.0V ≤ VDD_ ≤ 3.6V
5
2.25V ≤ VDD_ ≤
5
2.75V
1.71V ≤ VDD_ ≤
tUVLO_EN
CL = 15pF, VDD_ rising
Input UVLO to Output
Default (Figure 2)
tUVLO_DE
CL = 15pF, VDD_ falling
Refresh Rate
FR
ns
8
1.89V
Output UVLO to Output
Data Valid (Figure 2)
ns
8
1.89V
Fall Time (Figure 1)
ns
1.1
10
1.7
ms
0.5
ms
kHz
Note 1: All devices are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design and
characterization.
Note 2: Not production tested. Guaranteed by design and characterization.
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Analog Devices | 8
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Note 3: All currents into the device are positive. All currents out of the device are negative. All voltages are referenced to their
respective ground (GNDA or GNDB), unless otherwise noted.
Note 4: All measurements taken with VDDA = VDDB, unless otherwise noted.
Note 5: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output. CMTI applies to
both rising and falling common-mode voltage edges. Tested with the transient generator connected between GNDA and
GNDB (VCM = 1000V).
ESD Protection
PARAMETER
SYMBOL
CONDITIONS
VALUE
UNITS
Human Body Model, All Pins
±4
kV
IEC 61000-4-2 Contact, GNDB to GNDA
±6
kV
ESD
Safety Regulatory Approvals
UL
The devices are certified under UL1577. For more details, refer to File E351759.
The MAX22420/MAX22421 are rated up to 3000VRMS isolation voltage for single protection.
The MAX22820/MAX22821 are rated up to 5000VRMS isolation voltage for single protection.
cUL (Equivalent to CSA notice 5A)
The MAX22420/MAX22421 are certified up to 3000VRMS for single protection. For more details, refer to File E351759.
The MAX22820/MAX22821 are certified up to 5000VRMS for single protection. For more details, refer to File E351759.
VDE (Pending)
The MAX22420/MAX22421 are certified to DIN VDE V 0884-11: 2017-1. Reinforced Insulation, Maximum Transient Isolation
Voltage 4242VPK, Maximum Repetitive Peak Isolation Voltage 630VPK.
The MAX22820/MAX22821 are certified to DIN VDE V 0884-11: 2017-1. Reinforced Insulation, Maximum Transient Isolation
Voltage 7070VPK, Maximum Repetitive Peak Isolation Voltage 1200VPK.
CSA/Sira (Pending)
The devices are certified for use in intrinsic safety (IS) to IS applications under ATEX and IECEx.
ATEX: EN 60079-0:2012+A11:2013 and EN 60079-11:2012
IECEx: IEC 60079-0:2011 Edition 6 and IEC 60079-11:2011 Edition 6
II 1G Ex ia IIC Ga
These couplers are suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings
shall be ensured by means of suitable protective circuits.
www.analog.com
Analog Devices | 9
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Test Circuits and Timing Diagrams
VDDA
IN1, IN2
VDDA
0.1µF
0.1µF
VDDA
VDDB
TEST
SOURCE
GNDA
VDDB
50%
GNDB
tSCSLH
RL
VDDB
OUT2
(A)
tPHL
50%
CL
GNDB
tPLH
OUT1
OUT_
GNDA
50%
VDDB
MAX2242_
MAX2282_
IN_
50%
GNDB
tSCSHL
90%
50%
50%
10%
tF
tR
(B)
Figure 1. Test Circuit (A) and Timing Diagram (B)
www.analog.com
Analog Devices | 10
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
0.1µF
VDDA
VDDA
0.1µF
VDDB
VUVLO,
FALLING
VDDA
GNDA
VDDA
VDDB
VDDB
VDDB
VDDB
MAX22_2_B/C
100k
IN_
VUVLO,
FALLING
VUVLO,
RISING
GNDB
OUT_
GNDA
GNDB
VDDB
100k
CL
OUT_
50%
GNDB
tUVLO_DE
tUVLO_EN
0.1µF
VDDA
VDDA
0.1µF
VUVLO,
FALLING
VDDB IN_, VDDA
GNDA
VDDA
VDDB
VDDB
VDDB
MAX22_2_E/F
VDDA
VDDB
100k
IN_
VUVLO,
FALLING
VUVLO,
RISING
GNDB
OUT_
GNDA
GNDB
VDDB
100k
CL
OUT_
50%
GNDB
(A)
*THE 100k RESISTORS ARE USED TO DEMONSTRATE THE DIFFERENCE BETWEEN
OUTPUT DEFAULT AND OUTPUT HIGH-Z. IT IS NOT REQUIRED BY APPLICATIONS.
SEE STARTUP AND UNDERVOLTAGE LOCKOUT SECTION FOR MORE INFORMATION.
tUVLO_DE
tUVLO_EN
(B)
Figure 2. Enable to Output Timing Diagrams (tUVLO_EN, tUVLO_DE)
www.analog.com
Analog Devices | 11
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Table 1. Insulation Characteristics (Narrow SOIC)
PARAMETER
Partial Discharge Test
Voltage
SYMBOL
CONDITIONS
VALUE
UNITS
VPR
Method B1 = VIORM x 1.875 (t = 1s, partial discharge < 5pC)
1182
VP
Maximum Repetitive Peak
Isolation Voltage
VIORM
(Note 6)
630
VP
Maximum Working Isolation
Voltage
VIOWM
Continuous RMS voltage (Note 6)
445
VRMS
Maximum Transient Isolation
Voltage
VIOTM
t = 1s (Note 6)
4242
VP
fSW = 60Hz, duration = 60s (Notes 6, 7)
3000
VRMS
Reinforced Insulation, test method per IEC 60065,
VTEST = 1.6 x VIOSM = 10000VPEAK (Notes 6, 9)
6250
VP
Maximum Withstanding
Isolation Voltage
Maximum Surge Isolation
Voltage
Isolation Resistance
VISO
VIOSM
RIO
Barrier Capacitance Side A
to Side B
CIO
Minimum Creepage
Distance
Minimum Clearance
Distance
> 1012
VIO = 500V, 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500V, TS = 150°C
> 109
fSW = 1MHz (Note 8)
Ω
1.5
pF
CPG
4
mm
CLR
4
mm
Distance through insulation
0.021
mm
Material Group I (IEC 60112)
> 600
Internal Clearance
Comparative Tracking Index
VIO = 500V, TA = 25°C
CTI
Climate Category
40/125/21
Pollution Degree
(DIN VDE 0110, Table 1)
2
Table 2. Insulation Characteristics (Wide SOIC)
PARAMETER
Partial Discharge Test
Voltage
SYMBOL
CONDITIONS
VALUE
UNITS
VPR
Method B1 = VIORM x 1.875 (t = 1s, partial discharge < 5pC)
2250
VP
Maximum Repetitive Peak
Isolation Voltage
VIORM
(Note 6)
1200
VP
Maximum Working Isolation
Voltage
VIOWM
Continuous RMS voltage (Note 6)
848
VRMS
Maximum Transient Isolation
Voltage
VIOTM
t = 1s (Note 6)
7070
VP
fSW = 60Hz, duration = 60s (Notes 6, 7)
5000
VRMS
Reinforced Insulation, test method per IEC 60065,
VTEST = 1.6 x VIOSM = 12800VPEAK (Notes 6, 9)
8000
VP
Maximum Withstanding
Isolation Voltage
Maximum Surge Isolation
Voltage
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VISO
VIOSM
Analog Devices | 12
MAX22420, MAX22421
MAX22820, MAX22821
Isolation Resistance
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
RIO
Barrier Capacitance Side A
to Side B
CIO
Minimum Creepage
Distance
Minimum Clearance
Distance
> 1012
VIO = 500V, 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500V, TS = 150°C
> 109
fSW = 1MHz (Note 8)
Ω
1.5
pF
CPG
8
mm
CLR
8
mm
Distance through insulation
0.021
mm
Material Group I (IEC 60112)
> 600
Internal Clearance
Comparative Tracking Index
VIO = 500V, TA = 25°C
CTI
Climate Category
Pollution Degree
(DIN VDE 0110, Table 1)
40/125/21
2
Note 6: VISO, VIOTM, VIOWM, VIORM, and VIOSM are defined by the IEC 60747-5-5 standard.
Note 7: Product is qualified at VISO for 60s and 100% production tested at 120% of VISO for 1s.
Note 8: Capacitance is measured with all pins on field-side and logic-side tied together.
Note 9: Devices are immersed in oil during surge characterization.
www.analog.com
Analog Devices | 13
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Typical Operating Characteristics
(VDDA - VGNDA = +3.3V, VDDB - VGNDB = +3.3V, VGNDA = VGNDB, TA = +25°C, unless otherwise noted.)
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Analog Devices | 14
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
(VDDA - VGNDA = +3.3V, VDDB - VGNDB = +3.3V, VGNDA = VGNDB, TA = +25°C, unless otherwise noted.)
www.analog.com
Analog Devices | 15
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
(VDDA - VGNDA = +3.3V, VDDB - VGNDB = +3.3V, VGNDA = VGNDB, TA = +25°C, unless otherwise noted.)
www.analog.com
Analog Devices | 16
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Pin Configurations
TOP VIEW
VDDA
1
IN1
2
+
8
VDDB
VDDA
1
7
OUT1
IN1
2
MAX22420
+
8
VDDB
7
OUT1
MAX22820
IN2
3
6
OUT2
IN2
3
6
OUT2
GNDA
4
5
GNDB
GNDA
4
5
GNDB
VDDA
1
8
VDDB
VDDA
1
8
VDDB
OUT1
2
7
IN1
OUT1
2
7
IN1
+
MAX22421
+
MAX22821
IN2
3
6
OUT2
IN2
3
6
OUT2
GNDA
4
5
GNDB
GNDA
4
5
GNDB
NARROW SOIC
WIDE SOIC
Pin Descriptions
PIN
MAX22420/ MAX22421/
MAX22820 MAX22821
NAME
FUNCTION
Power Supply Input for Side A. Bypass VDDA to GNDA with a 0.1μF ceramic capacitor as
1
1
VDDA
2
—
IN1
—
2
OUT1
3
3
IN2
4
4
GNDA
Ground Reference for Side A.
5
5
GNDB
Ground Reference for Side B.
6
6
OUT2
Logic Output 2 on Side B.
7
—
OUT1
Logic Output 1 on Side B.
—
7
IN1
8
8
VDDB
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close as possible to the pin.
Logic Input 1 on Side A.
Logic Output 1 on Side A.
Logic Input 2 on Side A.
Logic Input 1 on Side B.
Power Supply Input for Side B. Bypass VDDB to GNDB with a 0.1μF ceramic capacitor as
close as possible to the pin.
Analog Devices | 17
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Functional Diagrams
VDDB
VDDA
IN1
OUT1
OUT1
IN2
OUT2
IN2
OUT2
GNDA
GNDB
GNDA
GNDB
VDDA
www.analog.com
MAX22420
MAX22820
MAX22421
MAX22821
VDDB
IN1
Analog Devices | 18
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Detailed Description
The MAX22_2_ are a family of 2-channel reinforced ultra-low-power digital isolators. The MAX22_2_ consume ultra-low
power not only in DC but also across the entire operating speed range up to 10Mbps. The family offers two unidirectional
channel configurations to accommodate any 2-channel design.
The MAX22_20 feature two channels transferring digital signals in one direction. The MAX22_21 have one channel to
transmit data in one direction and the other channel to transmit in the opposite direction.
The MAX22420/1 are available in an 8-pin narrow-body SOIC package with 4mm creepage and clearance and are rated
up to 3kVRMS. The MAX22820/1 are available in an 8-pin wide-body SOIC package with 8mm creepage and clearance
and are rated up to 5kVRMS. This family of digital isolators offers ultra-low-power operation, high electromagnetic
interference (EMI) immunity, and stable temperature performance through Analog Devices’ proprietary process
technology. The devices isolate different ground domains and block high-voltage/high-current transients from sensitive or
human interface circuitry.
The family of devices has a maximum data rate of 10Mbps and can be ordered with two glitch filter options and defaulthigh or default-low outputs. The default is the state the output assumes when the input is open circuit. The B/E versions
have 70ns (typ) glitch filter and C/F versions have 29ns (typ) glitch filter. The devices have two supply inputs (V DDA and
VDDB) that independently set the logic levels on either side of device. V DDA and VDDB are referenced to GNDA and
GNDB, respectively. The family also features a refresh circuit to ensure output accuracy when an input remains in the
same state indefinitely.
Digital Isolation
The MAX22_2_ provide reinforced galvanic isolation for digital signals that are transmitted between two ground domains.
The MAX22420/1 withstand differences of up to 3kVRMS for up to 60 seconds, and up to 630VPEAK of continuous
isolation. The MAX22820/1 withstand differences of up to 5kV RMS for up to 60 seconds, and up to 1200kVPEAK of
continuous isolation.
Level Shifting
The wide supply voltage range of both VDDA and VDDB allows the family of devices to be used for level translation in
addition to isolation. VDDA and VDDB can be independently set to any voltage from 1.71V to 5.5V. The supply voltage
sets the logic level on the corresponding side of the isolator.
Unidirectional Channels
Each channel of the devices is unidirectional; it only passes data in one direction, as indicated in the Functional Diagrams.
Each device features two unidirectional channels that operate independently with guaranteed data rates from DC up to
10Mbps. The output driver of each channel is push-pull, eliminating the need for pullup resistors. The outputs are able to
drive both TTL and CMOS logic inputs.
Startup and Undervoltage Lockout
The VDDA and VDDB supplies are both internally monitored for undervoltage conditions. Undervoltage events can occur
during power-up, power-down, or during normal operation due to a sagging supply voltage. When an undervoltage
condition is detected on the output supply, the outputs go to high-Z regardless of the state of the inputs. When an
undervoltage condition is detected on the input supply, the outputs go to default regardless of the state of the inputs as
seen in Table 3. During the output supply rises above the UVLO (Powered), the output transitions from high-Z to default
state for a short period of time before becoming valid. During the output supply drops below the UVLO (Undervoltage),
the output transitions to high-Z immediately. Figure 2 shows the output UVLO to output valid and input UVLO to output
default timing diagrams. Figure 3 through Figure 6 show the behavior of the outputs during power-up and power-down.
Table 3. Output Behavior During Undervoltage Condition
VIN_
VDDA
VDDB
VOUTA
VOUTB
1
Powered
Powered
High
High
0
Powered
Powered
Low
Low
X
Undervoltage
Powered
High-Z
Default
X
Powered
Undervoltage
Default
High-Z
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Analog Devices | 19
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Figure 3. Undervoltage Lockout Behavior MAX22_2_B/C, Input
High, Weak Outputs Pulldown to Ground
Figure 4. Undervoltage Lockout Behavior MAX22_2_E/F, Input
High, Weak Outputs Pullup to Supply
Figure 5. Undervoltage Lockout Behavior MAX22_2_B/C, Input
Low, Weak Outputs Pulldown to Ground
Figure 6. Undervoltage Lockout Behavior MAX22_2_E/F, Input
Low, Weak Outputs Pullup to Supply
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Analog Devices | 20
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Safety Limits
Damage to the IC can result in a low-resistance path to ground or to the supply and, without current limiting, the devices
can dissipate excessive amounts of power. Excessive power dissipation can damage the die and result in damage to the
isolation barrier, potentially causing downstream issues. Table 4 shows the safety limits for the MAX22_2_.
The maximum safety temperature (TS) for the device is the 150°C maximum junction temperature specified in the
Absolute Maximum Ratings. The power dissipation (PD) and junction-to-ambient thermal impedance (𝜃 JA) determine the
junction temperature. Thermal impedance values (𝜃 JA and 𝜃 JC) are available in the Package Information section and
power dissipation calculations are discussed in the Calculating Power Dissipation section. Calculate the junction
temperature (TJ) as:
TJ = TA + (PD x 𝜃 JA)
Figure 7 shows the thermal derating curves for safety limiting the power of the device. Figure 8 shows the thermal derating
curve for safety limiting the current of the device. Ensure that the junction temperature does not exceed 150°C.
Figure 7. Thermal Derating Curve for Safety Power Limiting
Figure 8. Thermal Derating Curve for Safety Current Limiting
Table 4. Safety Limiting Values
PARAMETER
SYMBOL
TEST CONDITIONS
Safety Current on Any Pin
(No Damage to Isolation Barrier)
IS
TJ = 150°C, TA = 25°C
Total Safety Power Dissipation
PS
TJ = 150°C, TA = 25°C
Maximum Safety Temperature
TS
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MAX
UNIT
300
mA
8 Narrow SOIC
723
8 Wide SOIC
1418
150
mW
°C
Analog Devices | 21
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Applications Information
Power-Supply Sequencing
The family of devices does not require special power-supply sequencing. The logic levels are set independently on either
side by VDDA and VDDB. Each supply can be present over the entire specified range regardless of the level or presence
of the other supply.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data errors, bypass V DDA and VDDB with 0.1μF low-ESR ceramic
capacitors to GNDA and GNDB, respectively. Place the bypass capacitors as close to the power supply input pins as
possible.
Layout Considerations
The PCB designer should follow some critical recommendation in order to get the best performance from the design.
•
•
•
Keep the input/output traces as short as possible. To keep signal paths low inductance, avoid using vias.
Have a solid ground plane underneath the high-speed signal layer.
Keep the area underneath the devices free from ground and signal planes. Any galvanic or metallic connection
between the field-side and logic-side defeats the isolation.
Calculating Power Dissipation
The required current for a given supply (VDDA or VDDB) can be estimated by summing the current required for each
channel. The supply current for a channel depends on whether the channel is an input or an output, the channel’s data
rate, and the capacitive or resistive load if it is an output. The typical current for an input or output at any data rate can be
estimated from the graphs in Figure 9 and Figure 10. Note that the data in Figure 9 and Figure 10 are extrapolated from
the supply current measurements in a typical operating condition.
The total current for a single channel is the sum of the no load current (shown in Figure 9 and Figure 10), which is a
function of voltage and data rate, and the load current, which depends on the type of load. Current into a capacitive load
is a function of the load capacitance, the switching frequency, and the supply voltage.
ICL = CL × fSW × VDD
where:
ICL is the current required to drive the capacitive load.
CL is the load capacitance on the isolator’s output pin.
fSW is the switching frequency (bits per second/2).
VDD is the supply voltage on the output side of the isolator.
Current into a resistive load depends on the load resistance, the supply voltage and the average duty cycle of the data
waveform. The DC load current can be conservatively estimated by assuming the output is always high.
IRL = VDD ÷ RL
where:
IRL is the current required to drive the resistive load.
VDD is the supply voltage on the output side of the isolator.
RL is the load resistance on the isolator’s output pin.
Example (shown in Figure 11): A MAX22421C is operating with VDDA = 2.5V, VDDB = 3.3V, channel 1 operating at
2Mbps with a 15pF capacitive load, and channel 2 operating at 10Mbps with a 10kΩ resistive load. See Table 5 and
Table 6 for VDDA and VDDB supply-current calculation worksheets.
www.analog.com
Analog Devices | 22
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
VDDA must supply:
•
•
•
Channel 1 is an output channel operating at 2.5V and 2Mbps, consuming 23.93μA, estimated from Figure 10.
Channel 2 is an input channel operating at 2.5V and 10Mbps, consuming 393.35μA, estimated from Figure 9.
ICL on Channel 1 for 15pF capacitor at 2.5V and 2Mbps is 37.5μA.
Total current for side A = 454.8μA (typ)
VDDB must supply:
•
•
•
Channel 1 is an input channel operating at 3.3V and 2Mbps, consuming 82.92μA, estimated from Figure 9.
Channel 2 is an output channel operating at 3.3V and 10Mbps, consuming 102.49μA, estimated from Figure 10.
IRL on Channel 2 for 10kΩ resistor switching at 50% duty cycle and at 3.3V is 165μA.
Total current for side B = 350.4μA (typ)
Figure 9. Supply Current per Input Channel (Estimated)
Figure 10. Supply Current per Output Channel (Estimated)
2.5V
.1μF
3.3V
VDDA
OUT1
2Mbps
MAX22421C/F
.1 μF
VDDB
IN1
2Mbps
15pF
10Mbps
IN2
OUT2
10Mbps
10k
GNDA
GNDB
Figure 11. Example Circuit for Supply Current Calculation
www.analog.com
Analog Devices | 23
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Table 5. Side A Supply Current Calculation Worksheet
SIDE A
VDDA = 2.5V
CHANNEL IN/OUT
DATA RATE
(Mbps)
LOAD
TYPE
LOAD
NO LOAD
CURRENT (μA)
LOAD CURRENT (μA)
Capacitive
15pF
23.93
2.5V x 1MHz x 15pF = 37.5μA
1
OUT
2
2
IN
10
393.35
Total: 454.8μA
Table 6. Side B Supply Current Calculation Worksheet
SIDE B
VDDB = 3.3V
CHANNEL IN/OUT
DATA RATE
(Mbps)
1
IN
2
2
OUT
10
LOAD
TYPE
LOAD
NO LOAD
CURRENT (μA)
LOAD CURRENT (μA)
82.92
Resistive
10kΩ
102.49
3.3V/10kΩ x 0.5 = 165μA
Total: 350.4μA
www.analog.com
Analog Devices | 24
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Typical Application Circuits
4-20mA Loop Powered Control
24V
ISOLA TED
DC-DC
3.3V
5V
12V
.1μF
.1μF
.1μF
MAX22820
FIELD
SENSOR
SPI
MI CRO
CONTROLLER
PWMA
PWMA
PWMB
PWMB
VCCI
4-20mA
VCC
PLC
MAX 12900
RSENSE
GNDA
GNDB
Product Selector Guide
MAX22 8 2 0 E A
PACKAGE TYPE
4: NSOIC
8: WSOIC
CHANNEL
CONFIGURATION
0: 2/0
1: 1/1
GLITCH REJECTION
B/E: 70ns
C/F: 29ns
www.analog.com
W
A +
LEAD-FREE/ ROHS COMPLIANT
PINS
A: 8
PACKAGE TYPE
S: NSOIC
W: W SOIC
TEMP RANGE
-40 °C TO +12 5°C
Analog Devices | 25
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Ordering Information
CHANNEL
CONFIGURATION
GLITCH
REJECTION (ns)
DEFAULT
OUTPUT
PIN-PACKAGE
TEMPERATURE
RANGE (°C)
MAX22420BASA+*
2/0
70
High
8 Narrow SOIC
-40 to +125
MAX22420CASA+*
2/0
29
High
8 Narrow SOIC
-40 to +125
MAX22420EASA+*
2/0
70
Low
8 Narrow SOIC
-40 to +125
MAX22420FASA+*
2/0
29
Low
8 Narrow SOIC
-40 to +125
MAX22421BASA+
1/1
70
High
8 Narrow SOIC
-40 to +125
MAX22421CASA+
1/1
29
High
8 Narrow SOIC
-40 to +125
MAX22421EASA+*
1/1
70
Low
8 Narrow SOIC
-40 to +125
MAX22421FASA+*
1/1
29
Low
8 Narrow SOIC
-40 to +125
MAX22820BAWA+*
2/0
70
High
8 Wide SOIC
-40 to +125
MAX22820CAWA+*
2/0
29
High
8 Wide SOIC
-40 to +125
MAX22820EAWA+
2/0
70
Low
8 Wide SOIC
-40 to +125
MAX22820FAWA+*
2/0
29
Low
8 Wide SOIC
-40 to +125
MAX22821BAWA+*
1/1
70
High
8 Wide SOIC
-40 to +125
MAX22821CAWA+*
1/1
29
High
8 Wide SOIC
-40 to +125
MAX22821EAWA+*
1/1
70
Low
8 Wide SOIC
-40 to +125
MAX22821FAWA+*
1/1
29
Low
8 Wide SOIC
-40 to +125
PART NUMBER
*Future product—contact Analog Devices for availability.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Chip Information
PROCESS: BiCMOS
www.analog.com
Analog Devices | 26
MAX22420, MAX22421
MAX22820, MAX22821
Reinforced, Ultra-Low-Power,
Two-Channel Digital Isolators
Revision History
REVISION
NUMBER
0
1
REVISION
DESCRIPTION
DATE
2/22
Release for Market Intro
3/22
Remove future product asterisks in Ordering Information table
PAGES
CHANGED
—
26
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their
respective owners.
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Analog Devices | 27
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