19-3155; Rev 0; 5/04
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
The MAX8543/MAX8544 current-mode, constant-frequency PWM buck controllers operate from a 3V to
13.2V input supply and generate adjustable 0.8V to 0.9
x VIN output voltages at loads up to 25A. They feature
adjustable switching frequency and synchronization for
noise-sensitive applications.
The MAX8543/MAX8544 can start with (or without) a preexisting bias on the output, without discharging the output. This feature simplifies tracking supply designs for
core and I/O applications and redundant supply designs.
The MAX8543/MAX8544 use the DC resistance of the
output inductor as the current-sense element for lossless, low-cost current sensing. The current-sense
threshold can be set to four discrete levels to accommodate inductors with different DC resistance values.
The MAX8544 features a power-OK monitor and two
MAX8544 controllers that can operate at 180° out-ofphase for dual-output applications.
Features
♦ Prebias Startup/Monotonic
♦ 1% Output Accuracy
♦ Ceramic, Polymer, or Electrolytic Capacitors
♦ 200kHz to 1MHz Adjustable Frequency
♦ 160kHz to 1.2MHz Synchronization
♦ Lossless, Foldback Current Limit
♦ Overvoltage Protection
♦ Enable (On/Off)
♦ Adjustable Soft-Start
♦ MAX8544
Latch-Off/Autorecovery
Power-OK Monitor
Out-of-Phase Clock Output
Ordering Information
Applications
Base Stations
TEMP RANGE
PIN-PACKAGE
Networks and Telecom
MAX8543EEE
PART
-40°C to +85°C
16 QSOP
Storage
MAX8544EEP
-40°C to +85°C
20 QSOP
Servers
Pin Configurations appear at end of data sheet.
Typical Operating Circuit
INPUT 3V TO 13.2V
IN
ON
OFF
VL
EN
FSYNC
OPTIONAL
SYNCHRONIZATION
VIN = 3V
TO 5.5V
BST
SS
MAX8543
DH
LX
COMP
OUTPUT
0.8V TO 0.9 x VIN
UP TO 25A
DL
ILIM
GND
PGND
CS+
CSPOK (MAX8544)
FB
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8543/MAX8544
General Description
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
ABSOLUTE MAXIMUM RATINGS
IN, EN, CS+, CS- to GND .......................................-0.3V to +14V
BST, DH to LX ..........................................................-0.3V to +6V
BST to GND ............................................................-0.3V to +20V
DL, COMP, ILIM2, SS, SYNCO,
FSYNC to GND .......................................-0.3V to (VVL + 0.3V)
VL, FB, POK, ILIM1, ILIM, MODE to GND ................-0.3V to +6V
PGND to GND .......................................................-0.3V to +0.3V
Continuous Power Dissipation (TA = +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C) .......666.7mW
20-Pin QSOP (derate 9.1mW/°C above +70°C) .......727.3mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 13.2V, VBST - VLX = 5V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
Operating Input Voltage Range
VL connected to IN for VIN < 5.5V
Quiescent Supply Current
VFB = 0.9V, no switching
Shutdown Supply Current
MIN
TYP
3.0
2
MAX
13.2
V
3
mA
EN = GND, MODE = GND, IN not connected to VL
10
EN = GND, VL = IN, MODE = GND
20
VL Undervoltage-Lockout Trip Level
VVL rising, typical hysteresis is 80mV
2.52
Output Voltage Adjust Range (VOUT)
(Note 1)
0.8
VL Output Voltage
5.5V < VIN < 13.2V, 1mA < IVL < 75mA
4.5
2.7
UNITS
2.88
µA
V
V
5
VL Output Current
5.5
V
75
mA
VOLTAGE REFERENCE
SS Shutdown Resistance
From SS to GND, VEN = 0V
SS Soft-Start Current
VREF = 0.625V
Soft-Start Ramp Time
Output from 0% to 100%, CREF = 0.01µF to 1µF
14
20
100
Ω
24
34
µA
33
ms/µF
ERROR AMPLIFIER
FB Regulation Voltage
Transconductance
0.792
0.8
0.808
V
70
110
160
µS
COMP Shutdown Resistance
From COMP to GND, VEN = 0V
20
100
Ω
FB Input Leakage Current
VFB = 0.9V
5
100
nA
+0.9
V
FB Input Common-Mode Range
-0.1
CURRENT-SENSE AMPLIFIER
Voltage Gain
VOUT = 0 to 13V
VILIM1 = 0V
8.8
11
13.2
VILIM1 = (1/3)VVL
4.8
6
7.2
VILIM1 = (2/3)VVL
3.2
4
4.8
VILIM1 = VVL
2.4
3
3.6
5
5.5
µA
+1
µA
V/V
CURRENT LIMIT
ILIM2 Output Current (MAX8544 Only)
RILIM2 = 50kΩ to 200kΩ
4.5
ILIM1 Input Current
VILIM1 = 0V or VVL
-1
2
_______________________________________________________________________________________
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
(VIN = 13.2V, VBST - VLX = 5V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
VCS+ - VCS-, VILIM1 = 0V
MIN
TYP
MAX
UNITS
38.5
50
56.5
VCS+ - VCS-, VILIM1 = (1/3)VVL
85
100
115
VCS+ - VCS-, VILIM1 = (2/3)VVL
127.5
150
172.5
170
200
230
VLX - VPGND, RILIM2 = 50kΩ (MAX8544 only)
-42.5
-50
-57.5
VLX - VPGND, RILIM2 = 200kΩ (MAX8544 only)
-160
-200
-240
VLX - VPGND, VFB = 0.8V (MAX8543 only)
-110
-130
-150
VLX - VPGND, VFB = 0V (MAX8543 only)
-20
-30
-40
Negative Current-Limit Threshold
% of positive-direction current limit VLX - VPGND
-25
-50
-85
%
CS+, CS- Input Current
VCS+ = VCS- = 0 or 5V
-40
+40
µA
0
13.2
V
Current-Limit Threshold
VCS+ - VCS-, VILIM1 = VVL
CS+, CS- Input Common-Mode Range
mV
OSCILLATOR
Switching Frequency
RFSYNC = 18.2kΩ
800
RFSYNC = 158kΩ
Minimum Off-Time
Measured at DH
Minimum On-Time
Measured at DH
1000
150
FSYNC Synchronization Range
160
FSYNC Input High Pulse Width
100
FSYNC Input Low Pulse Width
100
RFSYNC = 18.2kΩ, free-running mode,
at maximum duty cycle
SYNCO Output Low Level
ISYNCO = 5mA
SYNCO Output High Level
ISYNCO = 5mA
165
kHz
220
270
90
145
ns
1200
kHz
ns
ns
ns
FSYNC Rise/Fall Time
SYNCO Phase Shift from DH Rising
1200
200
180
100
ns
195
Degrees
0.4
V
VVL - 1V
V
MOSFET DRIVERS
DH On-Resistance, High State
DH On-Resistance, Low State
DL On-Resistance, High State
DL On-Resistance, Low State
Break-Before-Make Dead Time
LX, BST, IN Leakage Current
(VBST - VLX) = 5V
1
(VBST - VLX) = 3V
1.2
(VBST - VLX) = 5V
1
(VBST - VLX) = 3V
1.2
VVL = 5V
1
VVL = 3V
1.2
VVL = 5V
0.6
VVL = 3V
0.8
Low-side off to high-side on
55
High-side off to low-side on
40
VBST = 18.7V, VLX = 13.2V, VIN = 13.2V
2.5
2.5
2.5
1.7
Ω
Ω
Ω
Ω
ns
5
µA
THERMAL PROTECTION
Thermal Shutdown
Rising temperature
Thermal-Shutdown Hysteresis
+160
°C
15
°C
_______________________________________________________________________________________
3
MAX8543/MAX8544
ELECTRICAL CHARACTERISTICS (continued)
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 13.2V, VBST - VLX = 5V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
88
91
94
%
POK
Power-OK Threshold
VFB rising, percent of VOUT,
typical hysteresis is 3%
POK Output Voltage, Low
VFB = 0.6V, IPOK = 2mA
POK Leakage Current, High
VPOK = 5.5V
25
200
mV
0.001
1
µA
+115
+120
%
0.4
V
OVERVOLTAGE PROTECTION (OVP)
Output Overvoltage Fault-Trip level
Rising edge compared to regulation set point;
triggers after one or two clock cycles
+110
MODE CONTROL
MODE Logic-Level Low
3V ≤ VVL ≤ 5.5V
MODE Logic-Level High
3V ≤ VVL ≤ 5.5V
1.8
VMODE = 0V
-1
MODE Input Current
MODE = VL
V
+1
5
10
µA
SHUTDOWN CONTROL
EN Logic-Level Low
3V ≤ VVL ≤ 5.5V
EN Logic-Level High
3V ≤ VVL ≤ 5.5V
2
VEN = 0 or 5.5V
-1
EN Input Current
0.45
VEN = 13.2V
V
V
+4
1.5
6
µA
ELECTRICAL CHARACTERISTICS
(VIN = 13.2V, VBST - VLX = 5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
MAX
UNITS
3.0
13.2
V
VFB = 0.9V, no switching
3
mA
EN = GND, MODE = GND, IN not connected to VL
10
EN = GND, VL = IN, MODE = GND
20
Operating Input Voltage Range
VL connected to IN for VIN < 5.5V
Quiescent Supply Current
Shutdown Supply Current
VL Undervoltage-Lockout Trip Level
VVL rising, typical hysteresis is 80mV
2.52
Output Voltage Adjust Range (VOUT)
(Note 1)
0.8
VL Output Voltage
5.5V < VIN < 13.2V, 1mA < IVL < 75mA
4.5
2.88
µA
V
V
5.5
V
75
mA
100
Ω
14
34
µA
0.788
0.808
V
70
160
µS
100
Ω
100
nA
+0.9
V
VL Output Current
VOLTAGE REFERENCE
SS Shutdown Resistance
From SS to GND, VEN = 0V
SS Soft-Start Current
VREF = 0.625V
ERROR AMPLIFIER
FB Regulation Voltage
Transconductance
COMP Shutdown Resistance
From COMP to GND, VEN = 0V
FB Input Leakage Current
VFB = 0.9V
FB Input Common-Mode Range
4
-0.1
_______________________________________________________________________________________
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
MAX8543/MAX8544
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 13.2V, VBST - VLX = 5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
MAX
UNITS
VILIM1 = 0V
8.8
13.2
VILIM1 = (1/3)VVL
4.8
7.2
VILIM1 = (2/3)VVL
3.2
4.8
VILIM1 = VVL
2.4
3.6
4.2
5.5
µA
µA
CURRENT-SENSE AMPLIFIER
Voltage Gain
VOUT = 0 to 13V
V/V
CURRENT LIMIT
ILIM2 Output Current (MAX8544 Only)
RILIM2 = 50kΩ to 200kΩ
ILIM1 Input Current
VILIM1 = 0V or VVL
-1
+1
38.5
56.5
VCS+ - VCS-, VILIM1 = (1/3)VVL
85
115
VCS+ - VCS-, VILIM1 = (2/3)VVL
VCS+ - VCS-, VILIM1 = 0V
Current-Limit Threshold
127.5
172.5
VCS+ - VCS-, VILIM1 = VVL
170
230
VLX - VPGND, RILIM2 = 50kΩ (MAX8544 only)
-40
-60
VLX - VPGND, RILIM2 = 200kΩ (MAX8544 only)
-160
-240
VLX - VPGND, VFB = 0.8V (MAX8543 only)
-110
-150
-40
mV
VLX - VPGND, VFB = 0V (MAX8543 only)
-20
Negative Current-Limit Threshold
% of positive-direction current limit VLX - VPGND
-25
-85
%
CS+, CS- Input Current
VCS+ = VCS- = 0V or 5V
-40
+40
µA
0
13.2
V
CS+, CS- Input Common-Mode Range
OSCILLATOR
Switching Frequency
RFSYNC = 18.2kΩ
800
1200
kHz
Minimum Off-Time
Measured at DH
150
270
ns
Minimum On-Time
Measured at DH
FSYNC Synchronization Range
160
FSYNC Input High Pulse Width
100
FSYNC Input Low Pulse Width
100
FSYNC Rise/Fall Time
SYNCO Phase Shift from DH Rising
RFSYNC = 18.2kΩ
SYNCO Output Low Level
ISYNCO = 5mA
SYNCO Output High Level
ISYNCO = 5mA
165
140
ns
1200
kHz
ns
ns
100
ns
195
Degrees
0.4
V
VVL - 1V
V
MOSFET DRIVERS
DH On-Resistance, High State
(VBST - VLX) = 5V
2.5
Ω
DH On-Resistance, Low State
(VBST - VLX) = 5V
2.5
Ω
DL On-Resistance, High State
VVL = 5V
2.5
Ω
DL On-Resistance, Low State
VVL = 5V
1.7
Ω
LX, BST, IN Leakage Current
VBST = 18.7V, VLX = 13.2V, VIN = 13.2V
5
µA
_______________________________________________________________________________________
5
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 13.2V, VBST - VLX = 5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
MAX
UNITS
88
94
%
200
mV
1
µA
+120
%
0.4
V
POK
Power-OK Threshold
VFB rising, percent of VOUT,
typical hysteresis is 3%
POK Output Voltage, Low
VFB = 0.6V, IPOK = 2mA
POK Leakage Current, High
VPOK = 5.5V
OVERVOLTAGE PROTECTION (OVP)
Output Overvoltage Fault-Trip level
Rising edge compared to regulation set point;
triggers after one or two clock cycles
+110
MODE CONTROL
MODE Logic-Level Low
3V ≤ VVL ≤ 5.5V
MODE Logic-Level High
3V ≤ VVL ≤ 5.5V
1.8
VMODE = 0V
-1
MODE Input Current
MODE = VL
V
+1
10
µA
SHUTDOWN CONTROL
EN Logic-Level Low
3V ≤ VVL ≤ 5.5V
EN Logic-Level High
3V ≤ VVL ≤ 5.5V
2
VEN = 0V or 5.5V
-1
EN Input Current
0.45
VEN = 13.2V
Note 1: Maximum output voltage is limited by maximum duty cycle and external components.
Note 2: Specifications to -40°C are guaranteed by design and not production tested.
6
_______________________________________________________________________________________
V
V
+4
6
µA
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
EFFICIENCY vs. LOAD CURRENT
WITH 3.3V INPUT
VOUT = 2.5V
60
50
40
VOUT = 1.8V
50
20
10
10
1
2.51
2.50
2.49
2.48
2.46
fS = 500kHz
0.1
1
2.45
0
100
10
3
6
9
12
LOAD CURRENT (A)
LOAD CURRENT (A)
LINE REGULATION WITH 12V INPUT
AND 2.5V OUTPUT
LINE REGULATION
3.0V TO 3.6V INPUT
OSCILLATOR FREQUENCY
vs. INPUT VOLTAGE
NO LOAD
2.502
2.500
15A LOAD
2.496
2.494
NO LOAD
2.50
15A LOAD
fS = 350kHz
2.48
15A LOAD
fS = 500kHz
2.46
2.44
2.492
MAX8543 toc06
2.52
OUTPUT VOLTAGE (V)
2.506
580
560
TA = +85°C
540
520
500
TA = +25°C
480
TA = -40°C
460
440
420
2.490
2.42
12.0
12.6
13.2
R6 = 53.6kΩ
400
3.0
3.1
3.2
INPUT VOLTAGE (V)
3.3
3.4
3.5
3.6
INPUT VOLTAGE (V)
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
OSCILLATOR FREQUENCY
vs. INPUT VOLTAGE
700
MAX8543 toc07
11.4
680
OSCILLATOR FREQUENCY (kHz)
10.8
15
600
OSCILLATOR FREQUENCY (kHz)
2.54
MAX8543 toc04
2.508
2.498
2.52
LOAD CURRENT (A)
2.510
2.504
2.53
2.47
0
100
10
VOUT = 1.5V
40
20
0.1
VOUT = 1.8V
60
30
fS = 600kHz
VOUT = 2.5V
70
30
0
OUTPUT VOLTAGE (V)
80
2.54
OUTPUT VOLTAGE (V)
70
90
EFFICIENCY (%)
EFFICIENCY (%)
80
2.55
MAX8543 toc02
VOUT = 3.3V
MAX8543 toc05
90
LOAD REGULATION WITH 12V INPUT
100
MAX8543 toc01
100
MAX8543 toc03
EFFICIENCY vs. LOAD CURRENT
WITH 12V INPUT
660
640
TA = +85°C
620
600
580
560
TA = +25°C
TA = -40°C
540
520
R6 = 42.2kΩ
500
5.5
7.5
9.5
11.5
13.5
INPUT VOLTAGE (V)
_______________________________________________________________________________________
7
MAX8543/MAX8544
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX8544 STEP-LOAD RESPONSE
7.5A TO 15A TO 7.5A (5A/μs)
MAX8544 STEP-LOAD RESPONSE
1.5A TO 15A TO 1.5A (5A/μs)
MAX8543 toc08
MAX8543 toc09
50mV/div
AC-COUPLED
VOUT
IOUT
5A/div
100mV/div
AC-COUPLED
VOUT
IOUT
5A/div
0
0
10μs/div
10μs/div
MAX8544 POWER-UP WAVEFORMS
MAX8544 POWER-DOWN WAVEFORMS
MAX8543 toc10
MAX8543 toc11
VIN
VIN
5V/div
5V/div
VOUT
VOUT
2V/div
VPOK
VPOK
2V/div
5V/div
2V/div
IL
10A/div
IL
10A/div
0
0
2ms/div
2ms/div
MAX8543 POWER-DOWN WAVEFORMS
MAX8543 POWER-UP WAVEFORMS
MAX8543 toc13
MAX8543 toc12
2V/div
VIN
VIN
2V/div
1V/div
VOUT
VOUT
1V/div
10A/div
10A/div
IL
IL
2ms/div
8
0
0
2ms/div
_______________________________________________________________________________________
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
MAX8544 ENABLE WAVEFORMS
FSYNC AND SYNCO WAVEFORMS
MAX8543 toc14
MAX8543 toc15
VOUT
1V/div
VEN
5V/div
VLX
10V/div
VOUT
2V/div
VPOK
VFSYNC
5V/div
VSYNCO
5V/div
5V/div
10A/div
IL
0
2μs/div
2ms/div
OVERVOLTAGE PROTECTION
WITH 15A LOAD
SHORT CIRCUIT AND RECOVERY
MAX8543 toc17
MAX8543 toc16
VIN
10V/div
12V
VOUT
1V/div
5V
1V/div
VOUT
0V
VDH
10V/div
0V
5V
10A/div
IL
0
10A/div
IIN
VDL
5V/div
0
40μs/div
1ms/div
PREBIASED STARTUP
(OUTPUT PREBIASED AT 1.5V)
MAX8543 toc18
5V/div
VIN
2.5V
VOUT
500mV/div
1.5V
VLX
10V/div
VDL
5V/div
1ms/div
_______________________________________________________________________________________
9
MAX8543/MAX8544
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
BODE PLOT, 600kHz, 15A LOAD
BODE PLOT, 600kHz, NO LOAD
MAX8543 toc19
MAX8543 toc20
SWEEP TIME
10.000s
0dB
SWEEP TIME
10.000s
90°
30°/div
0dB
90°
30°/div
10dB/div
10dB/div
1kHz
10kHz
100kHz
1MHz
1kHz
10kHz
100kHz
1MHz
Pin Description
PIN
NAME
FUNCTION
MAX8543
MAX8544
1
2
GND
2
3
SS
3
4
COMP
Compensation. Connect to an external RC network to compensate the feedback loop.
See the Compensation Design section. COMP is internally pulled to GND in shutdown.
4
5
FB
Output Feedback. Connect to the center of a voltage-divider connected between OUT
and GND to set the output voltage. The FB threshold voltage is 0.8V.
5
6
EN
Enable. Drive EN logic high to enable the output, or drive logic low for shutdown.
Connect EN to IN for always-on operation.
6
7
CS-
Negative Differential Current-Sensing Input
10
Ground. Connect to the analog ground plane.
Soft-Start. Connect a 0.1µF to 1µF ceramic capacitor from SS to GND. This capacitor
sets the soft-start period during startup. See the Startup and Soft-Start section. SS is
internally pulled to GND in shutdown.
7
8
CS+
Positive Differential Current-Sensing Input
—
9
ILIM1
8
—
ILIM
Digital Programmable Current-Limit Input for Inductor Current Sensing (VCS+ - VCS-).
See Table 3.
9
12
PGND
10
13
DL
Low-Side MOSFET Gate-Driver Output. Connect to the gate of the low-side external
MOSFETs. DL is pulled low in shutdown.
11
14
VL
Internal 5V Linear-Regulator Output. Connect a 1µF to 10µF ceramic capacitor from
VL to PGND. Connect VL to IN for VIN less than 5.5V. VL provides power for bias and
gate drive.
12
15
IN
Input Supply Voltage. IN is the input to the internal linear regulator. Connect VL to IN for
VIN less than 5.5V.
Power Ground. Connect to the power ground plane and to the source of the low-side
external MOSFETs. Connect PGND to GND at a single point.
______________________________________________________________________________________
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
PIN
NAME
FUNCTION
MAX8543
MAX8544
13
16
LX
Inductor Connection
14
17
DH
High-Side MOSFET Gate-Driver Output. Connect DH to the gate of the high-side
external MOSFETs. DH is pulled low in shutdown.
15
18
BST
Boost Capacitor Connection. Connect a 0.1µF or larger ceramic capacitor from BST to
LX. BST provides power for the high-side MOSFET gate drive.
16
19
FSYNC
Frequency Set and Synchronization. Connect a resistor from FSYNC to GND to set the
switching frequency or drive with a clock signal to synchronize between 160kHz and
1.2MHz. See the Switching Frequency and Synchronization section.
—
1
ILIM2
Analog Programmable Current-Limit Input for Low-Side MOSFET (VLX - VPGND).
Connect a resistor from ILIM2 to ground to set the overcurrent threshold. See the
Setting the Current Limits section.
—
10
MODE
Current-Limit Operating-Mode Selection. Connect MODE to VL for latch-off current limit
or connect to GND for automatic-recovery current limit with the MAX8544. The MAX8543
always uses automatic-recovery current limit.
—
11
POK
—
20
SYNCO
Power-OK. POK is an open-drain output that is high impedance when the output is
above 91% of its nominal regulation voltage. POK is pulled low when the output is out
of regulation and when the part is in shutdown. To use POK as a logic-level signal,
connect a pullup resistor from POK to the logic supply.
Synchronization Output. Provides a clock output that is 180° out of phase with the rising
edge of DH for out-of-phase synchronization of another MAX8544.
______________________________________________________________________________________
11
MAX8543/MAX8544
Pin Description (continued)
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
VIN = (10.8V TO 13.2V)
VL
C12
9
SYNC IN
C1
ILIM1
IN
D2
R6
19
ON
OFF
6
D1
FSYNC
BST
EN
DH
2
18
17
N1
C4A
N2
MAX8544EEP
SS
C7
LX
VL
DL
R3
4
14
5
10
R8
1
VL
VOUT = 2.5V
UP TO 15A
L1
16
VL
13
N3
C6A
R4
N4
C6B
C9
COMP
PGND
R2
C4C
C3
C2
C8
C4B
GND
C5
3
15
12
R5
FB
CS+
MODE
ILIM2
CSSYNCO
C10
8
7
20
C11
SYNC OUT
R1
R9
11
POK
POK
R7
Figure 1. Typical Applications Circuit with 12V (±10%) Input, 2.5V Output at Up to 15A, and 600kHz Switching Frequency
12
______________________________________________________________________________________
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
MAX8543/MAX8544
Table 1. Suggested Components for Figure 1
DESIGNATION
QTY
DESCRIPTION
C1
1
1µF ±20%, 16V X5R ceramic capacitor (0603)
Panasonic ECJ1VB1C105M or equivalent
C2
1
10µF ±20%, 6.3V X5R ceramic capacitor (0805)
Panasonic ECJ2FB0J106M or Taiyo Yuden JMK212BJ106MG
C3
1
0.1µF ±10%, 50V X7R ceramic capacitor (0603)
TDK C1608X7R1H104KT or equivalent
C4A, C4B, C4C
2
10µF ±20%, 16V X5R ceramic capacitors (1206)
Panasonic ECJ3YB1C106M or equivalent
C5
1
0.22µF ±10%, 10V X7R ceramic capacitor (0603)
Taiyo Yuden LMK107BJ224KA or equivalent
C6A, C6B
2
180µF, 4V aluminum poly SPCAPs
Panasonic EEFUE0G181XR
C7
1
10pF, 50V C0G ceramic capacitor (0603)
C8
1
220pF ±10%, 50V X7R ceramic capacitor (0603)
C9, C10
2
0.47µF ±10% X7R ceramic capacitors (0603)
C11
1
100pF, 50V C0G ceramic capacitor (0603)
C12
1
470µF ±20%, 16V aluminum electrolytic capacitor
Rubycon 16MBZ470M
D1
1
100mA, 30V Schottky diode (SOT-323)
Central CMSSH-3
D2
1
250mA, 100V switching diode (SOT23)
Central CMPD914
L1
1
0.82µH, 33A, 1.6mΩ inductor
Vishay IHLP-5050FD-01 0.82µH
N1, N2
2
N-channel MOSFETs
IRF IRF7821
N3, N4
2
N-channel MOSFETs
IRF IRF7832
R1
1
17.4kΩ ±1% resistor (0603)
R2
1
8.06kΩ ±1% resistor (0603)
220kΩ ±5% resistor (0603)
R3
1
R4, R5
2
1.3kΩ ±5% resistors (0603)
R6
1
42.2kΩ ±1% resistor (0603)
R7
1
90.9kΩ ±1% resistor (0603)
R8
1
9.31kΩ ±1% resistor (0603)
R9
1
100kΩ ±5% resistor (0603)
______________________________________________________________________________________
13
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
VIN = (3V TO 3.6V)
C12
8
SYNC IN
C1
ILIM
IN
D2
R6
16
ON
OFF
5
1
12
D1
FSYNC
BST
EN
MAX8543
DH
15
14
N1
C4A
N2
SS
LX
11
VL
DL
3
IN
4
FB
CS+
6
10
N3
C6A
R4
N4
C6B
C9
COMP
PGND
R2
VOUT = 2.5V
UP TO 15A
L1
C2
R3
C4D
C3
13
C7
C8
C4C
GND
C5
2
C4B
9
7
CSC11
C10
R1
R5
Figure 2. Typical Applications Circuit with 3.3V (±10%) Input, 2.5V Output at Up to 15A, and 500kHz Switching Frequency
14
______________________________________________________________________________________
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
MAX8543/MAX8544
Table 2. Suggested Components for Figure 2
DESIGNATION
QTY
DESCRIPTION
C1
1
1µF ±10%, 16V X5R ceramic capacitor (0603)
Panasonic ECJ1VB1C105K or equivalent
C2
1
10µF ±20%, 6.3V X5R ceramic capacitor (0805)
Panasonic ECJ2FB0J106M or Taiyo Yuden JMK212BJ106MG
C3
1
0.1µF ±10%, 50V X7R ceramic capacitor (0603)
TDK C1608X7R1H104KT or equivalent
C4A, C4B, C4C,
C4D
4
10µF ±20%, 16V X5R ceramic capacitors (1206)
Panasonic ECJ3YB1C106M or equivalent
C5
1
0.22µF ±10%, 10V X7R ceramic capacitor (0603)
Taiyo Yuden LMK107BJ224KA or equivalent
C6A, C6B
2
180µF, 4V, 10mΩ aluminum poly SPCAPs
Panasonic EEFUE0G181XR
C7
1
12pF, 50V C0G ceramic capacitor (0603)
C8
1
220pF ±10%, 50V X7R ceramic capacitor (0603)
C9, C10
2
0.47µF ±10% X7R ceramic capacitors (0603)
C11
1
100pF, 50V C0G ceramic capacitor (0603)
C12
1
470µF ±20%, 6.3V POSCAP
Sanyo 6PB470M
D1
1
100mA, 30V Schottky diode (SOT-323)
Central CMSSH-3
D2
1
250mA, 100V switching diode (SOT23)
Central CMPD914
L1
1
0.33µH, 16A, 2mΩ inductor (13 x 10 x 6.35)
Coilcraft DO3316P-331HC
N1, N2
2
N-channel MOSFETs
Vishay Si4866DY
N3, N4
2
N-channel MOSFETs
Vishay Si4866DY
R1
1
17.4kΩ ±1% resistor (0603)
R2
1
8.06kΩ ±1% resistor (0603)
R3
1
150kΩ ±5% resistor (0603)
R4, R5
2
680Ω ±5% resistors (0603)
R6
1
53.6kΩ ±1% resistor (0603)
______________________________________________________________________________________
15
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
Detailed Description
DC-DC Converter Control Architecture
The MAX8543/MAX8544 step-down controllers use a
PWM, current-mode control scheme. An internal
transconductance amplifier establishes an integrated
error voltage. The heart of the PWM controller is an
open-loop comparator that compares the integrated
voltage-feedback signal against the amplified currentsense signal plus the slope-compensation ramp, which
are summed into the main PWM comparator to preserve inner-loop stability and eliminate inductor staircasing. At each rising edge of the internal clock, the
high-side MOSFET turns on until the PWM comparator
trips or the maximum duty cycle is reached or the peak
current limit is reached. During this on-time, current
ramps up through the inductor, storing energy in a
magnetic field and sourcing current to the output. The
current-mode feedback system regulates the peak
inductor current as a function of the output-voltageerror signal. The circuit acts as a switch-mode
transconductance amplifier and pushes the output LC
filter pole normally found in a voltage-mode PWM to a
higher frequency.
During the second half of the cycle, the high-side
MOSFET turns off and the low-side MOSFET turns on.
The inductor releases the stored energy as the current
ramps down, providing current to the output. The output capacitor stores charge when the inductor current
exceeds the required load current and discharges
when the inductor current is lower, smoothing the voltage across the load. Under soft-overload conditions,
when the peak inductor current exceeds the selected
current limit (see the Current-Limit Circuit section), the
high-side MOSFET is turned off immediately and the
low-side MOSFET is turned on and remains on to let the
inductor current ramp down until the next clock cycle.
Under heavy-overload or short-circuit conditions, the
valley foldback current limit is enabled to reduce power
dissipation of external components.
The MAX8543/MAX8544 operate in a forced-PWM
mode. As a result, the controller maintains a constant
switching frequency, regardless of load, to allow for
easier filtering of the switching noise.
Internal 5V Linear Regulator (VL)
All MAX8543/MAX8544 functions are powered from the
on-chip, low-dropout, 5V linear regulator. Connect a
1µF to 10µF ceramic capacitor from VL to PGND. In
applications where the input voltage is less than 5.5V,
bypass the linear regulator by connecting VL to IN.
16
Undervoltage Lockout
When VL drops below 2.62V, the MAX8543/MAX8544
assume that the supply voltage is too low for proper operation, so the undervoltage-lockout (UVLO) circuitry
inhibits switching and forces the DL and DH gate drivers
low. When VL rises above 2.7V, the controller enters the
startup sequence and then resumes normal operation.
Startup and Soft-Start
The soft-start circuitry gradually ramps up the reference
voltage to control the rate of rise of the step-down controller output and reduce input surge currents during
startup. The soft-start period is determined by the value
of the capacitor from SS to GND. The soft-start time is
approximately (33ms/µF) x CSS. The MAX8543/MAX8544
also feature prebias startup; therefore, both external
power MOSFETs are kept off if the voltage at FB is higher
than that at SS. This allows the MAX8543/MAX8544 to
start up into a prebiased output without pulling the output
voltage down.
Before the MAX8543/MAX8544 can begin the soft-start
and power-up sequence, the following conditions must
be met:
1) VVL exceeds the 2.7V undervoltage-lockout threshold.
2) EN is at logic high.
3) The thermal limit is not exceeded.
Enable
The MAX8543/MAX8544 feature a low-power shutdown
mode. A logic low at EN shuts down the controller.
During shutdown, the output is high impedance, and
both DH and DL are low. Shutdown reduces the quiescent current (IQ) to less than 10µA. A logic high at EN
enables the controller.
Synchronous-Rectifier Driver (DL)
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal Schottky catch
diode with a low-resistance MOSFET switch. The
MAX8543/MAX8544 also use the synchronous rectifier
to ensure proper startup of the boost gate-driver circuit
and to provide the current-limit signal. The DL low-side
gate-drive waveform is always the complement of the
DH high-side gate-drive waveform (with controlled
dead time to prevent cross-conduction or shootthrough). An adaptive dead-time circuit monitors the DL
voltage and prevents the high-side MOSFET from turning on until DL is fully off. For the dead-time circuit to
work properly, there must be a low-resistance, lowinductance path from the DL driver to the MOSFET
gate. Otherwise, the sense circuitry in the MAX8543/
MAX8544 can interpret the MOSFET gate as off when
gate charge actually remains.
______________________________________________________________________________________
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
High-Side Gate-Drive Supply (BST)
A flying capacitor boost circuit (Figure 3) generates the
gate-drive voltage for the high-side n-channel MOSFET.
The capacitor between BST and LX is charged from VL
up to VVL minus the diode forward-voltage drop while the
low-side MOSFET is on. When the low-side MOSFET is
switched off, the stored voltage of the capacitor is
stacked above LX to provide the necessary turn-on
voltage (VGS) for the high-side MOSFET. The controller
then closes an internal switch between BST and DH to
turn the high-side MOSFET on.
Current-Sense Amplifier
The MAX8543/MAX8544 current-sense circuit amplifies
the differential current-sense voltage (VCS+ - VCS-). The
gain of the current-sense amplifier is determined by the
states of ILIM and ILIM1. This amplified current-sense
signal and the internal slope-compensation signal are
summed (VSUM) together and fed into the PWM comparator’s inverting input. The PWM comparator shuts
off the high-side MOSFET when V SUM exceeds the
integrated feedback voltage (VCOMP).
The differential current sense is also used to provide
peak inductor current limiting. This current limit is more
accurate than the valley current limit, which is measured
across the low-side MOSFET’s on-resistance.
IN
BST
DH
MAX8543/
MAX8544
N
LX
DL
N
Figure 3. The boost circuit provides voltage for the high-side
MOSFET gate drive.
Current-Limit Circuit
The MAX8543/MAX8544 use both valley foldback current
limiting and peak constant current limiting, simultaneously
(Figure 4). The valley foldback current limit is used to
reduce power dissipation of external components, mainly
inductor and power MOSFETs, and upstream power
source, when output is severely overloaded or short
circuited. Thus the circuit can withstand short-circuit
conditions indefinitely without causing overheating of any
component. The peak constant current limit sets the current-limit point more accurately since it does not have to
suffer the wide variation of the low-side power MOSFET’s
on-resistance due to tolerance and temperature.
The valley current is sensed across the on-resistance of
the low-side MOSFET (VPGND - VLX). The valley current
limit trips when the sensed current exceeds the valley
current-limit threshold. The valley current limit recovers
when the sensed current drops below the valley currentlimit threshold (except when using the latch-off option
with the MAX8544).
Set the minimum valley current-limit threshold, when the
output voltage is at a nominal regulated value, higher
than the maximum peak current-limit setting. With this
method, the current-limit point accuracy is controlled by
the peak current limit and is not interfered with by the
wide variation of MOSFET on-resistance. See the Setting
the Current Limits section for how to set these limits.
The MAX8543 has a fixed valley current-limit threshold
and fixed foldback ratio. The MAX8544 can select
between an adjustable valley current-limit threshold
with adjustable foldback ratio and a fixed valley current
limit without foldback for latch-off. When latch-off is
used (MODE is connected to VL), set the current-limit
threshold by only one resistor from ILIM2 to GND and
make sure this threshold is higher than the maximum
output current required by at least a 20% margin. Cycle
EN or input power to reset the current-limit latch.
The peak current limit is used to sense the inductor
current, and is more accurate than the valley current limit
since it does not depend upon the on-resistance of the
low-side MOSFET. The peak current can be measured
across the resistance of the inductor for the highest
efficiency, or alternatively, a current-sense resistor can
be used for more accurate current sensing. The
MAX8543/MAX8544 have four selectable peak currentlimit thresholds that are selected using ILIM (MAX8543)
or ILIM1 (MAX8544). See Table 3 for the current-limit
settings.
For more information on the current limit, see the
Setting the Current Limits section.
______________________________________________________________________________________
17
MAX8543/MAX8544
Use very short, wide traces, about 10 to 20 squares
(50 mils to 100 mils wide if the MOSFET is 1in from the
device) for the gate drive. The dead time at the other
edge (DH turning off) also has an adaptive dead-time
circuit operating in a similar manner. For both edges,
there is an additional fixed dead time after the adaptive
dead time expires.
IPEAK
ILOAD
INDUCTOR CURRENT
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
MAX8543/
MAX8544
LX
R1
IVALLEY
FB
R2
TIME
Figure 4. Inductor-Current Waveform
Switching Frequency and
Synchronization
The MAX8543/MAX8544 have an adjustable internal
oscillator that can be set to any frequency from 200kHz
to 1MHz. To set the switching frequency, connect a
resistor from FSYNC to GND. Calculate the resistor
value from the following equation:
⎛ 1
⎞ ⎛ 1kΩ ⎞
RFSYNC = ⎜
− 240ns⎟ ⎜
⎟
⎝ 2fS
⎠ ⎝ 14.18ns ⎠
The MAX8543/MAX8544 can also be synchronized to an
external clock by connecting the clock signal to FSYNC.
When using an external clock, select RFSYNC such that
the free-running frequency is within ±30% of the clock frequency. In addition, the MAX8544 has a synchronization
output (SYNCO) that provides a clock signal that is 180°
out-of-phase with the MAX8544 switching. SYNCO is
used to synchronize a second controller 180° out-ofphase with the first by connecting SYNCO of the first controller to FSYNC of the second when the first controller
operates in free-running mode. When the first controller is
synchronized to an external clock, the external clock is
inverted to generate SYNCO.
Power-Good Signal (POK)
POK is an open-drain output on the MAX8544 that monitors the output voltage. When the output is above 91% of
its nominal regulation voltage, POK is high impedance.
When the output drops below 91% of its nominal regulation voltage, POK is pulled low. POK is also pulled low
when the MAX8544 is shut down. To use POK as a logiclevel signal, connect a pullup resistor from POK to the
logic-supply rail.
18
Figure 5. Setting the Output Voltage with a Resistor VoltageDivider
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation
in the MAX8543/MAX8544. When the junction temperature exceeds TJ = +160°C, an internal thermal sensor
shuts down the device, allowing the IC to cool. The thermal sensor turns the IC on again after the junction temperature cools by 15°C, resulting in a pulsed output
during continuous thermal-overload conditions.
Design Procedure
Setting the Output Voltage
To set the output voltage for the MAX8543/MAX8544,
connect FB to the center of an external resistor-divider
from the output to GND (Figure 5). Select R2 between
8kΩ and 24kΩ; then calculate R1 with the following
equation:
⎛V
⎞
R1 = R2 × ⎜ OUT − 1⎟
⎝ VFB
⎠
where VFB = 0.8V. R1 and R2 should be placed as
close to the IC as possible.
Inductor Selection
There are several parameters that must be examined
when determining which inductor is to be used: input voltage, output voltage, load current, switching frequency,
and LIR. LIR is the ratio of peak-to peak inductor current
ripple to maximum DC load current. A higher LIR value
allows for a smaller inductor, but results in higher losses
and higher output ripple.
______________________________________________________________________________________
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
L=
Ensure that ILIM is equal to or greater than the maximum load current at peak current limit (see the Peak
Current Limit section):
VOUT × (VIN − VOUT )
VIN × fS × ILOAD(MAX) × LIR
where fS is the switching frequency. Choose a standardvalue inductor close to the calculated value. The exact
inductor value is not critical and can be adjusted to
make trade-offs among size, cost, and efficiency. Lower
inductor values minimize size and cost, but they also
increase the output ripple and reduce the efficiency due
to higher peak currents. On the other hand, higher inductor values increase efficiency, but eventually resistive
losses due to extra turns of wire exceed the benefit
gained from lower AC current levels. This is especially
true if the inductance is increased without also increasing the physical size of the inductor. Find a low-loss
inductor with the lowest possible DC resistance that fits
the allotted dimensions. Ferrite cores are often the best
choice, although powdered iron is inexpensive and can
work well at 300kHz. The chosen inductor’s saturation
current rating must exceed the peak inductor current
determined as:
ISC =
I
0.04 V
+ P −P
2
RDS(ON)
where 40mV is the maximum current-limit threshold
when the output is shorted (VOUT = 0V).
The MAX8544 has an adjustable valley current limit and
can be selected for foldback with automatic recovery,
or constant current with latch-up. To set the current limit
for foldback mode, connect a resistor from ILIM2 to the
output (R FOBK ), and another resistor from ILIM2 to
GND (RILIM). See Figure 6. The values of RFOBK and
RILIM are calculated as follows:
1) First, select the percentage of foldback (PFB). This
percentage corresponds to the current limit when
VOUT equals zero, divided by the current limit when
VOUT equals a nominal voltage. A typical value of
PFB is in the range of 15% to 40%. A lower value of
PFB yields lower short-circuit current. The following
equations are used to calculate RFOBK and RILIM:
RFOBK =
IPEAK = ILOAD(MAX) +
LIR
× ILOAD(MAX)
2
Setting the Current Limits
Valley Current Limit
The valley current limit employs a current foldback
scheme. The MAX8543 has a fixed valley current-limit
threshold of 130mV, and a fixed foldback ratio (PFB) of
23%. The foldback ratio is the current-limit threshold
when the output is at 0V (output shorted to ground),
divided by the threshold when the output is at its nominal
regulated value. Thus, the minimum output current limit
(ILIM) and maximum short-circuit current (ISC) is calculated as:
ILIM =
I
0.11V
+ P −P
2
RDS(ON)
where RDS(ON) is the maximum on-resistance of the
low-side MOSFET at the highest expected operating
junction temperature, and IP-P is the inductor ripple current, calculated as:
IP − P
RILIM =
PFB × VOUT
5μA × (1 − PFB )
5 × RDS(ON) × IVALLEY × (1 − PFB ) × RFOBK
[
]
VOUT − 5 × RDS(ON) × IVALLEY × (1 − PFB )
where IVALLEY is the value of the inductor valley
current at maximum load (ILOAD(MAX) - 1/2 IP-P),
and RDS(ON) is the maximum on-resistance of the
low-side MOSFET at the highest operating junction
temperature.
MAX8544
LX
OUT
RFOBK
ILIM2
RILIM
(VIN − VOUT ) × VOUT
=
fS × L × VIN
Figure 6. ILIM2 Resistor Connections
______________________________________________________________________________________
19
MAX8543/MAX8544
A good compromise between size and efficiency is an
LIR of 0.3. Once all the parameters are chosen, the
inductor value is determined as follows:
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
2) If the resulting value of R ILIM is negative, either
increase PFB or choose a low-side MOSFET with a
lower RDS(ON). The latter is preferred as it increases the efficiency and results in a lower short-circuit
current.
To set the constant current limit for the latch-up mode,
only RILIM is used. The equation for RILIM below sets
the current-limit threshold at 1.2 times the maximumrated output current:
RILIM =
1.2 × IVALLEY × RDS(ON)
1μA
Similarly, I VALLEY is the value of the inductor valley
current at maximum load, RDS(ON) is the maximum onresistance of the low-side MOSFET at the highest operating junction temperature.
To use the DC resistance of the output inductor for current sensing, an RC circuit is added (see Figure 7). The
RC time constant is set to be twice the inductor (L / RDC)
time constant. Pick the value of R4 in the range of 470Ω
to 2kΩ, and then calculate the capacitor value from: C9
= 2L / (RDC × R4). Add a resistor (R5) equal in value to
R4 to the CS- connection to minimize input-offset error.
The equivalent current-sense resistance is equal to the
DC resistance of the inductor (RDC).
To use a current-sense resistor, connect the resistor as
shown in Figure 8. Since most current-sense resistors
have inductance, the RC circuit is also required
and is calculated in the same manner as inductor
current sensing. Place C11 close to CS+ and CS- pins
to decouple the high-frequency noise pickup. Place
C10 (same value as C9) across R5 to aid in shortcircuit recovery.
Peak Current Limit
Peak inductor current-limit threshold (VTH) has four
possible settings through ILIM (MAX8543) or ILIM1
(MAX8544) as shown in Table 3 below. The resulting
current limit is calculated as:
ILIM =
VTH IP − P
−
RDC
2
L1
R4
MAX8543/
MAX8544
where RDC is either the DC resistance of the inductor or
the value of the optional current-sense resistor.
Note that VILIM is a logic-level setting, and can allow a
variation of ±0.1 x VVL without affecting VTH. To ensure
maximum output current, use the minimum value of VTH
from each setting, and the maximum RDC values at the
highest expected operating temperature. The DC resistance of the inductor’s copper wire has a +0.22%/°C
temperature coefficient.
VOUT
LX
C9
C10
R5
CS+
C11
CS-
Figure 7. Inductor RDC Current Sensing
Table 3. ILIM Current-Limit Threshold
Settings
RECOMMENDED
ILIM CONNECTION
VILIM
0
GND
Voltage-divider:
1/3 VVL 100kΩ from ILIM/ILIM1 to GND
200kΩ from ILIM/ILIM1 to VL
Voltage-divider:
2/3 VVL 200kΩ from ILIM/ILIM1 to GND
100kΩ from ILIM/ILIM1 to VL
VVL
20
VL
VTH
MIN
(mV)
VTH
TYP
(mV)
VTH
MAX
(mV)
38.5
50
56.5
85.0
100
115.0
L1
R3
R4
MAX8543/
MAX8544
C9
R5
CS+
C11
CS-
127.5
150
172.5
170.0
200
230.0
VOUT
LX
Figure 8. Using a Current-Sense Resistor
______________________________________________________________________________________
C10
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
For proper thermal-management design, the power dissipation must be calculated at the desired maximum
operating junction temperature, maximum output current,
and worst-case input voltage (for the low-side MOSFET,
worst case is at VIN(MAX); for the high-side MOSFET, it
could be either at VIN(MAX) or VIN(MIN)). The high-side
and low-side MOSFETs have different loss components
due to the circuit operation. The low-side MOSFET operates as a zero-voltage switch; therefore, major losses
are the channel-conduction loss (PLSCC) and the bodydiode conduction loss (PLSDC):
⎛
⎞
V
PLSCC = ⎜1 − OUT ⎟ × I2LOAD × RDS(ON)
V
⎝
IN ⎠
Use RDS(ON) at TJ(MAX):
PLSDC = 2 × ILOAD × VF × t DT × fS
The high-side MOSFET operates as a duty-cycle control
switch and has the following major losses: the channelconduction loss (PHSCC), the VI overlapping switching
loss (PHSSW), and the drive loss (PHSDR). The high-side
MOSFET does not have body-diode conduction loss
because the diode never conducts current:
V
PHSCC = OUT × I2LOAD × RDS(ON)
VIN
Use RDS(ON) at TJ(MAX):
PHSSW = VIN × ILOAD ×
QGS + QGD
× fS
IGATE
where IGATE is the average DH-driver output current
capability determined by:
IGATE ≅
0.5 × VVL
RDS(ON)(HS) + RGATE
where RDS(ON)(HS) is the high-side MOSFET driver’s
on-resistance (1Ω, typ) and RGATE is the internal gate
resistance of the MOSFET (≈0.5Ω to 3Ω):
PHSDR = QG × VGS × fS ×
RGATE
RGATE + RDS(ON)(HS)
where VGS ≈ VVL.
In addition to the losses above, allow about 20% more for
additional losses due to MOSFET output capacitances
and low-side MOSFET body-diode reverse-recovery
charge dissipated in the high-side MOSFET, but it is not
well defined in the MOSFET data sheet. Refer to the
MOSFET data sheet for thermal resistance specifications
to calculate the PC board area needed to maintain the
desired maximum operating junction temperature with the
above calculated power dissipations.
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side switch drain to
the low-side switch source or add resistors in series
with DH and DL to slow down the switching transitions.
However, adding series resistors increases the power
dissipation of the MOSFET, so be sure this does not
overheat the MOSFET.
where VF is the body-diode forward-voltage drop, tDT is
the dead time between high-side and low-side switching
transitions, and fS is the switching frequency.
______________________________________________________________________________________
21
MAX8543/MAX8544
MOSFET Selection
The MAX8543/MAX8544 drive two or four external,
logic-level, n-channel MOSFETs as the circuit switch
elements. The key selection parameters are:
1) On-resistance (RDS(ON)): the lower, the better.
2) Maximum drain-to-source voltage (V DSS): should
be at least 20% higher than the input supply rail at
the high-side MOSFET’s drain.
3) Gate charges (QG, QGD, QGS): the lower, the better.
For a 3.3V input application, choose a MOSFET with a
rated RDS(ON) at VGS = 2.5V. For a 5V input application,
choose the MOSFETs with rated RDS(ON) at VGS ≤ 4.5V.
For a good compromise between efficiency and cost,
choose the high-side MOSFET (N1, N2) that has conduction losses equal to the switching loss at nominal input
voltage and output current. The selected low-side
MOSFET (N3, N4) must have an RDS(ON) that satisfies the
current-limit-setting condition above. Ensure that the lowside MOSFET does not spuriously turn on due to dV/dt
caused by the high-side MOSFET turning on as this
would result in shoot-through current and degrade the
efficiency. MOSFETs with a lower QGD / QGS ratio have
higher immunity to dV/dt. For high-current applications, it
is often preferable to parallel two MOSFETs rather than to
use a single large MOSFET.
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
MOSFET Snubber Circuit
Fast switching transitions cause ringing because of resonating circuit parasitic inductance and capacitance at
the switching nodes. This high-frequency ringing
occurs at LX’s rising and falling transitions and can
interfere with circuit performance and generate EMI. To
dampen this ringing, a series RC snubber circuit is
added across each switch. Below is the procedure for
selecting the value of the series RC circuit.
Connect a scope probe to measure VLX to GND and
observe the ringing frequency, fR.
Find the capacitor value (connected from LX to GND)
that reduces the ringing frequency by half.
The circuit parasitic capacitance (CPAR) at LX is then
equal to 1/3rd the value of the added capacitance above.
The circuit parasitic inductance (LPAR) is calculated by:
LPAR =
1
(2πfR )
2
× CPAR
The resistor for critical dampening (RSNUB) is equal to
2π x fR x LPAR. Adjust the resistor value up or down
to tailor the desired damping and the peak voltage
excursion.
The capacitor (CSNUB) should be at least 2 to 4 times the
value of the CPAR to be effective. The power loss of the
snubber circuit (PRSNUB) is dissipated in the resistor and
can be calculated as:
PRSNUB = CSNUB × ( VIN ) × fSW
2
where VIN is the input voltage and fSW is the switching
frequency. Choose an RSNUB power rating that meets
the specific application’s derating rule for the power
dissipation calculated.
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple-current
requirement (IRMS) imposed by the switching currents
defined by the following equation:
IRMS =
22
ILOAD VOUT × ( VIN − VOUT )
VIN
IRMS has a maximum value when the input voltage equals
twice the output voltage (VIN = 2 x VOUT), so IRMS(MAX) =
ILOAD / 2. Ceramic capacitors are recommended due to
their low ESR and ESL at high frequency with relatively
low cost. Choose a capacitor that exhibits less than 10°C
temperature rise at the maximum operating RMS current
for optimum long-term reliability. Ceramic capacitors with
an X5R or better temperature characteristic are recommended. When operating from a soft input source, an
additional input capacitor (bulk bypass capacitor) may
be required to prevent input from sagging.
Output Capacitor
The key selection parameters for the output capacitor
are the actual capacitance value, the equivalent series
resistance (ESR), the equivalent series inductance
(ESL), and the voltage-rating requirements. These
parameters affect the overall stability, output voltage
ripple, and transient response. The output ripple has
three components: variations in the charge stored in
the output capacitor, the voltage drop across the
capacitor’s ESR, and ESL caused by the current into
and out of the capacitor. The maximum output voltage
ripple is estimated as follows:
VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) + VRIPPLE(ESL)
The output voltage ripple as a consequence of the
ESR, ESL, and output capacitance is:
VRIPPLE(ESR) = IP − P × ESR
V
VRIPPLE(ESL) = IN × ESL
L
VRIPPLE(C) =
IP − P
8 × COUT × fS
where IP-P is the peak-to-peak inductor current:
V − VOUT VOUT
IP − P = IN
×
fS × L
VIN
These equations are suitable for initial capacitor selection, but final values should be chosen based on a prototype or evaluation circuit. As a general rule, a smaller
current ripple results in less output voltage ripple. Since
the inductor ripple current is a factor of the inductor value
and input voltage, the output voltage ripple decreases
with larger inductance, and increases with higher input
voltages. Polymer, tantalum, or aluminum electrolytic
capacitors are recommended.
______________________________________________________________________________________
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
Compensation Design
The MAX8543/MAX8544 use an internal transconductance error amplifier whose output compensates the
control loop. The external inductor, output capacitor,
compensation resistor, and compensation capacitors
determine the loop stability. The inductor and output
capacitor are chosen based on performance, size, and
cost. Additionally, the compensation resistor and capacitors are selected to optimize control-loop stability. The
component values, shown in the Typical Application
Circuits (Figures 1 and 2), yield stable operation over the
given range of input-to-output voltages.
The controller uses a current-mode control scheme that
regulates the output voltage by forcing the required current through the external inductor, so the MAX8543/
MAX8544 use the voltage drop across the DC resistance
of the inductor or the alternate series current-sense resistor to measure the inductor current. Current-mode control
eliminates the double pole in the feedback loop caused
by the inductor and output capacitor resulting in a smaller
phase shift and requiring a less elaborate error-amplifier
compensation than voltage-mode control. A simple single
series RC and CC is all that is needed to have a stable,
high-bandwidth loop in applications where ceramic
capacitors are used for output filtering. For other types of
capacitors, due to the higher capacitance and ESR, the
frequency of the zero created by the capacitance and
ESR is lower than the desired closed-loop crossover frequency. To stabilize a nonceramic output-capacitor loop,
add another compensation capacitor (CF) from COMP to
GND to cancel this ESR zero.
The basic regulator loop is modeled as a power modulator, output feedback divider, and an error amplifier.
The power modulator has DC gain set by gmc x RLOAD,
with a pole and zero pair set by R LOAD, the output
capacitor (COUT), and its ESR. Below are equations
that define the power modulator:
GMOD(dc) = gmc ×
RLOAD × fS × L
RLOAD + (fS × L)
where RLOAD = VOUT / IOUT(MAX), fS is the switching
frequency, L is the output inductance, and g mc =
1 / (AVCS × RDC), where AVCS is the gain of the current-sense amplifier and RDC is the DC resistance of
the inductor (or current-sense resistor). A VCS is
dependent on the current-limit selection at ILIM, and
ranges from 3 to 11 (see Current-Sense Amplifier
Voltage Gain in the Electrical Characteristics table).
The frequencies at which the pole and zero created by
the power modulator are determined as follows:
fpMOD =
1
⎛ RLOAD × fS × L
⎞
2π × COUT × ⎜
+ ESR⎟
⎝ RLOAD + (fS × L)
⎠
fzMOD =
1
2π × COUT × ESR
When COUT is composed of “n” identical capacitors in
parallel, the resulting COUT = n x COUT(EACH), and ESR
= ESR(EACH) / n. Note that the capacitor zero for a parallel combination of like capacitors is the same as for an
individual capacitor.
The feedback voltage-divider has a gain of GFB = VFB /
VOUT, where VFB is equal to 0.8V.
The transconductance error amplifier has a DC gain,
GEA(DC) = gmEA x RO, where gmEA is the error-amplifier
transconductance, which is equal to 110µS, RO is the
output resistance of the error amplifier, which is 10MΩ.
A dominant pole is set by the compensation capacitor
(CC), the amplifier output resistance (RO), and a zero is
set by the compensation resistor (RC) and the compensation capacitor (CC). There is an optional pole set by
CF and RC to cancel the output-capacitor ESR zero if it
occurs near the crossover frequency (fC). Thus:
fpdEA =
1
2π × CC × (RO + RC )
______________________________________________________________________________________
23
MAX8543/MAX8544
The aluminum electrolytic capacitor is the least expensive; however, it has higher ESR. To compensate for this,
use a ceramic capacitor in parallel to reduce the switching ripple and noise. For reliable and safe operation,
ensure that the capacitor’s voltage and ripple-current ratings exceed the calculated values.
The response to a load transient depends on the
selected output capacitors. After a load transient, the
output voltage instantly changes by ESR x ΔI LOAD.
Before the controller can respond, the output voltage
deviates further depending on the inductor and output
capacitor values. After a short period of time (see the
Typical Operating Characteristics), the controller
responds by regulating the output voltage back to its
nominal state. The controller response time depends on
its closed-loop bandwidth. With a higher bandwidth,
the response time is faster, thus preventing the output
voltage from further deviation from its regulation value.
MAX8543/MAX8544
Step-Down Controllers with Prebias Startup,
Lossless Sensing, Synchronization, and OVP
fzEA =
fpEA =
For the case where fzMOD is less than fC:
The power-modulator gain at fC is:
1
2π × CC × RC
GMOD( fc) = GMOD(dc) ×
1
2π × CF × RC
fzMOD
The error-amplifier gain at fC is:
The crossover frequency, fC, should be much higher
than the power-modulator pole fPMOD. Also, fC should
be less than or equal to 1/5th the switching frequency.
Select a value for fC in the range:
f
fpMOD
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