OP249GP

a Dual, Precision JFET High Speed Operational Amplifier OP249 PIN CONNECTIONS 8-Lead Cerdip (Z Suffix), 8-Lead Plastic Mini-DIP (P Suffix) OUT A 1 –IN A 2 +IN A 3 V– 4 8 V+ A B 7 OUT B –+ +– 6 –IN B FEATURES Fast Slew Rate: 22 V/ s typ Settling Time (0.01%): 1.2 s max Offset Voltage: 300 V max High Open-Loop Gain: 1000 V/mV min Low Total Harmonic Distortion: 0.002% typ Improved Replacement for AD712, LT1057, OP215, TL072 and MC34082 Available in Die Form APPLICATIONS Output Amplifier for Fast D/As Signal Processing Instrumentation Amplifiers Fast Sample/Holds Active Filters Low Distortion Audio Amplifiers Input Buffer for A/D Converters Servo Controllers 20-Terminal LCC (RC Suffix) OUT A NC NC NC 18 NC 17 OUT B 16 NC 15 –IN B 14 NC 9 10 11 12 13 3 NC 4 –IN A 5 NC 6 +IN A 7 NC 8 2 1 20 19 5 +IN B NC +IN B NC V+ TO-99 (J Suffix) V+ 8 OUTA 1 A –+ B +– 6 –IN B 7 OUT B NC = NO CONNECT 8-Lead SO (S Suffix) +IN A V– +IN B –IN B 1 2 3 4 –A + + –B 8 7 6 5 –IN A OUT A V+ OUT B –IN A 2 +IN A 3 4 V– 5 +IN B GENERAL DESCRIPTION The OP249 is a high speed, precision dual JFET op amp, similar to the popular single op amp, the OP42. The OP249 outperforms available dual amplifiers by providing superior speed with excellent dc performance. Ultrahigh open-loop gain (1 kV/mV minimum), low offset voltage and superb gain linearity, makes the OP249 the industry’s first true precision, dual high speed amplifier. With a slew rate of 22 V/µs typical, and a fast settling time of less than 1.2 µs maximum to 0.01%, the OP249 is an ideal choice for high speed bipolar D/A and A/D converter applications. The excellent dc performance of the OP249 allows the full accuracy of high resolution CMOS D/As to be realized. Symmetrical slew rate, even when driving large load, such as 600 Ω or 200 pF of capacitance, and ultralow distortion, make the OP249 ideal for professional audio applications, active filters, high speed integrators, servo systems and buffer amplifiers. The OP249 provides significant performance upgrades to the TL072, AD712, OP215, MC34082 and the LT1057. 0.010 TA = +25 C VS = 15V VO = 10V p-p RL = 10k AV = +1 870ns 100 90 100 90 10 0% 10 0% 10mV 500ns 5V 1µs 0.001 20 100 1k 10k 20k Figure 1. Fast Settling (0.01%) Figure 2. Low Distortion AV = +1, R L = 1 0 kΩ Figure 3. Excellent Output Drive, RL = 600 Ω R EV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 NC V– OP249–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = S 15 V, TA = +25 C, unless otherwise noted) OP249A Min Typ Max 0.2 0.5 0.8 OP249E Min Typ Max 0.1 0.3 0.6 Min OP249F Typ Max 0.2 0.7 1.0 Units mV mV µV/Month pA pA V V V dB µV/V V/mV V V V mA mA mA mA V/µs MHz µs Degrees Ω pF Ω µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz pA/√Hz V Parameter Offset Voltage Long Term Offset Voltage Offset Stability Input Bias Current Input Offset Current Input Voltage Range Symbol Conditions VOS VOS IB IOS IVR (Note 1) VCM = 0 V, TJ = +25°C VCM = 0 V, TJ = +25°C (Note 2) ± 11 1.5 30 75 6 25 +12.5 ± 11 1.5 20 50 4 15 +12.5 ± 11 80 500 ± 12.0 ± 20 1.5 30 75 6 25 +12.5 –12.5 90 12 50 1200 +12.5 –12.5 +36 Common-Mode Rejection Power-Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO Short-Circuit Current Limit ISC Supply Current Slew Rate Gain-Bandwidth Product Settling Time Phase Margin Differential Input Impedance Open-Loop Output Resistance Voltage Noise Voltage Noise Density ISY SR GBW tS θ0 ZIN RO en p-p en Current Noise Density Voltage Supply Range in VS –12.5 80 90 VCM = ± 11 V 12 31.6 VS = ± 4.5 V to ± 18 V VO = ± 10 V, RL = 2 kΩ 1000 1400 RL = 2 kΩ +12.5 ± 12.0 –12.5 Output Shorted to +36 Ground ± 20 ± 50 –33 No Load, VO = 0 V 5.6 7.0 22 RL = 2 kΩ, CL = 50 pF 18 (Note 4) 3.5 4.7 10 V Step 0.01%3 0.9 1.2 0 dB Gain 55 1012 6 35 0.1 Hz to 10 Hz 2 fO = 10 Hz 75 26 fO = 100 Hz 17 fO = 1 kHz 16 fO = 10 kHz fO = 1 kHz 0.003 ± 4.5 ± 15 ± 18 –12.5 86 95 9 31.6 1000 1400 +12.5 ± 12.0 –12.5 +36 ± 20 ± 50 –33 5.6 7.0 18 22 3.5 4.7 0.9 1.2 55 1012 6 35 2 75 26 17 16 0.003 ± 4.5 ± 15 ± 18 18 3.5 ± 4.5 ± 50 –33 5.6 7.0 22 4.7 0.9 1.2 55 1012 6 35 2 75 26 17 16 0.003 ± 15 ± 18 NOTES 1 Long-term offset voltage is guaranteed by a 1000 HR life test performed on three independent wafer lots at +125 °C with LTPD of three. 2 Guaranteed by CMR test. 3 Settling time is sample tested. 4 Guaranteed by design. Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS (@ V = S 15 V, TA = +25 C, unless otherwise noted) Min OP249G Typ 0.4 40 10 +12.5 –12.0 90 12 1100 +12.5 –12.5 +36 –33 5.6 22 4.7 0.9 55 1012 6 Max 0.2 75 25 Units mV pA pA V V V dB µV/V V/mV V V V mA mA mA mA V/µs MHz µs Degree Ω pF Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Symbol VOS IB IOS IVR Conditions VCM = 0 V, TJ = +25°C VCM = 0 V, TJ = +25°C (Note 1) VCM = ± 11 V VS = ± 4.5 V to ± 18 V VO = ± 10 V; RL = 2 kΩ RL = 2 kΩ ± 11 76 500 ± 12.0 ± 20 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO 50 Short-Circuit Current Limit ISC Output Shorted to Ground ± 50 7.0 Supply Current Slew Rate Gain Bandwidth Product Settling Time Phase Margin Differential Input Impedance ISY SR GBW tS θ0 ZIN No Load; VO = 0 V RL = 2 kΩ, CL = 50 pF (Note 2) 10 V Step 0.01% 0 dB Gain 18 1.2 – 2– REV. C OP249 Parameter Open Loop Output Resistance Voltage Noise Voltage Noise Density Symbol RO en p-p en Conditions 0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz fO = 1 kHz Min OP249G Typ 35 2 75 26 17 16 0.003 ± 15 Max Units Ω µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz pA/√Hz V Current Noise Density Voltage Supply Range NOTES 1 Guaranteed by CMR test. 2 Guaranteed by design. in VS ± 4.5 ± 18 Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS A grade unless otherwise noted) Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current Input Offset Current Input Voltage Range Symbol Conditions VOS TCVOS IB IOS IVR OP249A Min Typ Max 0.12 1.0 (@ VS = 15 V, –40 C ≤ TA ≤ +85 C for E/F grades, and –55 C ≤ TA ≤ +125 C for OP249E Min Typ Max 0.1 0.5 OP249F Typ Max 0.5 1.1 Min Units mV µV/°C nA nA V V V dB µV/V V/mV V V V mA mA (Note 1) (Note 1) (Note 2) ± 11 1 5 4 20 0.04 4 +12.5 –12.5 110 5 50 1400 +12.5 –12.5 ± 11 86 750 ± 12.0 ± 18 1 3 0.25 3.0 0.01 0.7 +12.5 –12.5 100 5 50 1400 +12.5 –12.5 ± 11 80 250 ± 12.0 ± 18 2.2 6 0.3 4.0 0.02 1.2 +12.5 –12.5 90 7 100 1200 +12.5 –12.5 Common-Mode Rejection Power-Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO 76 VCM = ± 11 V VS = ± 4.5 V to ± 18 V RL = 2 kΩ; VO = ± 10 V 500 RL = 2 kΩ ± 12.0 Output Shorted to Ground No Load, VO = 0 V ± 10 Short-Circuit Current Limit Supply Current ISC ISY 5.6 ± 60 7.0 5.6 ± 60 7.0 5.6 ± 60 7.0 NOTES 1 TJ = +85°C for E/F Grades; T J = +125°C for A Grade. 2 Guaranteed by CMR test. Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current Input Offset Current Input Voltage Range Symbol VOS TCVOS IB IOS IVR (@ VS = 15 V, –40 C ≤ TA ≤ +85 C for unless otherwise noted) Min OP249G Typ 1.0 6 0.5 0.04 +12.5 –12.5 95 10 1200 +12.5 –12.5 Max 3.6 25 4.5 1.5 Units mV µV/°C nA nA V V V dB µV/V V/mV V V V mA mA Conditions (Note 1) (Note 1) (Note 2) VCM = ± 11 V VS = ± 4.5 V to ± 18 V RL = 2 kΩ; VO = ± 10 V RL = 2 kΩ ± 11 76 250 ± 12.0 ± 18 Common-Mode Rejection Power-Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO 100 Short-Circuit Current Limit Supply Current NOTES 1 TJ = +85°C . 2 Guaranteed by CMR test. ISC ISY Output Shorted to Ground No Load, VO = 0 V 5.6 ± 60 7.0 Specifications subject to change without notice. REV. C – 3– OP249 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . 36 V Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range . . . . . . . . . . . . –65°C to +175°C Operating Temperature Range OP249A (J, Z, RC) . . . . . . . . . . . . . . . . . . –55°C to +125°C OP249E, F (J, Z) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C OP249G (P, S) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature OP249 (J, Z, RC) . . . . . . . . . . . . . . . . . . . –65°C to +175°C OP249 (P, S) . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C Package Type TO-99 (J) 8-Lead Hermetic DIP (Z) 8-Lead Plastic DIP (P) 20-Terminal LCC (RC) 8-Lead SO (S) 3 JA JC Units °C/W °C/W °C/W °C/W °C/W 145 134 96 88 150 16 12 37 33 41 NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For supply voltages less than ± 18 V, the absolute maximum input voltage is equal to the supply voltage. 3 θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in socket for TO, cerdip, P-DIP, and LCC packages; θJA is specified for device soldered to printed circuit board for SO package. ORDERING GUIDE1 Model OP249AZ2 OP249ARC/883 OP249EJ OP249FZ OP249GP OP249GS3 OP249GS-REEL OP249GS-REEL7 Temperature Range –55°C to +125°C –55°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Descriptions2 8-Lead Cerdip 20-Terminal LCC TO-99 H-08A 8-Lead Cerdip 8-Lead Plastic DIP 8-Lead SO 8-Lead SO 8-Lead SO Package Options Q-8 E-20A H-08A Q-8 N-8 SO-8 SO-8 SO-8 NOTES 1 Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages. 2 For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet. 3 For availability and burn-in information on SO and PLCC packages, contact your local sales office. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP249 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –4– REV. C OP249 DICE CHARACTERISTICS V+ OUT (A) –IN (A) OUT (B) –IN (B) +IN (A) +IN (B) V– DIE SIZE 0.072 0.112 inch, 8,064 sq. mils (1.83 2.84 mm, 5.2 sq. mm) WAFER TEST LIMITS (@ V = S 15 V, TJ = +25 C unless otherwise noted) Symbol VOS TCVOS IB IOS IVR CMR PSRR AVO VO ISC ISY SR Conditions –40°C ≤ TJ ≤ 85°C VCM = 0 V VCM = 0 V (Note 1) VCM = ± 11 V VS = ± 4.5 V to ± 18 V RL = 2 kΩ RL = 2 kΩ Output Shorted to Ground No Load; VO = 0 V RL = 2 kΩ, CL = 50 pF OP249GBC Limits 0.5 6.0 225 75 ± 11 76 100 250 ± 12.0 ± 20/± 60 7.0 16.5 Units mV max µV/°C max pA max pA max V min dB min µV/V max V/mV min V min mA min/max mA max V/µs min Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Short-Circuit Current Limit Supply Current Slew Rate NOTES 1 Guaranteed by CMR test. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. REV. C –5– OP249–Typical Performance Characteristics 120 100 OPEN-LOOP GAIN – dB 65 TA = +25 C VS = 15V RL = 2k 10 GAIN BANDWIDTH PRODUCT – MHz 140 COMMON-MODE REJECTION – dB VS = 60 15V 120 100 80 60 40 20 0 100 TA = +25 C VS = 15V 80 60 40 0 PHASE – C PHASE MARGIN – C 8 m GAIN 45 90 55 GBW 50 6 PHASE 20 0 –20 1k 10k m = 55 135 180 225 100M 4 100k 1M 10M FREQUENCY – Hz 45 –75 –50 –25 0 25 50 75 TEMPERATURE – C 2 100 125 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 4. Open-Loop Gain, Phase vs. Frequency Figure 5. Gain Bandwidth Product, Phase Margin vs. Temperature Figure 6. Common-Mode Rejection vs. Frequency 120 28 TA = +25 C VS = 15V SLEW RATE – V/ s 28 POWER SUPPLY REJECTION – dB 100 26 VS = 15V RL = 2k CL = 50pF SLEW RATE – V/ s 26 TA = +25 C VS = 15V RL = 2k 80 +PSRR 60 –PSRR 40 24 –SR 22 +SR 24 22 20 20 20 0 10 18 16 –75 18 16 100 10k 100k 1k FREQUENCY – Hz 1M –50 –25 0 25 50 75 TEMPERATURE – C 100 125 0 0.2 0.4 0.6 0.8 1.0 DIFFERENTIAL INPUT VOLTAGE – Volts Figure 7. Power Supply Rejection vs. Frequency Figure 8. Slew Rate vs. Temperature Figure 9. Slew Rate vs. Differential Input Voltage 35 TA = +25 C VS = 15V 10 VOLTAGE NOISE DENSITY – nV Hz 100 8 OUTPUT STEP SIZE – Volts 6 4 2 0 –2 –4 –6 –8 30 TA = +25 C VS = 15V AVCL = +1 0.1% 80 TA = +25 C VS = 15V SLEW RATE – V/ s 25 NEGATIVE 0.01% 60 20 POSITIVE 0.01% 40 15 0.1% 20 10 5 –10 0 100 200 300 400 CAPACITIVE LOAD – pF 500 0 0 200 400 600 800 SETTLING TIME – ns 1000 0 100 1k FREQUENCY – Hz 10k Figure 10. Slew Rate vs. Capacitive Load Figure 11. Settling Time vs. Step Size Figure 12. Voltage Noise Density vs. Frequency –6– REV. C OP249 0.010 TA = +25 C VS = 15V VO = 10V p-p RL = 10k AV = +1 0.010 TA = +25 C VS = 15V VO = 10V p-p RL = 2k AV = +1 0.010 TA = +25 C VS = 15V VO = 10V p-p RL = 600 AV = +1 0.001 20 100 1k 10k 20k 0.001 20 100 1k 10k 20k 0.001 20 100 1k 10k 20k Figure 13. Distortion vs. Frequency Figure 14. Distortion vs. Frequency Figure 15. Distortion vs. Frequency 0.10 TA = +25 C VS = 15V VO = 10V p-p RL = 10k AV = +1 0.10 TA = +25 C VS = 15V VO = 10V p-p RL = 2k AV = +10 0.10 TA = +25 C VS = 15V VO = 10V p-p RL = 600 AV = +10 0.010 20 100 1k 10k 20k 0.010 20 100 1k 10k 20k 0.010 20 100 1k 10k 20k Figure 16. Distortion vs. Frequency Figure 17. Distortion vs. Frequency Figure 18. Distortion vs. Frequency 60 50 500mV 1s CLOSED-LOOP GAIN – dB 50 AVCL = +100 40 30 AVCL = +10 20 10 0 –10 –20 1k AVCL = +5 TA = +25 C VS = 15V 40 TA = +25 C VS = 15V IMPEDANCE – +1 V –1 V 30 AVCL = +10 AVCL = +1 20 AVCL = +100 BANDWIDTH (0.1Hz TO 10 Hz) TA = +25 C VS = 15V AVCL = +1 10 10k 100k 1M 10M FREQUENCY – Hz 100M 0 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 19. Low Frequency Noise Figure 20. Closed-Loop Gain vs. Frequency Figure 21. Closed-Loop Output Impedance vs. Frequency REV. C –7– OP249 30 MAXIMUM OUTPUT SWING – Volts 25 80 70 OVERSHOOT – % MAXIMUM OUTPUT SWING – Volts TA = +25 C VS = 15V AVCL = +1 RL = 10k 90 VS = 15V RL = 2k VIN = 100mV p-p AVCL = +1 NEGATIVE EDGE AVCL = +1 POSITIVE EDGE 16 14 12 +VOHM = |–VOHM | 10 8 6 4 2 0 100 TA = +25 C VS = 15V 20 60 50 40 30 20 15 10 5 10 0 1k AVCL = +5 0 100 200 300 400 LOAD CAPACITANCE – pF 500 1k LOAD RESISTANCE – 10k 0 10k 100k 1M FREQUENCY – Hz 10M Figure 22. Maximum Output Swing vs. Frequency Figure 23. Small Overshoot vs. Load Capacitance Figure 24. Maximum Output Voltage vs. Load Resistance 20 6.0 TA = +25 C RL = 2k SUPPLY CURRENT – mA 6.0 VS = 15V NO LOAD OUTPUT VOLTGE SWING – Volts 15 10 5 0 –5 –10 –15 –20 0 5.8 SUPPLY CURRENT – mA 5.8 TA = +25 C 5.6 TA = +125 C 5.4 TA = –55 C 5.2 5.6 5.4 5 10 15 SUPPLY VOLTAGE – Volts 20 5.2 –75 –50 –25 0 25 50 75 TEMPERATURE – C 100 125 5.0 0 5 10 15 SUPPLY VOLTAGE – Volts 20 Figure 25. Output Voltage Swing vs. Supply Voltage Figure 26. Supply Current vs. Temperature Figure 27. Supply Current vs. Supply Voltage 360 320 280 240 UNITS 180 TA = +25 C VS = 15V 350 OP249 (700 OP AMPS) 160 140 120 TA = +25 C VS = 15V 415 OP249 (830 OP AMPS) 270 240 210 180 UNITS VS = 15V –40 C TO +85 C (700 OP AMPS) UNITS 200 160 120 80 40 0 –1k –200 200 600 1k –600 –800 –400 0 400 800 VOS – V 100 80 60 40 20 0 –1k –200 200 600 1k –600 –800 –400 0 400 800 VOS – V 150 120 90 60 30 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V/ C Figure 28. VOS Distribution (J Package) Figure 29. VOS Distribution (P Package) Figure 30. TCVOS Distribution (J Package) –8– REV. C OP249 300 270 240 210 180 UNITS 50 INPUT BIAS CURRENT – pA VS = 15V –40 C TO +85 C (830 OP AMPS) OFFSET VOLTAGE – V 10k VS = 15V VS = 15V VCM = 0V 1k 40 30 150 120 90 60 30 0 0 2 4 6 8 10 12 14 16 18 20 22 24 V/ C 100 20 10 10 0 0 2 4 3 5 1 TIME AFTER POWER APPLIED – Minutes 1 –75 –50 –25 0 25 50 75 100 125 TEMPERATURE – C Figure 31. TCVOS Distribution (P Package) Figure 32. Offset Voltage Warm-Up Drift Figure 33. Input Bias Current vs. Temperature 104 TA = +25 C VS = 15V INPUT BIAS CURRENT – pA 50 TA = +25 C VS = 15V 40 80 BIAS CURRENT – pA 103 INPUT OFFSET CURRENT – pA TA = +25 C VCM = 0V 60 30 102 40 20 101 20 10 100 –15 –10 –5 0 5 10 15 0 0 COMMON-MODE VOLTAGE – Volts 2 4 6 8 10 TIME AFTER POWER APPLIED – Minutes 0 0 25 50 75 –75 –50 –25 TEMPERATURE – C 100 125 Figure 34. Bias Current vs. Common-Mode Voltage Figure 36. Bias Current Warm-Up Drift Figure 36. Input Offset Current vs. Temperature SHORT-CIRCUIT OUTPUT CURRENT – mA 80 VS = OPEN-LOOP GAIN – V/mV 80 VS = 15V 15V 60 60 SOURCE 40 RL = 10k 40 RL = 2k 20 SINK 20 0 0 25 50 75 –75 –50 –25 TEMPERATURE – C 100 125 0 0 25 50 75 –75 –50 –25 TEMPERATURE – C 100 125 Figure 37. Open-Loop Gain vs. Temperature Figure 38. Short-Circuit Output Current vs. Junction Temperature REV. C –9– OP249 V+ +IN VOUT APPLICATIONS INFORMATION –IN The OP249 represents a reliable JFET amplifier design, featuring an excellent combination of dc precision and high speed. A rugged output stage provides the ability to drive a 600 Ω load and still maintain a clean ac response. The OP249 features a large signal response that is more linear and symmetric than previously available JFET input amplifiers—compare the OP249’s large-signal response, as illustrated in Figure 41, to other industry standard dual JFET amplifiers. Typically, JFET amplifier’s stewing performance is simply specified as just a number of volts/µs. There is no discussion on the quality, i e., linearity, symmetry, etc., of the stewing response. V– Figure 39. Simplified Schematic (1/2 OP249) 1/2 OP249 +3V 5k +18V A) OP249 1/2 OP249 +3V –18V 5k Figure 40. Burn-In Circuit B) LT1057 C) AD712 Figure 41. Large-Signal Transient Response, AV = +1, VIN = 20 V p-p, ZL = 2 kΩ//200 pF, VS = ± 15 V –10– REV. C OP249 The OP249 was carefully designed to provide symmetrically matched slew characteristics in both the negative and positive directions, even when driving a large output load. An amplifier’s slewing limitation determines the maximum frequency at which a sinusoidal output can be obtained without significant distortion. It is, however, important to note that the nonsymmetric stewing typical of previously available JFET amplifiers adds a higher series of harmonic energy content to the resulting response—and an additional dc output component. Examples of potential problems of nonsymmetric slewing behavior could be in audio amplifier applications, where a natural low distortion sound quality is desired, and in servo or signal processing systems where a net dc offset cannot be tolerated. The linear and symmetric stewing feature of the OP249 makes it an ideal choice for applications that will exceed the full-power bandwidth range of the amplifier. VERTICAL 50 V/DIV INPUT VARIATION HORIZONTAL 5V/DIV OUTPUT CHARGE Figure 43. Open-Loop Gain Linearity. Variation in OpenLoop Gain Results in Errors in High Closed-Loop Gain Circuits. RL = 600 Ω, VS = ± 15 V R4 +V VIN R5 50k R1 200k R2 31 –V 1/2 OP249 VOUT R3 VOS ADJUST RANGE = V R2 R1 Figure 44. Offset Adjust for Inverting Amplifier Configuration +V Figure 42. Small-Signal Transient Response, AV = +1, ZL = 2 kΩ 100 pF, No Compensation, VS = ± 15 V R5 R3 50k R1 200k R2 33 –V VIN VOS ADJUST RANGE = GAIN = VOUT VIN =1+ V R4 1/2 OP249 VOUT As with most JFET-input amplifiers, the output of the OP249 may undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion will not damage the amplifier, nor will it cause an internal latch-up condition. Supply decoupling should be used to overcome inductance and resistance associated with supply lines to the amplifier. A 0.1 µF and a 10 µF capacitor should be placed between each supply pin and ground. OPEN-LOOP GAIN LINEARITY R2 R1 R5 R4 + R2 1 + R5 IF R2