OP270FZ

Dual Very Low Noise Precision Operational Amplifier OP270 Data Sheet FUNCTIONAL BLOCK DIAGRAMS Very low noise density of 5 nV/√Hz at 1 kHz maximum Excellent input offset voltage of 75 μV maximum Low offset voltage drift of 1 μV/°C maximum Very high gain of 1500 V/mV minimum Outstanding CMR of 106 dB minimum Slew rate of 2.4 V/μs typical Gain bandwidth product of 5 MHz typical Industry-standard 8-lead dual pinout –IN A 1 16 OUT A +IN A 2 15 NC NC 3 14 NC V– 13 V+ 12 NC 4 NC 5 OP270 +IN B 6 11 NC –IN B 7 10 OUT B NC 8 9 NC NC = NO CONNECT 00325-001 FEATURES OUT A 1 –IN A 2 +IN A 3 V– 4 A OP270 B 8 V+ 7 OUT B 6 –IN B 5 +IN B 00325-002 Figure 1. 16-Lead SOIC (S-Suffix) Figure 2. 8-Lead PDIP (P-Suffix) 8-Lead CERDIP (Z-Suffix) GENERAL DESCRIPTION The OP270 is a high performance, monolithic, dual operational amplifier with exceptionally low voltage noise density (5 nV/√Hz maximum at 1 kHz). It offers comparable performance to the industry-standard OP27 from Analog Devices, Inc. consumption of the dual OP270 is one-third less than two OP27 devices, a significant advantage for power conscious applications. The OP270 is unity-gain stable with a gain bandwidth product of 5 MHz and a slew rate of 2.4 V/μs. The OP270 features an input offset voltage of less than 75 μV and an offset drift of less than 1 μV/°C, guaranteed over the full military temperature range. Open-loop gain of the OP270 is more than 1,500,000 into a 10 kΩ load, ensuring excellent gain accuracy and linearity, even in high gain applications. The input bias current is less than 20 nA, which reduces errors due to signal source resistance. With a common-mode rejection (CMR) of greater than 106 dB and a power supply rejection ratio (PSRR) of less than 3.2 μV/V, the OP270 significantly reduces errors due to ground noise and power supply fluctuations. The power The OP270 offers excellent amplifier matching, which is important for applications such as multiple gain blocks, low noise instrumentation amplifiers, dual buffers, and low noise active filters. Rev. F The OP270 conforms to the industry-standard 8-lead CERDIP and PDIP pinouts. For higher speed applications, the ADA4004-2 or the AD8676 are recommended. For a quad op amp, see the OP470 data sheet. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2001–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com OP270 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Voltage and Current Noise ........................................................ 12  Functional Block Diagrams ............................................................. 1  Total Noise and Source Resistance ........................................... 12  General Description ......................................................................... 1  Noise Measurements .................................................................. 14  Revision History ............................................................................... 2  Capacitive Load Driving and Power Supply Considerations .... 15  Specifications..................................................................................... 3  Unity-Gain Buffer Applications ............................................... 15  Electrical Specifications ............................................................... 4  Low Phase Error Amplifier ....................................................... 16  Absolute Maximum Ratings............................................................ 5  Five-Band, Low Noise, Stereo Graphic Equalizer .................. 16  ESD Caution .................................................................................. 5  Digital Panning Control ............................................................ 17  Typical Performance Characteristics ............................................. 6  Dual Programmable Gain Amplifier ....................................... 17  Test Circuits ..................................................................................... 11  Outline Dimensions ....................................................................... 19  Applications Information .............................................................. 12  Ordering Guide .......................................................................... 20  REVISION HISTORY 10/15—Rev. E to Rev. F Changes to General Description Section ...................................... 1 Changes to Supply Voltage Parameter and Differential Input Voltage Parameter, Table 3 .............................................................. 5 Deleted Table 4; Renumbered Sequentially .................................. 5 2/10—Rev. D to Rev. E Change to Input Noise Current Density Parameter, Table 1 ...... 3 Change to Figure 18 ......................................................................... 8 2/09—Rev. C to Rev. D Updated Format .................................................................. Universal Reorganized Layout ............................................................ Universal Changes to Figure 7 .......................................................................... 6 Changes to Figure 22 ........................................................................ 9 Deleted Applications Heading ...................................................... 11 Changes to Figure 44 ...................................................................... 17 Changes to Figure 46 ...................................................................... 18 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 4/03—Rev. B to Rev. C Deletion of OP270A model ............................................... Universal Edits to Features.................................................................................1 Changes to Specifications .................................................................2 Deletion of Wafer Limits and Dice Characteristics ......................4 Changes to Absolute Maximum Ratings ........................................4 Changes to Ordering Guide .............................................................4 Changes to Equations in Noise Measurements section............. 10 Change to Figure 10 ....................................................................... 11 Updated Outline Dimensions ....................................................... 14 11/02—Rev. A to Rev. B Updated Ordering Guide .............................................................. 15 9/02—Rev. 0 to Rev. A Edits to Absolute Maximum Ratings ..............................................5 Edits to Ordering Guide ................................................................ 15 2/01—Revision 0: Initial Version Rev. F | Page 2 of 20 Data Sheet OP270 SPECIFICATIONS VS = ±15 V, TA = 25°C, unless otherwise noted. Table 1. Parameter Input Offset Voltage Input Offset Current Input Bias Current Input Noise Voltage1 Input Noise Voltage Density2 Input Noise Current Density Large-Signal Voltage Gain Symbol VOS IOS IB en p-p en en en in in in AVO Input Voltage Range3 Output Voltage Swing Common-Mode Rejection Power Supply Rejection Ratio Slew Rate Supply Current (All Amplifiers) Gain Bandwidth Product Channel Separation1 IVR VO CMR PSRR Input Capacitance Input Resistance Differential Mode Common Mode Settling Time CIN RIN RINCM tS SR ISY GBP CS Test Conditions VCM = 0 V VCM = 0 V 0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 Hz fO = 100 Hz fO = 1 kHz VO = ±10 V, RL = 10 kΩ VO = ±10 V, RL = 2 kΩ RL ≥ 2 kΩ VCM = ±11 V VS = ±4.5 V to ±18 V OP270E Typ 10 1 5 80 3.6 3.2 3.2 1.1 0.7 0.6 1500 2300 Min Max 150 15 40 200 6.5 5.5 5.0 OP270G Typ 50 5 15 80 3.6 3.2 3.2 1.1 0.7 0.6 750 1500 Min Max 250 20 60 Unit μV nA nA nV p-p nV/√Hz nV/√Hz nV/√Hz pA/√Hz pA/√Hz pA/√Hz V/mV 1200 500 900 350 700 V/mV ±12 ±12 106 ±12.5 ±13.5 125 0.56 ±12 ±12 100 ±12 ±12 90 3.2 ±12.5 ±13.5 120 1.0 5.6 ±12.5 ±13.5 110 1.5 5.6 V V dB μV/V 2.4 4 6.5 2.4 4 6.5 2.4 4 6.5 V/μs mA 1.7 AV = +1, 10 V, step to 0.01% OP270F Typ 20 3 10 80 3.6 3.2 3.2 1.1 0.7 0.6 1000 1700 Min 750 No load VO = ±20 V p-p, fO = 10 Hz Max 75 10 20 200 6.5 5.5 5.0 125 5 175 1.7 1.7 5 175 5 175 MHz dB 3 3 3 pF 0.4 20 5 0.4 20 5 0.4 20 5 MΩ GΩ μs 1 Guaranteed but not 100% tested. Sample tested. 3 Guaranteed by CMR test. 2 Rev. F | Page 3 of 20 125 OP270 Data Sheet ELECTRICAL SPECIFICATIONS VS = ±15 V, −40°C ≤ TA ≤ 85°C, unless otherwise noted. Table 2. Parameter Input Offset Voltage Average Input Offset Voltage Drift Input Offset Current Input Bias Voltage Large-Signal Voltage Gain Symbol VOS TCVOS Test Conditions IOS IB AVO VCM = 0 V VCM = 0 V VO = ±10 V, RL = 10 kΩ VO = ±10 V, RL = 2 kΩ AVO Input Voltage Range1 Output Voltage Swing Common-Mode Rejection Power Supply Rejection Ratio Supply Current (All Amplifiers) 1 IVR VO CMR PSRR RL ≥ 2 kΩ VCM = ±11 V VS = ±4.5 V to ±18 V ISY No load Min OP270E Typ Max 25 150 0.2 1 1000 1.5 6 1800 500 ±12 ±12 100 Min 30 60 OP270F Typ Max 45 275 0.4 2 600 5 15 1400 900 300 ±12.5 ±13.5 120 0.7 ±12 ±12 94 4.4 Min 400 700 225 670 V/mV ±12 ±12 90 5.6 ±12.5 ±13.5 115 1.8 10 ±12.5 ±13.5 100 2.0 1.5 V V dB μV/V 7.2 4.4 7.2 4.4 7.2 mA Rev. F | Page 4 of 20 50 80 Unit μV μV/°C 15 19 1250 Guaranteed by CMR test. 40 70 OP270G Typ Max 100 400 0.7 3 nA nA V/mV Data Sheet OP270 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Differential Input Voltage1 Differential Input Current1 Input Voltage Output Short-Circuit Duration Storage Temperature Range Lead Temperature Range (Soldering, 60 sec) Junction Temperature (TJ) Operating Temperature Range 1 Rating ±18 V ±1.0 V ±25 mA Supply voltage Continuous −65°C to +150°C 300°C −65°C to +150°C −40°C to +85°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION The OP270 inputs are protected by back-to-back diodes. To achieve low noise performance, current-limiting resistors are not used. If the differential voltage exceeds +10 V, the input current should be limited to ±25 mA. Rev. F | Page 5 of 20 OP270 Data Sheet 10 CURRENT NOISE DENSITY (pA/√Hz) TA = 25°C VS = ±15V 5 4 3 1/f CORNER = 5Hz 2 1 1 10 100 TA = 25°C VS = ±15V 1 1/f CORNER = 200Hz 00352-007 10 9 8 7 6 00352-004 VOLTAGE NOISE DENSITY (nV/√Hz) TYPICAL PERFORMANCE CHARACTERISTICS 0.1 10 1k 100 FREQUENCY (Hz) Figure 3. Voltage Noise Density vs. Frequency 10k Figure 6. Current Noise Density vs. Frequency 40 TA = 25°C VS = ±15V 30 4 20 VOLTAGE (µV) AT 10kHz AT 1kHz 3 0 –20 0 ±5 ±10 ±15 –30 –75 ±20 00352-008 1 10 –10 2 00352-005 VOLTAGE NOISE DENSITY (nV/√Hz) 5 1k FREQUENCY (Hz) –50 –25 SUPPLY VOLTAGE (V) Figure 4. Voltage Noise Density vs. Supply Voltage 25 50 75 100 125 Figure 7. Input Offset Voltage vs. Temperature 5 00352-006 TA = 25°C VS = ±15V 4 3 2 1 0 00352-009 NOISE VOLTAGE (100nV/DIV) CHANGE IN OFFSET VOLTAGE (µA) 0.1Hz TO 10Hz NOISE TA = 25°C TS = ±15V 0 TEMPERATURE (°C) 0 1 2 3 4 TIME (Minutes) TIME (1 sec/DIV) Figure 8. Warm-Up Offset Voltage Drift Figure 5. 0.1 Hz to 10 Hz Input Voltage Noise Rev. F | Page 6 of 20 5 Data Sheet 7 OP270 130 VS = ±15V VCM = 0V 110 6 100 90 5 CMR (dB) 4 80 70 60 50 40 3 2 –75 00352-010 30 –50 –25 0 25 50 75 100 00352-013 INPUT BIAS CURRENT (nA) TA = 25°C VS = ±15V 120 20 10 125 1 10 100 TEMPERATURE (°C) Figure 9. Input Bias Current vs. Temperature 3 2 1 –25 0 25 50 75 100 5 4 +125°C +25°C 2 125 –55°C 3 0 ±5 TEMPERATURE (°C) 8 TOTAL SUPPLY CURRENT (mA) 4 3 –7.5 VS = ±15V –5.0 –2.5 0 2.5 5.0 7.5 10.0 6 5 4 3 2 0 –75 12.5 00352-015 1 00352-012 INPUT BIAS CURRENT (nA) 5 –10.0 ±20 7 6 2 ±15 Figure 13. Total Supply Current vs. Supply Voltage TA = +25°C VS = ±15V –12.5 ±10 SUPPLY VOLTAGE (V) Figure 10. Input Offset Current vs. Temperature 7 1M 00352-014 TOTAL SUPPLY CURRENT (mA) 4 –50 100k 6 VS = ±15V VCM = 0V 0 –75 10k Figure 12. CMR vs. Frequency 00352-011 INPUT OFFSET CURRENT (nA) 5 1k FREQUENCY (Hz) –50 –25 0 25 50 75 100 TEMPERATURE (°C) COMMON-MODE VOLTAGE (V) Figure 11. Input Bias Current vs. Common-Mode Voltage Figure 14. Total Supply Current vs. Temperature Rev. F | Page 7 of 20 125 Data Sheet 140 25 TA = 25°C 120 80 TA = 25°C VS = ±15V 20 PHASE SHIFT (Degrees) OP270 100 PHASE +PSR 60 40 0 10 1 10 100 1k 10k 100k 1M 10M 140 PHASE MARGIN = 62° 160 5 GAIN 180 0 –5 00352-016 20 120 –10 100M 1 2 FREQUENCY (Hz) 3 4 5 6 7 8 00352-019 –PSR 80 15 OPEN-LOOP GAIN (dB) PSR (dB) 100 9 10 FREQUENCY (MHz) Figure 15. PSR vs. Frequency Figure 18. Open-Loop Gain and Phase Shift vs. Frequency 140 5000 TA = 25°C VS = ±15V 120 OPEN-LOOP GAIN (V/mA) OPEN-LOOP GAIN (dB) 4000 100 80 60 40 3000 2000 00352-017 10 100 1k 10k 100k 1M 10M 0 100M 0 ±5 ±10 FREQUENCY (Hz) ±15 ±20 ±25 SUPPLY VOLTAGE (V) Figure 16. Open-Loop Gain vs. Frequency 80 Figure 19. Open-Loop Gain vs. Supply Voltage 80 TA = 25°C VS = ±15V 8 PHASE MARGIN (Degrees) 40 20 70 7 Ф 60 6 5 GBP 50 0 –20 1k 00352-018 CLOSED-LOOP GAIN (dB) 60 10k 100k 1M 4 40 –75 10M FREQUENCY (Hz) Figure 17. Closed-Loop Gain vs. Frequency GAIN BANDWIDTH PRODUCT (MHz) 1 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 150 00352-021 0 00352-020 1000 20 Figure 20. Phase Margin and Gain Bandwidth Product vs. Temperature Rev. F | Page 8 of 20 Data Sheet OP270 OUTPUT IMPEDANCE (Ω) 24 20 16 12 8 00352-022 4 0 1k 10k 100k 1M TA = 25°C VS = ±15V AV = 1 75 50 AV = 10 AV = 100 25 0 1k 10M 10k FREQUENCY (Hz) Figure 21. Maximum Output Swing vs. Frequency 15 SLEW RATE (V/µs) 12 NEGATIVE SWING 10 9 8 VS = ±15V 2.6 2.5 –SR 2.4 +SR 7 5 100 1k 2.2 –75 10k 00352-026 2.3 6 –50 LOAD RESISTANCE (Ω) 75 100 125 CHANNEL SEPARATION (dB) 170 20 10 160 150 140 130 120 110 100 90 200 50 180 30 0 25 190 TA = 25°C VS = ±15V VIN = 100mV AV = +1 40 0 Figure 25. Slew Rate vs. Temperature 00352-024 SMALL-SIGNAL OVERSHOOT (%) 50 –25 TEMPERATURE (°C) Figure 22. Maximum Output Voltage vs. Load Resistance 0 10M 2.7 13 00352-023 MAXIMUM OUTPUT VOLTAGE (V) POSITIVE SWING 11 1M Figure 24. Output Impedance vs. Frequency 2.8 TA = 25°C VS = ±15V 14 100k FREQUENCY (Hz) 400 600 800 TA = 25°C VS = ±15V VO = 20V p-p TO 10kHz 80 70 1000 CAPACITIVE LOAD (pF) 1 10 100 00352-027 MAXIMUM OUTPUT SWING (V) 100 TA = 25°C VS = ±15V THD = 1% 00352-025 28 1k 10k 100k FREQUENCY (Hz) Figure 23. Small-Signal Overshoot vs. Capacitive Load Figure 26. Channel Separation vs. Frequency Rev. F | Page 9 of 20 1M OP270 TA = 25°C VS = ±15V AV = +1 RL = 2kΩ TA = 25°C VS = ±15V VO = 20V p-p RL = 2kΩ AV = 10 0.01 0.001 10 100 1k 50mV 200ns 10k FREQUENCY (Hz) Figure 29. Small-Signal Transient Response Figure 27. Total Harmonic Distortion vs. Frequency TA = 25°C VS = ±15V AV = +1 RL = 2kΩ 5V 20µs Figure 28. Large-Signal Transient Response Rev. F | Page 10 of 20 00352-030 00352-028 AV = 1 00352-029 TOTAL HARMONIC DISTORTION (%) 0.1 Data Sheet Data Sheet OP270 TEST CIRCUITS 5kΩ 500Ω 1/2 OP270 V1 20Vp-p 5kΩ 50Ω 1/2 OP270 CHANNEL SEPARATION = 20 LOG Figure 30. Channel Separation Test Circuit +18V 8 100kΩ 2 3 1/2 OP270 1 1/2 OP270 7 200kΩ 6 5 4 –18V Figure 31. Burn-In Circuit Rev. F | Page 11 of 20 00325-032 100kΩ V1 V2/1000 00325-031 V2 OP270 Data Sheet APPLICATIONS INFORMATION The OP270 is a very low noise dual op amp, exhibiting a typical voltage noise density of only 3.2 nV/√Hz at 1 kHz. Because the voltage noise is inversely proportional to the square root of the collector current, the exceptionally low noise characteristic of the OP270 is achieved in part by operating the input transistors at high collector currents. Current noise, however, is directly proportional to the square root of the collector current. As a result, the outstanding voltage noise density performance of the OP270 is gained at the expense of current noise performance, which is normal for low noise amplifiers. Figure 33 also shows the relationship between total noise and source resistance, but at 10 Hz. Total noise increases more quickly than shown in Figure 32 because current noise is inversely proportional to the square root of frequency. In Figure 33, the current noise of the OP270 dominates the total noise when RS is greater than 5 kΩ. Figure 32 and Figure 33 show that to reduce total noise, source resistance must be kept to a minimum. In applications with a high source resistance, the OP200, with lower current noise than the OP270, can provide lower total noise. 100 TOTAL NOISE (nV/√Hz) To obtain the best noise performance in a circuit, it is vital to understand the relationships among voltage noise (en), current noise (in), and resistor noise (et). TOTAL NOISE AND SOURCE RESISTANCE The total noise of an op amp can be calculated by E n  (e n ) 2  (i n R s ) 2  (e t ) 2 where: En is the total input-referred noise. en is the op amp voltage noise. in is the op amp current noise. et is the source resistance thermal noise. RS is the source resistance. OP270 RESISTOR NOISE ONLY 1 100 1k 10k Figure 33. Total Noise vs. Source Resistance (Including Resistor Noise) at 10 Hz Figure 34 shows peak-to-peak noise vs. source resistance over the 0.1 Hz to 10 Hz range. At low values of RS, the voltage noise of the OP270 is the major contributor to peak-to-peak noise, with current noise becoming the major contributor as RS increases. The crossover point between the OP270 and the OP200 for peak-to-peak noise is at a source resistance of 17 kΩ. 1k OP200 PEAK-TO-PEAK NOISE (nV) 100 OP200 10 100 OP270 RESISTOR NOISE ONLY 00352-035 Figure 32 shows the relationship between total noise at 1 kHz and source resistance. When RS is less than 1 kΩ, the total noise is dominated by the voltage noise of the OP270. As RS rises above 1 kΩ, total noise increases and is dominated by resistor noise rather than by the voltage or current noise of the OP270. When RS exceeds 20 kΩ, the current noise of the OP270 becomes the major contributor to total noise. OP270 00352-033 10 100 RESISTOR NOISE ONLY 1 100 1k 100k SOURCE RESISTANCE (Ω) The total noise is referred to the input and at the output is amplified by the circuit gain. TOTAL NOISE (nV/√Hz) OP200 10 00352-034 VOLTAGE AND CURRENT NOISE 10k 100k 1k 10k 100k SOURCE RESISTANCE (Ω) Figure 34. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs. Source Resistance (Including Resistor Noise) SOURCE RESISTANCE (Ω) Figure 32. Total Noise vs. Source Resistance (Including Resistor Noise) at 1 kHz Rev. F | Page 12 of 20 Data Sheet OP270 For reference, typical source resistances of some signal sources are listed in Table 4. Table 4. Typical Source Resistances Device Strain Gage Magnetic Tapehead, Microphone Source Impedance