SSM2161P

a FEATURES Clickless Digitally Controlled Level Adjustment SSM2160: Six Channels SSM2161: Four Channels 7-Bit Master Control Gives 128 Levels of Attenuation 5-Bit Channel Controls Give 32 Levels of Gain Master/Channel Step Size Set by External Resistors 100 dB Dynamic Range Automatic Power On Mute Excellent Audio Characteristics: 0.01% THD+N 0.001% IMD (SMPTE) –90 dBu Noise Floor –80 dB Channel Separation 90 dB SNR Single and Dual Supply Operation APPLICATIONS Home Theater Receivers Surround Sound Decoders Circle Surround* and AC-3* Decoders DSP Soundfield Processors HDTV and Surround TV Audio Systems Automotive Surround Sound Systems Multiple Input Mixer Consoles and Amplifiers GENERAL DESCRIPTION 6- and 4-Channel, Serial Input Master/Balance Volume Controls SSM2160/SSM2161 FUNCTIONAL BLOCK DIAGRAM V+ V– VREF POWER SUPPLY AND REFERENCE GENERATOR VCA CH1 IN CH1 OUT 5-BIT CHANNEL DAC ∑ CH2 IN VCA CH2 OUT 5-BIT CHANNEL DAC ∑ CH3 IN VCA CH3 OUT 5-BIT CHANNEL DAC ∑ CH4 IN VCA CH4 OUT The SSM2160 and SSM2161 allow digital control of volume of six and four audio channels, respectively, with a master level control and individual channel controls. Low distortion VCAs (Voltage Controlled Amplifiers) are used in the signal path. By using controlled rate-of-change drive to the VCAs, the “clicking” associated with switched resistive networks is eliminated in the Master control. Each channel is controlled by a dedicated 5-bit DAC providing 32 levels of gain. A master 7-bit DAC feeds every control port giving 128 levels of attenuation. Step sizes are nominally 1 dB and can be changed by external resistors. Channel balance is maintained over the entire master control range. Upon power-up, all outputs are automatically muted. A three- or four-wire serial data bus enables interfacing with most popular microcontrollers. Windows* software and an evaluation board for controlling the SSM2160 are available. The SSM2160 can be operated from single supplies of +10 V to +20 V or dual supplies from ± 5 V to ± 10 V. The SSM2161 can be operated from single supplies of +8.5 V to +20 V (for automotive applications) or dual supplies from ± 4.25 V to ± 10 V. An on-chip reference provides the correct analog common voltage for single supply applications. Both models come in P-DIP and SO packages. See the Ordering Guide for more details. R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. CLK DATA LD WRITE 5-BIT CHANNEL DAC ∑ CH5 IN VCA CH5 OUT 5-BIT CHANNEL DAC ∑ CH6 IN VCA CH6 OUT 5-BIT CHANNEL DAC 7-BIT MASTER DAC ∑ CH SET STEP SIZE ADJUST MSTR SET MSTR OUT SHIFT REGISTER AND ADDRESS DECODER *Circle Surround is a registered trademark of Rocktron Corporation. AC-3 is a registered trademark of Dolby Labs, Inc. Windows is a registered trademark of Microsoft Corp. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 SSM2160/SSM2161–SPECIFICATIONS 250 kHz, R = 10 k Parameter AUDIO PERFORMANCE Noise floor Total Harmonic Distortion + Noise Channel Separation Dynamic Range ANALOG INPUT Maximum Level Impedance ANALOG OUTPUT Maximum Level3 Impedance Offset Voltage Minimum Resistive Load Maximum Capacitive Load MASTER ATTENUATOR ERROR AV = 0 d B AV = –20 dB AV = –40 dB AV = –60 dB CHANNEL MATCHING CHANNEL GAIN ERROR AV = 0 dB AV = +10 dB AV = +31 dB MUTE ATTENUATION VOLTAGE REFERENCE Accuracy Output Impedance CONTROL LOGIC Logic Thresholds High (1) Low (0) Input Current Clock Frequency Timing Characteristics POWER SUPPLIES Voltage Range SSM2160 SSM2161 SSM2160 SSM2161 Supply Current VREF Percent of (V + ) + (V – ) 2 (VS = 6 V, TA = +25 C, AV = 0 dB, fAUDIO = 1 kHz, fCLOCK = , unless otherwise noted) L Min Typ –90 0.01 80 100 Max Units dBu 0.035 % dB dB 1.8 10 V rms kΩ Symbol NFL THD+N Conditions VIN = GND, BW= 20 kHz, AV = 0 dB1 2nd & 3rd Harmonics Only, VOUT = 0 dBu2 AV = 0 dB Any Channel to Another NFL to Clip Point VS = ± 10 V Any Channel VS = ± 10 V, All Conditions of Master Attenuation and Channel Gain VIN max ZIN 1.8 10 20 10 50 ZOUT RL min CL max Measured from Best Fit of All Channels from 0 dB and –127 dB (or Noise Floor) Channel Gain = 0 dB Channel Gain = 0 dB Channel Gain = 0 dB Channel Gain = 0 dB V rms Ω mV kΩ pF ± 0.5 ± 1.0 ± 2.0 ± 2.5 ± 1.0 dB dB dB dB dB dB dB dB dB Master Attenuation = 0 dB ± 0.5 ± 1.0 ± 2.0 –95 VIN = 0 dBu ±5 5 % Ω Re: DGND 2.0 ±1 1000 0.8 1 See Timing Diagrams V V µA kHz VS V+, V– Single Supply Dual Supply No Load +10 +8.5 ±5 ± 4.25 20 +20 +20 ± 10 ± 10 28 V V V V mA NOTES 1 Master = 0 dB; Channel = 0 dB. 2 Input level adjusted accordingly. 0 dBu = 0.775 V rms. 3 For other than ± 10 V supplies, maximum is V S/4. Specifications subject to change without notice. – 2– REV. 0 SSM2160/SSM2161 Timing Characteristics Timing Symbol tCL tCH tDS tDH tCW tWC tLW tWL tL tW3 Description Input Clock Pulse Width, Low Input Clock Pulse Width, High Data Setup Time Data Hold Time Positive CLK Edge to End of Write Write to Clock Setup Time End of Load Pulse to Next Write End of Write to Start of Load Load Pulse Width Load Pulse Width (3-Wire Mode) Min 200 200 50 75 100 50 50 50 250 250 Typ Max Units ns ns ns ns ns ns ns ns ns ns NOTES 1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the negative edge. 2. For SPI or microwire three-wire bus operation, tie LD to WRITE , and use WRITE pulse to drive both pins. (This generates an automatic internal load signal.) 3. If an idle HI clock is used, t CW and tWL are measured from the final negative transition to the idle state. 4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain/attenuation levels. Refer to the Address/Data Decoding Truth Table. 5. Data must be sent MSB first. 0 CLK 1 1 DATA 0 1 WRITE 0 1 LD 0 D7 D6 D5 D4 D3 D2 D1 D0 tCH 1 CLK 0 tDS 1 DATA 0 1 WRITE 0 1 LD 0 tWC D7 MSB tCL tDH tCW tL tWL tLW Figure 1. Timing Diagrams REV. 0 –3– SSM2160/SSM2161 ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATIONS 24-Lead Epoxy DIP and SOIC V+ 1 AGND 2 VREF 3 VOUT1 4 VIN1 5 VOUT3 6 24 CH SET 23 MSTR OUT 22 MSTR SET 21 VOUT2 Supply Voltage Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Single . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +36 V Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5 V Operating Temperature Range . . . . . . . . . . . . . 0°C to +70°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature Range . . . . . . . . . . . . –65°C to +165°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C ESD Ratings 883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 2.5 kV PACKAGE THERMAL INFORMATION TOP VIEW 19 VOUT4 VIN3 7 (Not to Scale) 18 VIN4 17 VOUT6 16 VIN6 15 DATA 14 CLK 13 DGND SSM2160 20 VIN2 VOUT5 8 VIN5 9 WRITE 10 Package Type3 24-Pin Plastic P-DIP 24-Pin SOIC 20-Pin Plastic P-DIP 20-Pin SOIC JA JC Units °C/W °C/W °C/W °C/W LD 11 V– 12 60 71 65 84 30 23 26 24 20-Lead Epoxy DIP and SOIC V+ 1 AGND 2 VREF 3 VOUT1 4 20 CH SET 19 MSTR OUT 18 MSTR SET 17 VOUT2 NOTES 1 Absolute maximum ratings apply at +25 °C unless otherwise noted. 2 VS is the total supply span from V+ to V–. 3 θJA is specified for the worst case conditions, i.e., for device in socket for P-DIP, packages and for device soldered onto a circuit board for SOIC packages. ORDERING GUIDE Model SSM2160P SSM2160S SSM2160S-REEL SSM2161P SSM2161S SSM2161S-REEL Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C Package Description 24-Lead Plastic DIP 24-Lead SOL 24-Lead SOL 20-Lead Plastic DIP 20-Lead SOL 20-Lead SOL Package Option N-24 R-24 R-24 N-20 R-20 R-20 VIN1 5 VOUT3 6 SSM2161 16 VIN2 TOP VIEW 15 VOUT4 (Not to Scale) VIN3 7 14 VIN4 13 DATA 12 CLK 11 DGND WRITE 8 LD 9 V– 10 –4– REV. 0 SSM2160/SSM2161 PIN DESCRIPTIONS SSM2160 SSM2161 Pin No. 1 2 Pin No. 1 2 Name V+ AGND Function V+ is the positive power supply pin. Refer to the Power Supply Connections section for more information. AGND is the internal ground reference for the audio circuitry. When operating the SSM2160 from dual supplies, AGND should be connected to ground. When operating from a single supply, AGND should be connected to V REF, the internally generated voltage reference. AGND may also be connected to an external reference. Refer to the Power Supply Connections section for more details. VREF is the internally generated ground reference for the audio circuitry obtained from a buffered divider between V+ and V–. In a dual-supply application with the AGND pin connected to ground, VREF should be left floating. In a single supply application, V REF should be connected to AGND. Refer to the Power Supply Connections section for more details. Audio Output from Channel 1. Audio Input to Channel 1. Audio Output from Channel 3. Audio Input to Channel 3. Audio Output from Channel 5. Audio Input to Channel 5. A logic LOW voltage enables the SSM2160 to receive information at the DATA input (Pin 15). A logic HIGH applied to WRITE retains data at their previous settings. See Timing Diagrams. Serves as CHIP SELECT. Loads the information retained by WRITE into the SSM2160 at logic LOW. See Timing Diagrams. V– is the negative power supply pin. Connect to ground if using in a single supply application. Refer to the Power Supply Connections section for more details. DGND is the digital ground reference for the SSM2160. This pin should always be connected to ground. All digital inputs, including WRITE, LD, CLK, and DATA are TTL input compatible; drive currents are returned to DGND. CLK is the clock input. It is positive edge triggered. See Timing Diagrams. Channel and Master control information flows MSB first into the DATA pin. Refer to Address/ Data Decoding Truth Table, Figure 19, for information on how to control the VCAs. Audio Input to Channel 6. Audio Output from Channel 6. Audio Input to Channel 4. Audio Output from Channel 4. Audio Input to Channel 2. Audio Output from Channel 2. MSTR SET is connected to the inverting input of an I-V converting op amp used to generate a Master Control voltage from the Master Control DAC current output. A resistor connected from MSTR OUT to MSTR SET reduces the step size of the Master control. See the Adjusting Step Sizes section for more details. A 10 µF capacitor should be connected from MSTR OUT to MSTR SET to eliminate the zipper noise in the Master control. MSTR OUT is connected to the output of the I-V converting op amp. See MSTR SET description. The step size of the Channel Control can be increased by connecting a resistor from CH SET to V+. No connection to CH SET is required if the default value of 1 dB per step is desired. Minimum of 10 Ω external resistor. See the Adjusting Step Sizes section for more details. 3 3 VREF 4 5 6 7 8 9 10 4 5 6 7 – – 8 CH1 OUT CH1 IN CH3 OUT CH3 IN CH5 OUT CH5 IN WRITE 11 12 13 9 10 11 LD V– DGND 14 15 16 17 18 19 20 21 22 12 13 – – 14 15 16 17 18 CLK DATA CH6 IN CH6 OUT CH4 IN CH4 OUT CH2 IN CH2 OUT MSTR SET 23 24 19 20 MSTR OUT CH SET REV. 0 –5– SSM2160/SSM2161–Typical Performance Characteristics 10 1.0 TA = +25°C VS = ±6V VIN = 0dBu RL = 10kΩ CL = 50pF 1.0 VS = 10V VS = 15V 0.1 0.5 0.1 VS = 20V TA = +25°C DUAL SUPPLY OPERATION VIN = SINEWAVE @ 1kHz RL = 10kΩ, CL = 50pF MASTER/CHANNEL = 0dB VS = ±5V THD+N – % 0.1 THD+N – % THD+N – % VS = ±12V 0.01 0.01 VS = ±6V 0.001 –70 –60 –40 –20 0 GAIN – dB 10 20 0.001 0.01 TA = +25°C SINGLE SUPPLY OPERATION VIN = SINEWAVE @ 1kHz RL = 10kΩ, CL = 50pF MASTER/CHANNEL = 0dB 1 0.1 INPUT VOLTAGE – Vrms 10 0.01 0.005 0.05 0.1 1 INPUT VOLTAGE – Vrms 10 Figure 2. THD vs. Gain 0.1 TA = +25°C DUAL SUPPLY OPERATION VIN = 300mVrms@1kHz RL = 10kΩ, CL = 50pF MASTER/CHANNEL = 0dB LPF: < 22kHz VS = ±12V VS = ±6V Figure 3. THD+N % vs. Amplitude –40 –50 CHANNEL SEPARATION – dB Figure 4. THD+N % vs. Amplitude –40 TA = +25°C –50 V = ±6V S VIN = 1Vrms @ 1kHz –60 R = 10kΩ, C = 50pF L L –60 –70 –80 –90 THD+N – % OUTPUT – dB TA = +25°C VS = ±6V VIN = 1Vrms @ 1kHz VIN = GND (NON SELECTED CH) RL = 100kΩ, CL = 50pF LPF: < 22kHz –70 –80 –90 0.01 –100 –110 –100 –110 –120 20 0.001 20 100 1k FREQUENCY – Hz 10k 30k –120 20 100 1k FREQUENCY – Hz 10k 20k 100 1k FREQUENCY – Hz 10k 30k Figure 5. THD+N % vs. Frequency Figure 6. Channel Separation vs. Frequency –60 –65 –70 –75 TA = 25°C VS = ±6V VIN = GND Figure 7. Mute vs. Frequency NOISE – dBu –80 –85 –90 –95 –100 –105 –110 –70 –60 –40 –30 –20 –10 0 GAIN – dB 10 20 31 40 Figure 8. Noise vs. Gain –6– REV. 0 SSM2160/SSM2161 0 –10 –20 –30 AMPLITUDE – dBu AMPLITUDE – dBu AMPLITUDE – dBu –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 2 4 6 TA = 25°C VS = ±12V VIN = 0dBu @ 1kHz RL = 100kΩ MASTER = 20dB CHANNEL = 0dB 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 2 4 6 TA = 25°C VS = ±12V VIN = –31dBu @ 1Hz RL = 100KΩ MASTER = 0dB CHANNEL = 0dB 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 TA = 25°C VS = ±12V VIN = –31dBu @ 1kHz RL = 100kΩ MASTER = 0dB CHANNEL = 31dB 8 10 12 14 16 18 20 22 FREQUENCY – kHz 8 10 12 14 16 18 20 22 FREQUENCY – kHz 0 2 4 6 8 10 12 14 16 18 20 22 FREQUENCY – kHz Figure 9a. THS vs. Frequency (FFT) 9b. THD vs. Frequency (FFT) Figure 9c. THD vs. Frequency (FFT) 0.1 AMPLITUDE – dBu TA = +25°C VS = ±12V SMPTE 4:1 IM-FREQ 60Hz/7kHz RL = 100kΩ 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 1MD (SMPTE) – % 0.010 TA = 25°C VS = ±12V RL = 100kΩ A MASTER = 0dB CHANNEL = +31dB B MASTER/CHANNEL = 0dB PSR – dB –20 TA = +25°C –30 V = ±6V ± 10% S LPF =