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A1157

A1157

  • 厂商:

    ALLEGRO(埃戈罗)

  • 封装:

  • 描述:

    A1157 - Chopper-Stabilized, Two Wire Hall-Effect Switches - Allegro MicroSystems

  • 数据手册
  • 价格&库存
A1157 数据手册
A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches Features and Benefits ▪ High speed, 4-phase chopper stabilization ▪ Low switchpoint drift throughout temperature range ▪ Low sensitivity to thermal and mechanical stresses ▪ On-chip protection ▫ Supply transient protection ▫ Reverse battery protection ▫ On-board voltage regulator ▫ 3.0 to 24 V operation ▪ Solid-state reliability ▪ Robust EMC and ESD performance ▪ Industry leading ISO 7637-2 performance through use of proprietary, 40-V clamping structures Description The A1150, A1152, A1153, A1155, A1156, A1157, and A1158 comprise a family of two-wire, unipolar, Hall-effect switches, which are factory-trimmed to optimize magnetic switchpoint accuracy. These devices are produced on the Allegro® advanced BiCMOS wafer fabrication process, which implements a patented high frequency, 4-phase, chopper-stabilization technique. This technique achieves magnetic stability over the full operating temperature range, and eliminates offsets inherent in devices with a single Hall element that are exposed to harsh application environments. The A115x family has a number of automotive applications. These include sensing seat track position, seat belt buckle presence, hood/trunk latching, and shift selector position. Two-wire unipolar switches are particularly advantageous in cost-sensitive applications because they require one less wire for operation versus the more traditional open-collector output switches. Additionally, the system designer inherently gains diagnostics because there is always output current flowing, which should be in either of two narrow ranges. Any current level not within these ranges indicates a fault condition. Continued on the next page… Packages 3-pin SOT23-W 2 mm × 3 mm × 1 mm (suffix LH) 3-pin ultramini SIP 1.5 mm × 4 mm × 3 mm (suffix UA) Approximate footprint Functional Block Diagram V+ VCC Regulator To all subcircuits Clock/Logic Sample and Hold Dynamic Offset Cancellation 0.01 μF Low-Pass Filter Schmitt Trigger Polarity Amp GND UA package only GND A1152-DS, Rev. 3 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches Description (continued) All family members are offered in two package styles. The LH is a SOT-23W style, miniature, low profile package for surface-mount applications. The UA is a 3-pin, ultra-mini, single inline package (SIP) for through-hole mounting. Both packages are lead (Pb) free, with 100% matte tin leadframe plating. Selection Guide Part Number Packing1 Package 3-pin SOT23W surface mount 3-pin SIP through hole 3-pin SOT23W surface mount 3-pin SIP through hole 3-pin SOT23W surface mount 3-pin SIP through hole 3-pin SOT23W surface mount 3-pin SIP through hole 3-pin SOT23W surface mount 3-pin SIP through hole 3-pin SOT23W surface mount 3-pin SIP through hole 3-pin SOT23W surface mount 3-pin SIP through hole Output (ICC) in South Polarity Field Low Low Supply Current at ICC(L) (mA) 2 to 5 Magnetic Operate Point, BOP (G) A1150LLHLX-T 13-in. reel, 10 000 pieces/reel A1150LUA-T2 Bulk, 500 pieces/bag A1152LLHLX-T 13-in. reel, 10 000 pieces/reel A1152LUA-T2 Bulk, 500 pieces/bag A1153LLHLX-T 13-in. reel, 10 000 pieces/reel A1153LUA-T2 Bulk, 500 pieces/bag A1155LLHLX-T 13-in. reel, 10 000 pieces/reel A1155LUA-T2 Bulk, 500 pieces/bag A1156LLHLX-T 13-in. reel, 10 000 pieces/reel A1156LUA-T2 Bulk, 500 pieces/bag A1157LLHLX-T 13-in. reel, 10 000 pieces/reel A1157LUA-T2 Bulk, 500 pieces/bag A1158LLHLX-T 13-in. reel, 10 000 pieces/reel A1158LUA-T2 Bulk, 500 pieces/bag 1Contact Allegro® for additional packing options. 2Contact factory for availability. 50 to 110 5 to 6.9 High Low 5 to 6.9 High Low 2 to 5 High 20 to 80 20 to 60 Absolute Maximum Ratings Characteristic Forward Supply Voltage Reverse Supply Voltage Magnetic Flux Density Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VCC VRCC B TA TJ(max) Tstg Range L Notes Rating 28 –18 Unlimited –40 to 150 165 –65 to 170 Unit V V G ºC ºC ºC Pin-out Diagrams 3 Terminal List Table Name VCC VOUT Number LH 1 2 3 UA 1 3 2 Function Input power supply Output signal Ground NC 1 2 1 2 3 GND LH Package UA Package Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches ELECTRICAL CHARACTERISTICS Valid at TA = –40°C to 150°C, TJ < TJ(max), CBYP = 0.01 μF, through operating supply voltage range; unless otherwise noted Characteristics Supply Voltage1,2 Symbol VCC A1150, A1157 ICC(L) Supply Current ICC(H) Supply Zener Clamp Voltage Supply Zener Clamp Current Reverse Supply Current Output Slew Rate3 Chopping Frequency VZ(sup) IZ(sup) IRCC di/dt fc ton POS A1150, A1152, A1155, A1157 A1153, A1156, A1158 B > BOP + 10 G – B < BRP – 10 G – ICC(H) – – – 25 μs A1158 A1152, A1155 A1153, A1156 A1150, A1152, A1155, A1157 A1153, A1156, A1158 Test Conditions Operating, TJ ≤ 165 °C B > BOP B < BRP B > BOP B < BRP B < BRP 12 B > BOP 28 – – – – – – – 90 700 – ICC(L)(max) + 3 mA –1.6 – – V mA mA mA / μs kHz – 17 mA Min. 3.0 2.0 5 Typ. – – – Max. 24 5.0 6.9 Unit V mA mA ICC(L)(max) + 3 mA, TA = 25°C VZ(sup) = 28 V VRCC = –18 V No bypass capacitor, capacitance of probe CS = 20 pF Power-Up Time4,5 Power-Up State2,4,6,7 1V ton < ton(max) , VCC slew rate > 25 mV / μs CC represents the generated voltage between the VCC pin and the GND pin. 2The V CC slew rate must exceed 600 mV/ms from 0 to 3 V. A slower slew rate through this range can affect device performance. 3Measured without bypass capacitor between VCC and GND. Use of a bypass capacitor results in slower current change. 4Power-Up Time is measured without and with bypass capacitor of 0.01 μF. Adding a larger bypass capacitor would cause longer Power-Up Time. 5Guaranteed by characterization and design. 6Power-Up State as defined is true only with a V CC slew rate of 25 mV / μs or greater. 7For t > t on and BRP < B < BOP , Power-Up State is not defined. MAGNETIC CHARACTERISTICS1 Valid at TA = –40°C to 150°C, TJ < TJ (max); unless otherwise noted Characteristics Magnetic Operating Point Symbol BOP A1155, A1156 A1157, A1158 A1150, A1152, A1153 Magnetic Release Point Hysteresis 1Relative Test Conditions A1150, A1152, A1153 Min. 50 20 20 45 10 10 5 Typ. – – – – – – – Max. 110 60 80 105 55 60 30 Unit2 G G G G G G G BRP BHYS A1155, A1156 A1157, A1158 values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present). 2 1 G (gauss) = 0.1 mT (millitesla). Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Package LH, on 1-layer PCB with copper limited to solder pads Package Thermal Resistance RθJA Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side Package UA, on 1-layer PCB with copper limited to solder pads *Additional thermal information available on the Allegro website Value 228 110 165 Unit ºC/W ºC/W ºC/W Power Derating Curve 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 20 VCC(max) Maximum Allowable VCC (V) 2-layer PCB, Package LH (RθJA = 110 ºC/W) 1-layer PCB, Package UA (RθJA = 165 ºC/W) 1-layer PCB, Package LH (RθJA = 228 ºC/W) VCC(min) 120 140 160 180 40 60 80 100 Temperature (ºC) Power Dissipation versus Ambient Temperature 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 20 Power Dissipation, PD (m W) 2l (R aye rP θJ C A= 11 B, P 0 º ac 1-la C/ ka yer W (R PC ) ge L θJA = B H 165 , Pac kag ºC/ eU W) A 1-lay er P (R CB, θJA = 228 Packag ºC/W e LH ) 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches Characteristic Performance A1152/A1153/A1155/A1156 A1152/A1153/A1155/A1156 Average Supply Current (Low) versus Temperature 7.0 Average Supply Current (Low) versus Supply Voltage 7.0 Supply Current, ICC(L) (mA) Supply Current, ICC(L) (mA) 6.5 VCC = 24 V 6.0 VCC = 3.0 V 5.5 6.5 TA = 150°C TA = –40°C 6.0 TA = 25°C 5.5 5.0 -60 5.0 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26 Ambient Temperature, TA (°C) Supply Voltage, VCC (V) A1150/A1157/A1158 A1150/A1157/A1158 Average Supply Current (Low) versus Temperature 5.0 Average Supply Current (Low) versus Supply Voltage 5.0 5.0 Supply Current, ICC(L) (mA) Supply Current, ICC(L) (mA) 4.5 4.0 VCC = 24 V 3.5 VCC = 3.0 V 3.0 2.5 2.0 -60 4.5 4.0 3.5 3.0 2.5 2.0 TA = 150°C TA = 25°C TA = –40°C -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26 Ambient Temperature, TA (°C) Supply Voltage, VCC (V) A1150/A1152/A1153/A1155/A1156/A1157/A1158 A1150/A1152/A1153/A1155/A1156/A1157/A1158 Average Supply Current (High) versus Temperature 17 Average Supply Current (High) versus Supply Voltage 17 Supply Current, ICC(H) (mA) Supply Current, ICC(H) (mA) 16 VCC = 24 V VCC = 3.0 V 14 16 TA = –40°C TA = 150°C TA = 25°C 15 15 14 13 13 12 -60 12 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26 Ambient Temperature, TA (°C) Supply Voltage, VCC (V) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches A1150/A1152/A1153 A1155/A1156 Average Operate Point versus Temperature 110 100 Average Operate Point versus Temperature 60 55 Applied Flux Density at Operate Point, BOP (G) Applied Flux Density at Operate Point, BOP (G) 50 45 40 35 30 25 20 -60 -40 -20 0 20 40 60 80 100 120 140 160 VCC = 24 V VCC = 3.0 V 90 VCC = 24 V 80 VCC = 3.0 V 70 60 50 -60 -40 -20 0 20 40 60 80 100 120 140 160 Ambient Temperature, TA (°C) Ambient Temperature, TA (°C) A1150/A1152/A1153 A1155/A1156 Average Release Point versus Temperature 105 Average Release Point versus Temperature 55 50 Applied Flux Density at Release Point, BRP (G) 95 85 75 65 55 45 -60 Applied Flux Density at Release Point, BRP (G) 45 40 35 30 25 20 15 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 VCC = 3.0 V VCC = 24 V VCC = 3.0 V VCC = 24 V -40 -20 0 20 40 60 80 100 120 140 160 Ambient Temperature, TA (°C) Ambient Temperature, TA (°C) A1150/A1152/A1153/A1155/A1156/A1157/A1158 A1150/A1152/A1153/A1155/A1156/A1157/A1158 Average Switchpoint Hysteresis versus Temperature Applied Flux Density at Switchpoint Hysteresis, BHYS (G) 30 Average Switchpoint Hysteresis versus Temperature Applied Flux Density at Switchpoint Hysteresis, BHYS (G) 30 25 25 20 20 15 VCC = 24 V 10 VCC = 3.0 V 15 VCC = 3.0 V VCC = 24 V 10 5 -60 -40 -20 0 20 40 60 80 100 120 140 160 5 -60 -40 -20 0 20 40 60 80 100 120 140 160 Ambient Temperature, TA (°C) Ambient Temperature, TA (°C) Ambient Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches Functional Description The A1150, A1152, A1155, and A1157 output, ICC, switches low after the magnetic field at the Hall sensor IC exceeds the operate point threshold, BOP . When the magnetic field is reduced to below the release point threshold, BRP , the device output goes high. This is shown in figure 1, panel A. In the case of the reverse output polarity, as in the A1153, A1156, and A1158, the device output switches high after the magnetic field at the Hall sensor IC exceeds the operate point threshold, BOP . When the magnetic field is reduced to below the release point threshold, BRP, the device output goes low (panel B). The difference between the magnetic operate and release points is called the hysteresis of the device, BHYS . This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. I+ ICC(H) I+ ICC(H) Switch to High ICC(L) 0 Switch to High Switch to Low Switch to Low ICC ICC ICC(L) 0 BRP BHYS BHYS (A) Hysteresis curve for A1150, A1152, A1155, and A1157 (B) Hysteresis curve for A1153, A1156, and A1158 Figure 1. Alternative switching behaviors are available in the A115x device family. On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B– direction indicates decreasing south polarity field strength (including the case of increasing north polarity). BOP B– B+ B– B+ BRP BOP Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches RSENSE V+ VCC V+ VCC A115x CBYP 0.01 μF A115x CBYP 0.01 μF GND A ECU GND GND A A Package UA Only GND RSENSE (A) Low side sensing (B) High side sensing Figure 2. Typical application circuits Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall sensor IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. The patented Allegro technique, namely Dynamic Quadrature Offset Cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover Regulator its original spectrum at base band, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. The chopper stabilization technique uses a 350 kHz high frequency clock. For demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sampleand-hold circuits. Clock/Logic Hall Element Amp Low-Pass Filter Figure 3. Chopper stabilization circuit (Dynamic Quadrature Offset Cancellation) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Sample and Hold 8 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches Power Derating The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating TJ. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, RJA, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, RJC, is relatively small component of RJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate TJ, at PD. PD = VIN × IIN  T = PD × RJA TJ = TA + ΔT For example, given common conditions such as: TA= 25°C, VCC = 12 V, ICC = 4 mA, and RJA = 140 °C/W, then: PD = VCC × ICC = 12 V × 4 mA = 48 mW  T = PD × RJA = 48 mW × 140 °C/W = 7°C TJ = TA + T = 25°C + 7°C = 32°C A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding TJ(max), at a selected RJA and TA. (1) (2) (3) Example: Reliability for VCC at TA = 150°C, package UA, using a low-K PCB. Observe the worst-case ratings for the device, specifically: RJA = 165 °C/W, TJ(max) = 165°C, VCC(max) = 24 V, and ICC(max) = 17 mA. Calculate the maximum allowable power level, PD(max). First, invert equation 3: Tmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = Tmax ÷ RJA = 15°C ÷ 165 °C/W = 91 mW Finally, invert equation 1 with respect to voltage: VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 17 mA = 5 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages ≤VCC(est). Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and VCC(max) is reliable under these conditions. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches Package LH, 3-Pin SOT23W +0.12 2.98 –0.08 1.49 D 3 A 4°±4° +0.020 0.180–0.053 0.96 D +0.10 2.90 –0.20 D +0.19 1.91 –0.06 0.25 MIN 1.00 1 2 0.55 REF 0.25 BSC Seating Plane Gauge Plane 8X 10° REF Branded Face 2.40 0.70 0.95 B PCB Layout Reference View 1.00 ±0.13 NNT +0.10 0.05 –0.05 0.95 BSC 0.40 ±0.10 1 C Standard Branding Reference View N = Last two digits of device part number T = Temperature code For Reference Only; not for tooling use (reference DWG-2840) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A B Active Area Depth, 0.28 mm REF Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Branding scale and appearance at supplier discretion Hall element, not to scale C D Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches Package UA, 3-Pin SIP +0.08 4.09 –0.05 45° B C E 2.05 NOM 10° E 1.52 ±0.05 Mold Ejector Pin Indent Branded Face 0.79 REF 45° NNN 1.44 NOM +0.08 3.02 –0.05 E 1.02 MAX A 1 D Standard Branding Reference View 1 2 3 = Supplier emblem N = Last three digits of device part number 14.99 ±0.25 +0.03 0.41 –0.06 For Reference Only; not for tooling use (reference DWG-9065) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown +0.05 0.43 –0.07 A B C Dambar removal protrusion (6X) Gate and tie bar burr area Active Area Depth, 0.50 mm REF Branding scale and appearance at supplier discretion Hall element (not to scale) D E 1.27 NOM Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A1150, A1152, A1153, A1155, A1156, A1157, and A1158 Chopper-Stabilized, Two Wire Hall-Effect Switches Revision History Revision Rev. 3 Revision Date May 3, 2011 Description of Revision Add A1157 and A1158 variants Copyright ©2009-2011, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12
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