APEK8650KLY-01-MH-DK

A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK FEATURES AND BENEFITS DESCRIPTION • Automotive AEC-Q100 qualified • Operating voltage range: 2.5 to 5.5 V • UVLO stop threshold: 2.25 V (max) • Adjustable switching frequency (fOSC): 0.25 to 2.45 MHz • Synchronizes to external clock: 1.2× to 1.5× fOSC (typ) • Internal 70 mΩ high-side switching MOSFET • Internal 55 mΩ low-side switching MOSFET • Capable of at least 2.0 A steady-state output current • Sleep mode supply current less than 3 μA • Adjustable output voltage as low as 0.8 V with ±1% accuracy from –40°C to 125°C • Soft start time externally set via the SS pin • Pre-biased startup capable • Externally adjustable compensation The A8650 is an adjustable frequency, high output current, PWM regulator that integrates a high-side P-channel MOSFET and a low-side N-channel MOSFET. The A8650 incorporates current-mode control to provide simple compensation, excellent loop stability, and fast transient response. The A8650 uses external compensation to accommodate a wide range of power components to optimize transient response without sacrificing stability. The A8650 regulates input voltages from 2.5 to 5.5 V, down to output voltages as low as 0.8 V, and is able to supply at least 2.0 A of load current. The A8650 features include an externally adjustable switching frequency, an externally set soft start time to minimize inrush currents, an EN/SYNC input to either enable VOUT and/or synchronize the PWM switching frequency, and a Power OK (POK) output to indicate when VOUT is within regulation. The sleep mode current of the A8650 control circuitry is less than 3 μA. Protection features include VIN undervoltage lockout Continued on the next page… PACKAGES: 10-pin MSOP with exposed thermal pad (suffix LY) 10-pin DFN with exposed thermal pad (suffix EJ) Continued on the next page… APPLICATIONS: • GPS/Infotainment • Automobile Audio • Home Audio • Network and Telecom Not to scale Typical Application Diagram VIN 10 CIN1 3.3 µF 1206 CIN2 0.1 µF 0805 CIN3 10 nF 0603 9 2 EN/SYNC CSS 10 nF RFSET 10.7 kΩ 3 8 5 6 CP 22 pF VIN SW A8650 GND PGND FB 1 7 LO 1.0 µH COMP CO1 10 µF 1206 RFB1 9.09 kΩ RFB2 7.15 kΩ EN/SYNC SS FSET VOUT CO2 10 µF 1206 CO3 0.1 µF 0805 CO4 10 nF 0603 3.3V RPU 10 kΩ POK 4 POK RZ 6.65 kΩ CZ 1.5 nF Typical application schematic, configured for VIN = 5 V , VOUT = 1.8 V, IOUT = 2.0 A at 2 MHz A8650-DS, Rev. 10 MCO-0000837 June 11, 2021 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 FEATURES AND BENEFITS (continued) DESCRIPTION (continued) • Stable with ceramic output capacitors • Enable input, and Power OK (POK) output • Cycle-by-cycle current limiting (OCP) • Hiccup mode short circuit protection (HIC) • Overvoltage protection (OVP) • Overtemperature protection (TSD) • Open circuit and adjacent pin short circuit tolerant • Short to ground tolerant at every pin (UVLO), cycle-by-cycle overcurrent protection (OCP), hiccup mode short circuit protection (HIC), overvoltage protection (OVP), and thermal shutdown (TSD). In addition, the A8650 provides open circuit, adjacent pin short circuit, and short to ground protection at every pin to satisfy the most demanding automotive applications. The A8650 is available in both 10-pin MSOP and DFN packages with an exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. SELECTION GUIDE Part Number Operating Ambient Temperature Range TA, (°C) Package Packing Leadframe Plating A8650KLYTR-T –40 to 125 10-pin MSOP with exposed thermal pad 4000 pieces per 13-in. reel 100% matte tin A8650KEJTR-T –40 to 125 10-pin DFN with exposed thermal pad 1500 pieces per 7-in reel 100% matte tin ABSOLUTE MAXIMUM RATINGS [1] Characteristic VIN Pin to GND SW to GND [2] Symbol Notes VIN VSW Continuous t < 50 ns All other pins Unit –0.3 to 6 V –0.3 to VIN + 0.3 V –1.0, VIN + 2.0 V –0.3 to 6.0 V Operating Ambient Temperature TA –40 to 125 °C Maximum Junction Temperature TJ(max) 150 °C Tstg –55 to 150 °C Storage Temperature K temperature range Rating [1] Operation at levels beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability. [2] SW has internal clamp diodes to GND and V  . Applications that forward bias these diodes should take care not to exceed the IC package power dissipation limits. IN THERMAL CHARACTERISTICS: May require derating at maximum conditions, see application information Value Unit Package Thermal Resistance (LY) Characteristic Symbol RθJA On 4-layer PCB based on JEDEC standard Test Conditions* 48 °C/W Package Thermal Resistance (EJ) RθJA On 4-layer PCB based on JEDEC standard 45 °C/W *Additional thermal information available on the Allegro website. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK Table of Contents Specifications 2 Functional Block Diagram 4 5 Characteristic Performance 9 Pin-out Diagram and Terminal List Functional Description Overview Reference Voltage Oscillator/Switching Frequency Transconductance Error Amplifier Slope Compensation Sleep Mode Enable/Synchronization (EN/SYNC) Input Power MOSFETs Pulse Width Modulation (PWM) Current Sense Amplifier Soft Start (Startup) and Inrush Current Control Pre-Biased Startup Power OK (POK) Output 11 11 11 11 11 11 12 12 12 13 13 13 13 14 Protection Features Undervoltage Lockout (UVLO) Thermal Shutdown (TSD) Overvoltage Protection (OVP) Cycle-by-Cycle Overcurrent Protection (OCP) Output Short Circuit (Hiccup Mode) Protection Application Information Design and Component Selection Setting the Output Voltage (VOUT, RFB1, RFB2) Base PWM Switching Frequency (RFSET) Output Inductor (LO) Output Capacitors Input Capacitors Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ , CZ , CP ) A Generalized Tuning Procedure Power Dissipation and Thermal Calculations PCB Component Placement and Routing Package Outline Drawing Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14 14 14 14 14 15 18 18 18 18 19 20 21 21 22 24 25 27 29 3 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 FUNCTIONAL BLOCK DIAGRAM VIN Current Sense CURRENT fOSC Oscillator FSET PWM_CLK fSYNC ADJ EN/SYNC > 1.2 x fOSC Slope Compensation Reset Dominant PWM Comparator Regulators - ON POR + 10 ns - EN/SYNC Sleep 100 kΩ VIN 0.8V VSSOFFS 200 mV 150 nA + 0.8 V (max) POR Error Amplifier + + - FB EN/SYNC + 1.65 V (typ) 1.25 V (typ) Digital Delay - Q R Q SW VIN 55 mΩ Off PGND CLAMP_ACTIVE COMP POR TSD Protection CURRENT EN CURRENT (OCP) FAULT EN / CLR LATCHED FAULT = 1, if: VIN (UVLO) EN = 0 or FB EN_HICCUP UVLO = 1 CLAMP_ACTIVE OCP COUNT EN 1.5 kΩ OFF HICCUP HIC RST (100 mV) HICCUP HICCUP HICCUP = 1 if: FB < 625 mV and COMP ≈ 1.25 V and 7 OCP events 2 kΩ 10 µA 20 µA POK OFF + 115% x VREF 111% x VREF FB 92% x VREF 88% x VREF OFF UV / OV OV FBOK POK Comparator + 125 ns OVP Comparator - SS Clamp 1.25 V S tOFF(MIN) VPWMOFFS 350 mV VREF 70 mΩ Off GND FBOK VIN Non-Overlap ADJ Falling Delay 7 PWM Cycles PAD Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 PINOUT DIAGRAMS AND TERMINAL LIST TABLE 10 VIN SW 1 EN/SYNC 3 SW 1 10 VIN PGND 2 9 GND EN/SYNC 3 8 SS POK 4 7 FB FSET 5 6 COMP 9 GND PGND 2 PAD POK 4 FSET 5 8 SS 7 FB 6 COMP Package LY, 10-Pin MSOP Pinout Diagram PAD Package EJ, 10-Pin DFN Pinout Diagram Terminal List Table Number Name Function The drain of both the internal high- and low-side MOSFETs. The output inductor (LO) should be connected to this pin. LO should be placed as close as possible to this pin and connected with relatively wide traces. 1 SW 2 PGND 3 EN/SYNC 4 POK Power OK output signal. This pin is an open drain output that transitions from low impedance to high impedance when the output is within the final regulation voltage. 5 FSET Frequency setting pin. A resistor, RFSET , from this pin to GND sets the PWM switching frequency. See figure 10 and/or equation 2 to determine the value of RFSET . 6 COMP Output of the error amplifier and compensation node for the current mode control loop. Connect a series RC network from this pin to GND for loop compensation. See the Design and Component Selection sections of this datasheet for further details. 7 FB Feedback (negative) input to the error amplifier. Connect a resistor divider from the regulator output node, VOUT, to this pin to program the output voltage. 8 SS Soft start pin. Connect a capacitor, CSS , from this pin to GND to set the soft start time. This capacitor also determines the hiccup period during overcurrent. 9 GND Ground connection. 10 VIN Power input for the control circuits and the source of the internal high-side P-channel MOSFET. Connect this pin to a power supply of 2.5 to 5.5 V. A high quality ceramic capacitor should be placed very close to this pin. – PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s) of the PCB with at least 6 vias, directly in the pad. Power ground connection. Enable and synchronization input. This pin is a logic input that turns the regulator on or off: set this pin to logic high to turn the regulator on or set this pin to logic low to turn the regulator off. This pin also functions as a synchronization input to allow the PWM frequency to be set by an external clock. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK ELECTRICAL CHARACTERISTICS: Valid at –40°C ≤ TA = TJ ≤ 125°C, VIN = 5 V; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit 2.5 − 5.5 V INPUT VOLTAGE SPECIFICATIONS Operating Input Voltage Range VIN VIN UVLO Start Threshold VINUVSTART VIN rising 2.00 2.22 2.45 V VIN UVLO Stop Threshold VINUVSTOP VIN falling 1.80 2.02 2.25 V VIN UVLO Hysteresis VINUVHYS − 200 − mV VEN/SYNC = 5 V, VFB = 1.0 V, no PWM switching − 2 4 mA VIN = VSW = 5 V, VEN/SYNC ≤ 0.4 V − 1 3 μA 792 800 808 mV INPUT CURRENTS Input Quiescent Current IQ Input Sleep Supply Current IQSLEEP REFERENCE VOLTAGE Reference (Feedback) Voltage VREF 2.5 < VIN < 5.5 V, VFB = VCOMP ERROR AMPLIFIER Feedback Input Bias Current [1] IFB Open Loop Voltage Gain [2] VCOMP = 0.7 V, VFB regulated so that ICOMP = 0 A AVOL Transconductance gm ICOMP = 0 μA, VSS > 500 mV – –150 –300 nA − 65 − dB 550 750 950 μA/V 0 V < VSS < 500 mV – 250 – μA/V Source Current IEA(SRC) VFB < 0.8 V, VCOMP = 0.7 V − –50 − μA Sink Current IEA(SINK) VFB > 0.8 V, VCOMP = 0.7 V − +50 − μA 1.00 1.25 1.50 V FAULT = 1, HICCUP = 1, or EN/SYNC = low − 1.5 − kΩ VCOMP for 0% duty cycle − 350 − mV − 65 105 ns − 50 100 ns Maximum Output Voltage VEAO(MAX) COMP Pull Down Resistance RCOMP PULSE WIDTH MODULATION (PWM) PWM Ramp Offset VPWMOFFS High-Side MOSFET Minimum Controllable On-Time tON(MIN) Low-Side MOSFET Minimum On‑Time tOFF(MIN) Gate Driver Non-Overlap Time [2] COMP to SW Current Gain Slope Compensation [2] Does not include total gate driver non-overlap time, 2 x tNO tNO − 15 − ns gmPOWER − 4.5 − A/V fsw = 2.0 MHz 1.65 2.35 2.85 A/μs fsw = 0.25 MHz 0.21 0.29 0.36 A/μs TA = 25°C, IDS = 100 mA − 70 80 mΩ IDS = 100 mA − − 145 mΩ VIN = 5 V − 12 − ns VEN/SYNC ≤ 0.4 V, VSW = 0 V, VIN = 5 V, –40˚C < TA = TJ < 85˚C − − 4 μA TA = TJ = 125˚C − 5 25 μA SE MOSFET PARAMETERS High-Side MOSFET On-Resistance [3] SW Node Rise Time [2] High-Side MOSFET Leakage [4] RDS(ON)HS tR(SW) ILKG(HS) Continued on the next page… Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK ELECTRICAL CHARACTERISTICS (Continued): Valid at –40°C ≤ TA = TJ ≤ 125°C, VIN = 5 V; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit TA = 25°C, IDS = 100 mA − IDS = 100 mA − 55 65 mΩ − 115 VEN/SYNC ≤ 0.4 V, VSW = 5 V, –40˚C < TA = TJ < 85˚C mΩ − − 1 μA VEN/SYNC ≤ 0.4 V, VSW = 5 V, TA = TJ = 125˚C − 4 10 μA RFSET = 8.45 kΩ 2.20 2.45 2.70 MHz RFSET = 23.2 kΩ 0.90 1.00 1.10 MHz RFSET = 100 kΩ − 250 − kHz 1.2 × fOSC − 1.5 × fOSC – − − 2.9 MHz MOSFET PARAMETERS (continued) Low-Side MOSFET On-Resistance [3] RDS(on)LS Low-Side MOSFET Leakage [4] ILKG(LS) OSCILLATOR FREQUENCY Oscillator Frequency fOSC SYNCHRONIZATION TIMING Synchronization Frequency Range fSW(MULT) Synchronized PWM Frequency Relative to fOSC(typ) fSYNC Synchronization Input Duty Cycle DSYNC Synchronization Input Pulse Width tPWSYNC VIN = 3.3 V, VEN/SYNC = 3.3 V pulse input − − 80 % 200 − − ns Synchronization Input Edge Rise Time [2] trSYNC − 10 15 ns Synchronization Input Edge Fall Time [2] tfSYNC − 10 15 ns ENABLE/SYNCHRONIZATION INPUT EN/SYNC High Threshold VEN/SYNC(H) VEN/SYNC rising − − 1.8 V EN/SYNC Low Threshold VEN/SYNC(L) VEN/SYNC falling 0.8 − − V EN/SYNC Hysteresis VEN/SYNC VEN/SYNC(H) – VEN/SYNC(L) − 200 − mV tSLEEP VEN/SYNC transitioning low − 32 − PWM cycles 50 100 − kΩ − 10 − ns EN/SYNC Digital Delay (HYS) EN/SYNC Input Resistance REN/SYNC EN/SYNC Pulse Rejection tEN/SYNCR VIN = 3.3 V, VEN/SYNC = 1.3 V pulse input OVERCURRENT PROTECTION (OCP) AND HICCUP MODE ILIM(5%) Duty Cycle = 5% 3.5 4.1 4.7 A ILIM(90%) Duty Cycle = 90% 2.3 3.1 4.2 A Hiccup Disable Threshold HICDIS VFB rising − 750 − mV Hiccup Enable Threshold HICEN VFB falling − 625 − mV Hiccup enabled, OCP pulses − 7 − counts Pulse-by-Pulse Current Limit OCP / HICCUP Count Limit OCPLIMIT Continued on the next page… Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK ELECTRICAL CHARACTERISTICS (Continued): Valid at –40°C ≤ TA = TJ ≤ 125°C, VIN = 5 V; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit 120 200 270 mV SOFT START (SS PIN) SS Offset Voltage VSSOFFS VSS rising due to ISSSU SS Fault/Hiccup Reset Voltage VSS_RESET VSS falling due to ISSHIC − 100 120 mV −10 –20 −30 μA VSS = 0.5 V, HICCUP = 1 5 10 20 μA FAULT = 1 or EN/SYNC = low − 2 − KΩ tSS(DELAY) CSS = 22 nF − 175 − μs tSS CSS = 22 nF − 880 − μs VFB = 0 V − fSW / 3 − − VFB ≥ 600 mV − fSW − − SS Startup (Source) Current ISSSU VSS = 1 V, HICCUP = FAULT = 0 SS Hiccup (Sink) Current ISSHIC SS Input Resistance SS to VOUT Delay Time VOUT Soft Start Ramp Time SS Switching Frequency RSS fSW(SS) POWER OK (POK PIN) OUTPUT POK Output Voltage POK Undervoltage Threshold POK Undervoltage Hysteresis POK Overvoltage Threshold POK Overvoltage Hysteresis VPOK POKUV IPOK = 4 mA − − 0.4 V VFB rising, as a percent of VREF 89 92 95 % POKUVHYS VFB falling, as a percent of VREF POKOV VFB rising, as a percent of VREF POKOVHYS VFB falling, as a percent of VREF − 4 − % 112 115 118 % − 4 − % POK Digital Delay POKDLY VFB rising only − 7 − PWM cycles POK Leakage IPOK(LKG) VPOK = 5 V, VCOMP ≤ 0.3 V − − 1 μA THERMAL SHUTDOWN PROTECTION (TSD) Thermal Shutdown Threshold [2] TTSD Temperature rising 155 170 185 °C Thermal Shutdown Hysteresis [2] TTSDHYS Temperature falling − 20 − °C [1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. [3] T = T = 25˚C ensured by design and characterization, not production tested. A J [4] T = T = 85˚C ensured by design and characterization, not production tested. A J Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 CHARACTERISTIC PERFORMANCE Reference Voltage versus Temperature 2.75 806 2.50 804 2.25 802 2.00 fOSC (MHz) V REF (mV) 808 800 798 f OSC = 2.44 MHz 1.75 f OSC = 1.00 MHz 1.50 796 1.25 794 1.00 792 Switching Frequency versus Temperature 0.75 -50 -25 0 25 50 75 100 125 150 -50 -25 0 Temperature (°C) 125 150 Threshold (% of VFB) 110 2.20 VIN (V) 100 115 Stop, VINUVSTOP 2.30 2.10 2.00 1.90 1.80 POKOV, VFB rising 105 POKOV, VFB falling 100 POKUV, VFB rising POKUV, VFB falling 95 90 85 1.70 80 -50 4.5 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Cycle-by-Cycle Current Limit at t ON(MIN) versus Temperature Error Amplifier Transconductance versus Temperature 950 4.4 150 900 4.3 850 4.2 4.1 EA gm (µA/V) ILIM (5%) (A) 75 POKOV and POKUV Thresholds versus Temperature 120 Start, VINUVSTART 2.40 50 Temperature (°C) VIN UVLO Start and Stop Thresholds versus Temperature 2.50 25 4.0 3.9 3.8 800 750 700 650 3.7 600 3.6 3.5 550 -50 -25 0 25 50 75 Temperature (°C) 100 125 150 -50 -25 0 25 50 75 100 125 150 Temperature (°C) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 EN/SYNC High and Low Thresholds versus Temperature 1.8 25 VEN/SYNC(L) 1.7 23 VEN/SYNC(H) SS Pin Current (µA) 1.6 EN/SYNC (V) 1.5 1.4 1.3 1.2 1.1 -25 0 25 50 75 100 125 Hiccup, ISSHIC 13 10 150 -50 -25 0 25 50 75 100 Temperature (°C) POK Low Output Voltage versus Temperature Hiccup Enable and Disable Thresholds versus Temperature 850 VPOK at 4 mA 0.30 125 825 HICEN, VFB falling 800 HICDIS, VFB rising 150 775 0.25 Threshold (mV) (V) Startup, ISSSU 15 Temperature (°C) 0.35 V POK 18 5 -50 0.20 0.15 0.10 750 725 700 675 650 625 600 0.05 575 0.00 550 -50 4.0 -25 0 25 50 75 100 125 150 Temperature (°C) -50 25 50 75 Temperature (°C) VIN Sleep Current versus Temperature High- and Low-Side MOSFETs Leakage versus Temperature 20.0 3.5 17.5 3.0 15.0 Leakage Current (µA) IQSLEEP (µA) 20 8 1.0 0.40 Soft Start Startup and Hiccup Currents versus Temperature 2.5 2.0 1.5 1.0 0.5 -25 0 100 125 150 High-Side, ILKG(HS) Low-Side, ILKG(LS) 12.5 10.0 7.5 5.0 2.5 0.0 0.0 -50 -25 0 25 50 75 Temperature (°C) 100 125 150 -50 -25 0 25 50 75 100 125 150 Temperature (°C) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK FUNCTIONAL DESCRIPTION Overview The A8650 is a synchronous PWM regulator that incorporates all the control and protection circuitry necessary to satisfy a wide range of low voltage applications. The A8650 employs current mode control to provide fast transient response, simple compensation, and excellent stability. The features of the A8650 include a ±1% precision reference, an adjustable switching frequency, a transconductance error amplifier, an enable/synchronization input, integrated power MOSFETs, adjustable soft-start time, pre-bias startup capability, low current sleep mode, and a Power OK (POK) output. The protection features of the A8650 include undervoltage lockout (UVLO), cycle-by-cycle overcurrent protection (OCP), hiccup mode short circuit protection (HIC), overvoltage protection (OVP), and thermal shutdown (TSD). In addition, the A8650 provides open circuit, adjacent pin short circuit, and pin-toground short circuit protection. Reference Voltage The A8650 incorporates an internal reference that allows output voltages as low as 0.8 V. The accuracy of the internal reference is ±1% across the entire operating temperature range. The output voltage of the regulator is adjusted by connecting a resistor divider (RFB1 and RFB2 in the typical application schematic) from VOUT to the FB pin of the A8650. Oscillator/Switching Frequency The base PWM switching frequency, fOSC , of the A8650 is adjustable from 250 kHz to 2.45 MHz and has an accuracy of ±12% across the operating temperature range. The base frequency is used to set the device switching frequency, fSW  , which can also be further increased by the optional synchronization function (described later in the section on EN/SYNC operation) . Connecting a resistor from the FSET pin to GND, as shown in the typical application schematic, sets the base switching frequency. An FSET resistor with ±1% tolerance is recommended. A graph of fOSC versus RFSET , and an equation to calculate RFSET , are provided in the Component Selection section of this datasheet. Transconductance Error Amplifier The primary function of the transconductance error amplifier is to regulate the A8650 output voltage. The error amplifier is shown in figure 1 as a device with three inputs, two positive and one negative. The negative input simply is connected to the FB pin and is used to sense the feedback voltage for regulation. The two positive inputs are connected to the soft start and reference voltages, and the error amplifier performs an analog OR selection between them. It regulates to either the soft start pin voltage minus the Soft Start Offset (200 mV (typ)) or the A8650 internal reference, whichever is lower. To stabilize the regulator, a series RC compensation network (RZ CZ) must be connected from the error amplifier output (COMP pin) to GND as shown in the typical application schematic. In most applications, an additional, low value capacitor (CP) should be connected in parallel with the RZ CZ compensation network to roll-off the loop gain at higher frequencies. However, if the CP capacitor is too large, the phase margin of the regulator may be reduced. If the regulator is disabled or a fault occurs, the COMP pin is immediately pulled to GND via an internal 1.5 kΩ pull-down and PWM switching is inhibited. Slope Compensation The A8650 incorporates internal slope compensation to allow PWM duty cycles near or above 50% to accommodate a wide range of input/output voltages, switching frequencies, and inductor values. As shown in the functional block diagram, the slope compensation signal is added to the sum of the current sense and PWM Ramp Offset (VPWMOFFS). The amount of slope compensation is scaled directly with the base switching frequency (fOSC , set by RFSET). However, the amount of slope compensation does VSSOFFS 200 mV SS Pin + + VREF 800 mV - Error Amplifier COMP Pin FB Pin Figure 1. A8650 Error Amplifier Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK not change when the synchronization function is used to alter the switching frequency. Sleep Mode If the voltage at the EN/SYNC pin is low for more than 32 PWM clock cycles, the A8650 discharges the soft start capacitor (via a 2 kΩ pulldown) until VSS ≈ 100 mV. At that time the A8650 will enter sleep mode and draw less than IQSLEEP (3 μA (max)) from VIN . However, the total current drawn by the VIN pin will be the sum of the current drawn by the control circuitry plus any leakage due to the high- and low-side MOSFETs ( ILKG(HS), and ILKG(LS) ). Enable/Synchronization (EN/SYNC) Input The enable/synchronization (EN/SYNC) input provides three functions: enabling/disabling the A8650 with system control, enabling/disabling the A8650 automatically, and synchronizing the output PWM frequency synchronization to an external clock signal input. When EN/SYNC is being used as a system controlled enabling/ disabling logic input, when EN/SYNC is kept high, the A8650 turns on and, provided there are no fault conditions, VOUT will ramp to its final voltage in a time set by the soft start capacitor (CSS ). When EN/SYNC is brought low for more than 32 PWM clock cycles (see figure 2) the voltage at the soft start pin is discharged by a 2 kΩ pulldown, and VSS will decay quickly starting from the input voltage level. When VSS drops below ≈ 100 mV, the A8650 will enter sleep mode and draw less than 3 µA from the input. A timing diagram showing startup and shutdown using EN/SYNC is shown in figure 8. The short delay (the 32 PWM clock cycles between when EN/SYNC transitions to low and when PWM switching stops) is necessary because the enable circuitry must distinguish between the relatively constant enabling/ disabling function logic levels and the longest allowed pulses generated when the EN/SYNC frequency synchronization function also is being used. When used in the frequency synchronization function, EN/SYNC accepts an external clock to scale the PWM switching frequency (fSW) from 1.2× to 1.5× above the base frequency (fOSC ) set by the RFSET resistor. The applied clock pulses must satisfy the pulse width, duty cycle, and rise/fall time requirements shown in the Electrical Characteristics table in this datasheet. Note that when EN/SYNC is used as a synchronization input, soft start still occurs at the base frequency (fOSC ) and synchronization to the external clock occurs only after soft start is complete (when VFB > POKUV). Finally, when used to automatically enable the A8650, the EN/SYNC input pin is connected to VIN via a resistor, as shown in figure 3. The series resistance is recommended to prevent large VIN capacitors from discharging into the EN/SYNC pin at powerdown. Power MOSFETs The A8650 includes a 70 mΩ, high-side P-channel MOSFET capable of delivering up to 4.1 A at 5% duty cycle. The A8650 also includes a 55 mΩ, low-side N-channel MOSFET to provide synchronous rectification. The low-side MOSFET continues to conduct when the inductor current crosses zero to maintain constant conduction mode (CCM). This helps to minimize EMI/EMC for noise sensitive VEN/SYNC VCOMP VOUT 32 PWM cycles VSS VSS = 100 mV Sleep mode Figure 2. PWM switching stops 32 PWM cycles after EN/SYNC transitions low, and sleep mode begins when VSS decays to VSS_RESET (100 mV) VIN 1 kΩ EN/SYNC PIN Figure 3. External circuit for automatically enabling the A8650 from VIN Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK applications by eliminating the SW output high-frequency ringing associated with discontinuous conduction mode (DCM). When a fault occurs or the A8650 is disabled, the SW pin becomes high impedance by turning off both the upper and lower MOSFETs. Pulse Width Modulation (PWM) A high-speed PWM comparator, capable of pulse widths less than 105 ns, is included in the A8650. The inverting input of the comparator is connected to the output of the error amplifier. The non-inverting input is connected to the sum of the current sense signal, the slope compensation, and the PWM Ramp Offset ( VPWMOFFS ). At the beginning of each PWM cycle, the PWM_CLK signal sets the PWM flip flop and the high-side MOSFET is turned on. When the summation of the current sense signal, the slope compensation, and the DC PWM Ramp Offset rises above the error amplifier voltage, the comparator resets the PWM flip flop and the high-side MOSFET is turned off. After a short delay to prevent cross-conduction (tNO), the low-side MOSFET is turned on. The PWM flip flop is reset dominant so, if the output voltage of the error amplifier drops below the PWM Ramp Offset, then PWM 0% duty cycle (that is, pulse skipping) operation is achieved. Current Sense Amplifier A high-bandwidth current sense amplifier monitors the current in the high-side MOSFET. The current signal is supplied to the PWM comparator, the cycle-by-cycle current limiter, and the hiccup mode counter. Soft Start (Startup) and Inrush Current Control Inrush currents to the regulator are controlled by the soft start function. When the A8650 is enabled, after all faults are cleared the soft start pin will source approximately 20 μA ( ISSSU ) and the voltage on the soft start capacitor (CSS) will ramp upward from 0 V. When the voltage at the soft start pin exceeds the Soft Start Offset (VSSOFFS , 200 mV(typ)), the error amplifier output slews upward and, shortly thereafter, PWM switching will begin. As shown in figure 4, there is a short delay (tSS(DELAY) ) between when the EN/SYNC pin transitions high and when the soft start voltage reaches 200 mV. After the A8650 starts switching, the error amplifier will regulate the voltage at the FB pin to the soft start pin voltage minus the Soft Start Offset voltage. After switching starts, the voltage at the SS pin will rise from 200 mV to 1000 mV, a difference of 800 mV. At the same time, the voltage at the FB pin will rise from 0 V to 800 mV and the regulator output voltage will rise from 0 V to the setpoint determined by the feedback resistor divider (RFB1 and RFB2). When the voltage at the soft start pin reaches approximately 1000 mV, the error amplifier will change mode and begin regulating to the A8650 internal reference, 800 mV. The voltage at the soft start pin will continue to rise to approximately VIN . Complete soft start operation is shown in figure 4. During startup, the PWM switching frequency is scaled linearly from fOSC / 3 to fOSC as the voltage at the FB pin ramps from 0 V to 600 mV. This is done to prevent the output inductor current from climbing to a level that may damage the A8650 when the input voltage is high and the output of the regulator is either shorted or soft starting a relatively high capacitance or very heavy load. Pre-Biased Startup If the output capacitors are pre-biased, the A8650 will shift the startup routine parameters to prevent discharging the output capacitors. Normally, PWM switching starts when the voltage at the soft start pin reaches approximately 200 mV. However, in the case with pre-biasing, the voltage at the FB pin (VFB) is nonzero. Switching will not start until the voltage at the soft-start VEN/SYNC VOUT = 1.8 V Switching starts when VCOMP > 350 mV VOUT VCOMP VSS = 1000 mV tSS VSS IL tSS(DELAY) VSS = 200 mV Figure 4. Startup to VOUT = 1.8 V, at IOUT = 2.0 A with CSS = 10 nF Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 pin increases to approximately VFB + 200 mV. At this voltage, the error amplifier output will slew upward. Shortly thereafter, PWM switching starts and VOUT ramps upward from the prebias level. Figure 5 shows startup when the output voltage is pre‑biased to 0.9 V. Power OK (POK) Output The Power OK (POK) output is an open drain output, so an external pull-up resistor must be connected to it. An internal comparator monitors the voltage at the FB pin and controls the internal open drain N-MOSFET at the POK pin. POK is high when the voltage at the FB pin is within regulation. The POK output is pulled low if any of the following are true: • VFB is rising, and is < 92% of the internal reference voltage, or • VFB is rising, and is > 115% of the internal reference voltage, or • EN/SYNC is low for more than 32 PWM clock cycles, or • VIN pin UVLO occurs, or • Thermal Shutdown (TSD) occurs. If the A8650 is running and EN/SYNC transitions low for more than 32 PWM clock cycles, then POK will transition low and remain low only as long as the internal circuitry is able to enhance the open-drain output device. When VIN fully collapses, POK will return to the high impedance state. The POK comparator incorporates hysteresis to prevent chattering due to voltage ripple at the FB pin. VEN/SYNC VOUT VOUT rises from 0.9 V VOUT = 0.9 V VOUT = 1.8 V Switching starts when VCOMP > 350 mV COMP pin released at VSS > VFB + 200 mV VCOMP VSS IL VSS = 200 mV Figure 5. Startup to VOUT = 1.8 V, VOUT pre-biased to 0.9 V Protection Features Undervoltage Lockout (UVLO) An undervoltage lockout (UVLO) comparator monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage is below the lockout threshold (VINUVSTART). The UVLO comparator incorporates enough hysteresis (VINUVHYS ) to prevent on/off cycling of the regulator due to IR drops in the VIN path during heavy loading or during startup. Figure 8 shows the A8650 operation for a UVLO-initiated startup (EN/SYNC = high, VIN ramps up). Thermal Shutdown (TSD) The A8650 protects itself from overheating by means of an internal thermal monitoring circuit. If the junction temperature exceeds the thermal shutdown threshold (TTSD , 170°C (typ)) the voltages at the soft start and COMP pins will be pulled to GND and both the high-side and low-side MOSFETs will be turned off. The A8650 will automatically restart when the junction temperature decreases more than the thermal shutdown hysteresis (TTSDHYS , 20°C(typ)). Figure 8 shows the A8650 operation during and after a TSD event. Overvoltage Protection (OVP) The A8650 uses the FB pin to provide a basic level of overvoltage protection. An overvoltage condition could occur if the load current decreases very quickly or the regulator output is pulled high by some external voltage. When an overvoltage condition is detected, POK is pulled low and PWM switching stops. The COMP and soft start pins are not directly affected by OVP. If the regulator output decreases back to the allowed operating range, POK will transition to high and PWM switching will resume. Cycle-by-Cycle Overcurrent Protection (OCP) The A8650 monitors the current in the high-side MOSFET and if the current exceeds the cycle-by-cycle overcurrent threshold (ILIM ) then the high-side MOSFET is turned off. Normal PWM operation resumes on the next clock pulse from the oscillator. The A8650 includes leading edge blanking to prevent falsely triggering the cycle-by-cycle current limit when the upper MOSFET is turned on. Because of the addition of the slope compensation ramp to the inductor current, the A8650 delivers more current at lower duty cycles and less current at higher duty cycles. For a given duty cycle, this results in a little more current being available at lower switching frequencies than at higher frequencies. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK Figure 6 shows the typical and worst-case cycle-by-cycle current limits versus duty cycle, at 2.45 MHz and 250 kHz. so, when hiccup occurs, the voltage at the soft start pin ramps downward. Output Short Circuit (Hiccup Mode) Protection Hiccup mode protects the A8650 when the load is either too high or when the output of the regulator is shorted to ground. When the voltage at the FB pin is below the Hiccup Enable Threshold (HICEN , 625 mV(typ)) hiccup mode protection is enabled. When the voltage at the FB pin is above the Hiccup Disable Threshold (HICDIS , 750 mV(typ)) hiccup mode protection is disabled. When the voltage at the soft start pin decays to a low level (VSS_RESET, 100 mV (typ) ), the hiccup latch is cleared and the 10 µA soft start pin current sink is turned off. Also, the soft start pin begins charging the soft start capacitor with 20 µA, so the voltage at the soft start pin begins to ramp upward. When the voltage at the soft start pin exceeds the Soft Start Offset (VSSOFFS , 200 mV (typ)) the error amplifier will force the voltage at the COMP pin to quickly ramp upward and, shortly thereafter, PWM switching will resume. If the short circuit at the regulator output remains, another hiccup cycle will occur. Hiccup cycles will repeat until the short circuit is removed or the regulator is disabled. If the short circuit is removed, the A8650 will soft start normally and the output voltage will be ramped to the setpoint level. Hiccup mode operation is shown in both figures 7 and 8. Hiccup Mode overcurrent protection monitors the number of overcurrent events using an up/down counter. An overcurrent pulse increments the counter by one and a PWM cycle without an overcurrent pulse decrements the counter by one. If more than seven consecutive overcurrents are detected, then the hiccup latch is set and PWM switching is stopped. The HICCUP signal causes the COMP pin to be pulled low. Hiccup mode also enables a current sink connected to the soft start pin (nominally 10 µA) 4.8 Short removed 4.6 VOUT 4.4 4.2 4.0 3.8 VCOMP ILIM (A) 3.6 3.4 Hiccup latch clears VCOMP ramp accelerates IOUT  too high ≈ 4.1 A 3.2 3.0 2.8 MIN_2.45 MHz 2.6 MIN_250 kHz 2.2 2.0 IL MAX_2.45 MHz 2.4 VSS = 200 mV VSS = 100 mV VSS TYP_2.45 MHz TYP_250 kHz MAX_250 kHz 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Duty Cycle (%) Figure 6. Cycle-by-cycle current limiting versus duty cycle; at fSW = 250 kHz (dashed curves) and fSW = 2.45 MHz (solid curves) Figure 7. Hiccup mode operation and recovery Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 TABLE 1. Summary of A8650 Fault Modes and Operation Fault Mode VSS VCOMP High-Side MOSFET and fSW Low-Side MOSFET POK State Reset Condition Output hard short to ground (VOUT = VFB = 0 V) Hiccup after VCOMP ≈ 1.25 V and 7 overcurrent faults Clamped to ≈1.25 V for ILIM , then pulled low during hiccup Controlled by VCOMP . fSW / 3 if 0< VFB> CP . In most cases, RO > 2 MΩ, 1 kΩ < RZ < 100 kΩ, 220 pF