UCN5810AF

5810-F UCN5810AF OUT 8 OUT 7 OUT 6 CLOCK GROUND LOGIC SUPPLY STROBE OUT 5 OUT 4 1 2 3 LATCHES 4 5 6 7 8 9 VDD ST CLK REGISTER REGISTER LATCHES BLNK 13 12 11 10 BLANKING OUT 1 OUT 2 OUT 3 VBB 15 14 18 17 16 OUT 9 OUT 10 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BiMOS II 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS The UCN5810AF, UCN5810EPF, and UCN5810LWF combine a 10-bit CMOS shift register and accompanying data latches, control circuitry, bipolar sourcing outputs with DMOS active pull-downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The UCN5810AF/EPF/LWF feature reduced supply requirements (active DMOS pull-downs) and lower saturation voltages when compared with the original UCN5810A. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V supply, they will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial data output enables cascade connections in applications requiring additional drive lines. Similar devices are available as the UCN5811A (12 bits), UCN5812AF/EPF (20 bits), and UCN5818AF/EPF (32 bits). The UCN5810AF/EPF/LWF output source drivers are NPN Darlingtons capable of sourcing up to 40 mA. The DMOS active pull-downs are capable of sinking up to 15 mA. For inter-digit blanking, all of the output drivers can be disabled and the DMOS sink drivers turned on by the BLANKING input high. The UCN5810AF is furnished in an 18-pin dual in-line plastic package. The UCN5810EPF is furnished in a 20-lead plastic chip carrier. The UCN5810LWF is furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and lower output saturation voltages allow all devices to source 25 mA from all outputs continuously, over the entire operating temperature range. All devices are also available for operation between -40°C and +85°C. To order, change the prefix from ‘UCN’ to ‘UCQ’. Data Sheet 26182.24C Dwg. PP-029 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Logic Supply Voltage, VDD ..................... 15 V Driver Supply Voltage, VBB .................... 60 V Continuous Output Current Range, IOUT .......................... -40 mA to +15 mA Input Voltage Range, VIN ........................ -0.3 V to VDD + 0.3 V Package Power Dissipation, PD (UCN5810AF) ........................... 2.27 W* (UCN5810EPF) ........................ 1.78 W* (UCN5810LWF) ........................ 1.56 W* Operating Temperature Range, TA .................................. -20°C to +85°C Storage Temperature Range, TS ................................ -55°C to +150°C *Derate linearly to 0 W at +150°C. FEATURES I High-Speed Source Drivers I 60 V Minimum Output Breakdown I Improved Replacements for TL4810B I Low Output Saturation Voltages I Low-Power CMOS Logic and Latches I To 3.3 MHz Data Input Rate I Active DMOS Pull-Downs Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Note that the UCN5810AF (dual in-line package) and UCN5810LWF (small-outline IC package) are electrically identical and share a common pin number assignment. Always order by complete part number, e.g., UCN5810AF . 5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS UCN5810EPF 20 19 OUT10 OUT 6 FUNCTIONAL BLOCK DIAGRAM CLOCK V DD LOGIC SUPPLY SERIAL DATA OUT 3 2 1 CLOCK NC GROUND LOGIC SUPPLY STROBE 4 5 6 7 8 CLK LATCHES REGISTER 18 V BB 17 16 SERIAL DATA OUT LOAD SUPPLY NC SERIAL DATA IN BLANKING SERIAL DATA IN STROBE SERIAL-PARALLEL SHIFT REGISTER LATCHES V DD ST REGISTER 15 LATCHES BLNK 14 BLANKING MOS BIPOLAR 12 10 11 13 9 OUT 5 OUT1 VBB Dwg. PP-059 LOAD SUPPLY GROUND OUT 1 OUT 2 OUT 3 OUT N Dwg. FP-013-1 UCN5810LWF OUT 8 OUT 7 OUT 6 CLOCK GROUND LOGIC SUPPLY STROBE OUT 5 OUT 4 1 2 3 LATCHES 4 5 6 7 8 9 VDD ST CLK REGISTER REGISTER LATCHES BLNK 13 12 11 10 BLANKING OUT 1 VBB 15 14 18 17 16 OUT 9 OUT 10 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN TYPICAL INPUT CIRCUIT VDD IN OUT 2 OUT 3 Dwg. PP-029-1 Dwg. PP-029-1 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 SUFFIX 'EP', R θJA = 59°C/W Dwg. EP-010-4A 2.0 SUFFIX 'A', R θJA = 60°C/W TYPICAL OUTPUT DRIVER V BB 1.5 1.0 0.5 SUFFIX 'LW', R θJA = 80°C/W OUT N 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. GP-024B Dwg. GP-024A Dwg. No. A-14,219 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1988, 2000 Allegro MicroSystems, Inc. 5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V unless otherwise noted. Limits @ VDD = 5 V Characteristic Output Leakage Current Output Voltage Symbol ICEX VOUT(1) VOUT(0) Test Conditions VOUT = 0 V, TA = +70°C IOUT = -25 mA IOUT = 1 mA IOUT = 2 mA Output Pull-Down Current IOUT(0) VOUT = 5 V to VBB VOUT = 20 V to VBB Input Voltage VIN(1) VIN(0) Input Current IIN(1) IIN(0) Serial Data Output Voltage VOUT(1) VOUT(0) Maximum Clock Frequency Supply Current fclk IDD(1) IDD(0) IBB(1) IBB(0) Blanking to Output Delay tPHL tPLH Output Fall Time Output Rise Time tf tr All Outputs High All Outputs Low Outputs High, No Load Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% CL = 30 pF, 90% to 10% CL = 30 pF, 10% to 90% VIN = VDD VIN = 0.8 V IOUT = -200 µA IOUT = 200 µA Mln. — 58 — — 2.0 — 3.5 -0.3 — — 4.5 — 3.3* — — — — — — — — Typ. -5.0 58.5 1.0 — 3.5 — — — — -0.05 4.7 200 — 100 100 0.7 10 2000 1000 1450 650 Max. -15 — 1.5 — — — 5.3 +0.8 100 -0.5 — 250 — 300 300 2.0 100 — — — — Limits @ VDD = 12 V Min. — 58 — — — 8.0 10.5 -0.3 — — 11.7 — — — — — — — — — — Typ. -5.0 58.5 — 1.0 — 13 — — — -0.1 11.8 100 — 200 200 0.7 10 1000 850 650 700 Max. -15 — — 1.5 — — 12.3 +0.8 240 -1.0 — 200 — 500 500 2.0 100 — — — — Units µA V V V mA mA V V µA µA V mV MHz µA µA mA µA ns ns ns ns Negative current is defined as coming out of (sourcing) the specified device pin. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. www.allegromicro.com 5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS CLOCK DATA IN C STROBE BLANKING G OUTN Dwg. No. A-12,649A A B D E F Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. TIMING REQUIREMENTS (TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) .......................................................................... 75 ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................. 75 ns C. Minimum Data Pulse Width ................................................................ 150 ns D. Minimum Clock Pulse Width ............................................................... 150 ns E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns F. Minimum Strobe Pulse Width ............................................................. 100 ns G. Typical Time Between Strobe Activation and Output Transistion ......................................................................... 500 ns Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency. TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X L = Low Logic Level H = High Logic Level X = Irrelevant Latch Contents I1 I2 I3 ... IN-1 IN Blanklng Output Contents I1 I2 I3 ... IN-1 IN R1 R2 R3 ... X X X ... RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L P1 P2 P3 ... PN-1 PN X X ... P = Present State R = Previous State 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS UCN5810AF Dimensions in Inches (controlling dimensions) 18 10 0.014 0.008 0.430 0.280 0.240 MAX 0.300 BSC 1 0.070 0.045 0.100 0.920 0.880 BSC 9 0.005 MIN 0.210 MAX 0.015 MIN 0.150 0.115 0.022 0.014 Dwg. MA-001-18A in Dimensions in Millimeters (for reference only) 10 0.355 0.204 18 10.92 7.11 6.10 MAX 7.62 BSC 1 1.77 1.15 2.54 23.37 22.35 BSC 9 0.13 MIN 5.33 MAX 0.39 MIN 3.81 2.93 0.558 0.356 Dwg. MA-001-18A mm NOTES: 1. 2. 3. 4. Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 21 devices. www.allegromicro.com 5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS UCN5810EPF Dimensions in Inches (controlling dimensions) 13 0.021 0.013 0.169 0.141 14 0.395 0.385 0.032 0.026 INDEX AREA 9 8 0.050 0.169 0.141 BSC 0.356 0.350 18 4 19 0.020 MIN 20 1 2 3 0.356 0.350 0.395 0.385 Dwg. MA-005-20A in 0.180 0.165 Dimensions in Millimeters (for reference only) 13 0.533 0.331 4.29 3.58 14 10.03 9.78 0.812 0.661 INDEX AREA 9 8 1.27 4.29 3.58 BSC 9.042 8.890 18 4 19 0.51 MIN 20 1 2 3 9.042 8.890 10.03 9.78 Dwg. MA-005-20A mm 4.57 4.20 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 48 devices or add “TR” to part number for tape and reel. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS UCN5810LWF Dimensions in Inches (for reference only) 18 10 0.0125 0.0091 0.2992 0.2914 0.419 0.394 0.050 0.016 0.020 0.013 1 2 3 0.4625 0.4469 0.050 BSC 0° TO 8° 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-18A in Dimensions in Millimeters (controlling dimensions) 18 10 0.32 0.23 7.60 7.40 10.65 10.00 1.27 0.40 0.51 0.33 1 2 3 11.75 11.35 1.27 BSC 0° TO 8° 2.65 2.35 0.10 MIN. Dwg. MA-008-18A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 41 devices or add “TR” to part number for tape and reel. www.allegromicro.com 5810-F 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000