UCN5811

581 1 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS Designed primarily for use with vacuum-fluorescent displays, the UCN5811A smart power BiMOS II driver features low-output saturation voltages and high output switching speed. These devices contain CMOS shift registers, data latches, and control circuitry, and bipolar high-speed sourcing outputs with DMOS active pull-down circuitry. The high-speed shift register and data latches allow direct interface with microprocessor-based systems. A CMOS serial data output enables cascade connections in applications requiring additional drive lines. The UCN5811A features 60 V and -40 mA output ratings, allowing it to be used in many other peripheral power driver applications. It can be used as an improved replacement tor the SN75512B. The Allegro devices do not require special power-up sequencing. The UCN5811A has been designed with BiMOS II logic for improved data entry rates. With a 5 V supply, it will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. Use of this device with TTL may require the use of appropriate pull-up resistors to ensure a proper input logic high. This device is supplied in a 20-pin plastic dual in-line package. It can be operated over the ambient temperature range of -20°C to +85°C. Copper lead frames and low output saturation voltages allow all outputs to be operated at 25 mA continuously at ambient temperatures of up to 76°C. Data Sheet 26182.20B OUT 11 OUT 12 BLANKING SERIAL DATA OUT SERIAL DATA IN LOGIC SUPPLY CLOCK STROBE OUT 1 OUT 2 1 2 3 4 BLNK 20 19 18 17 OUT 10 OUT 9 OUT 8 OUT 7 LOAD SUPPLY GROUND OUT 6 OUT 5 OUT 4 OUT 3 REGISTER LATCHES 5 6 7 8 9 10 VDD CLK ST VBB 16 15 14 13 12 11 Dwg. PP-029-5 FEATURES ABSOLUTE MAXIMUM RATINGS at TA = 25°C Logic Supply Voltage,VDD ..................... 15 V Driver Supply Voltage, VBB ................... 60 V Continuous Output Current, IOUT ......................... -40 mA to +25 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA ................................. -20°C to +85°C Storage Temperature Range, TS ............................... -55°C to +150°C I I I I I I To 3.3 MHz Data Input Rate Low-Power CMOS Logic and Latches High-Speed Source Drivers Active Pull-Downs Low-Output Saturation Voltages Improved Replacement for SN75512B Always order by complete part number: UCN5811A . 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 FUNCTIONAL BLOCK DIAGRAM CLOCK SERIAL DATA IN V DD LOGIC SUPPLY SERIAL DATA OUT 2.0 SERIAL-PARALLEL SHIFT REGISTER 1.5 R θJ A = 55 °C /W STROBE LATCHES 1.0 BLANKING MOS BIPOLAR 0.5 VBB LOAD SUPPLY 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. GS-004-1 GROUND OUT 1 OUT 2 OUT 3 OUT N Dwg. FP-013-1 TYPICAL INPUT CIRCUIT VDD IN TIMING WAVESHAPES Dwg. EP-010-5 TYPICAL OUTPUT DRIVER Dwg. W-184 Dwg. W-182 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1985, 2000 Allegro MicroSystems, Inc. 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V (unless otherwise noted). Limits @ VDD = 5 V Characteristic Output Leakage Current Output Voltage Symbol ICEX VOUT(H) VOUT(L) Test Conditions VOUT = 0 V, TA = +70°C IOUT = -25 mA, VBB = 60 V IOUT = 1 mA IOUT = 2 mA Output Pull-Down Current IOUT(L) VOUT = 10 V to VBB VOUT = 40 V to VBB Input Voltage VIN(1) VIN(0) Input Current IIN(1) IIN(0) Serial Data Output Voltage VOUT(H) VOUT(L) Maximum Clock Frequency Supply Current fclk IDD(H) IDD(L) IBB(H) IBB(L) Blanking to Output Delay tPHL tPLH Output Fall Time Output Rise Time tf tr All Outputs High All Outputs Low Outputs High, No Load Outputs Low CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF VIN = VDD VIN = 0.8 V IOUT = -200 µA IOUT = 200 µA Mln. — 58 — — 2.5 — 3.5 -0.3 — — 4.5 — 3.3* — — — — — — — — Typ. -5.0 58.5 2.0 — 4.0 — — — 0.05 -0.05 4.7 200 — 3.0 2.5 7.5 10 300 250 1000 150 Max. -15 — 3.0 — — — 5.3 +0.8 0.5 -0.5 — 250 — 5.0 4.0 12 100 550 450 1250 170 Limits @ VDD = 12 V Min. — 58 — — — 15 10.5 -0.3 — — 11.7 — — — — — — — — — — Typ. -5.0 58.5 — 2.0 — 18 — — 0.1 -1.0 11.8 100 — 15 7.0 7.5 10 125 170 250 150 Max. -15 — — 3.0 — — 12.3 +0.8 1.0 -1.0 — 200 — 20 10 12 100 150 200 300 170 Units µA V V V mA mA V V µA µA V mV MHz mA mA mA µA ns ns ns ns Negative current is defined as coming out of (sourcing) the specified device pin. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. www.allegromicro.com 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS CLOCK DATA IN C STROBE BLANKING G OUTN Dwg. No. 12,649A A B D E F Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON, the information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. TIMING REQUIREMENTS (TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) .......................................................................... 75 ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................. 75 ns C. Minimum Data Pulse Width ................................................................ 150 ns D. Minimum Clock Pulse Width ............................................................... 150 ns E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns F. Minimum Strobe Pulse Width ............................................................. 100 ns G. Typical Time Between Strobe Activation and Output Transistion ......................................................................... 500 ns Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency. TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN X = Irrelevant Latch Contents I1 I2 I3 ... IN-1 IN Blanklng Output Contents I1 I2 I3 ... IN-1 IN R1 R2 R3 ... X PN X X ... L H R1 R2 R3 ... P1 P2 P3 ... X X X ... RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 L L L ... L L P1 P2 P3 ... L = Low Logic Level PN-1 PN H = High Logic Level P = Present State R = Previous State 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS UCN5811A Dimensions in Inches (controlling dimensions) 20 11 0.014 0.008 0.430 0.280 0.240 MAX 0.300 BSC 1 0.070 0.045 0.100 1.060 0.980 BSC 10 0.005 MIN 0.210 MAX 0.015 MIN 0.150 0.115 0.022 0.014 Dwg. MA-001-20 in NOTES: 1. 2. 3. 4. Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 18 devices. www.allegromicro.com 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS UCN5811A Dimensions in Millimeters (for reference only) 20 11 0.355 0.204 10.92 7.11 6.10 MAX 7.62 BSC 1 1.77 1.15 2.54 26.92 24.89 BSC 10 0.13 MIN 5.33 MAX 0.39 MIN 3.81 2.93 0.558 0.356 Dwg. MA-001-20 mm NOTES: 1. 2. 3. 4. Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 18 devices. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. www.allegromicro.com 5811 BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS POWER INTERFACE DRIVERS Function 8-Bit (saturated drivers) 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit (constant-current LED driver) 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) 10-Bit (active pull-downs) 12-Bit (active pull-downs) 16-Bit (constant-current LED driver) 20-Bit (active pull-downs) 32-Bit (active pull-downs) 32-Bit 32-Bit (saturated drivers) 4-Bit 8-Bit 8-Bit 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) Unipolar Stepper Motor Translator/Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 28-Line Decoder/Driver * † ‡ Output Ratings* SERIAL-INPUT LATCHED DRIVERS -120 mA 350 mA 350 mA 350 mA 350 mA 75 mA 250 mA 350 mA 100 mA -25 mA -25 mA 75 mA -25 mA -25 mA 100 mA 100 mA 350 mA -25 mA 350 mA 100 mA 250 mA 1.25 A 250 mA 350 mA 100 mA 450 mA 50 V‡ 50 V 80 V 50 V‡ 80 V‡ 17 V 50 V 50 V‡ 50 V 60 V 60 V 17 V 60 V 60 V 30 V 40 V 50 V‡ 60 V 50 V‡ 50 V 50 V 50 V‡ 50 V 50 V‡ 50 V 30 V 5895 5821 5822 5841 5842 6275 6595 6A595 6B595 5810-F and 6809/10 5811 and 6811 6276 5812-F and 6812 5818-F and 6818 5833 5832 5800 5815 5801 6B273 6273 5804 6259 6A259 6B259 6817 Part Number† PARALLEL-INPUT LATCHED DRIVERS SPECIAL-PURPOSE DEVICES Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. Complete part number includes additional characters to indicate operating temperature range and package style. Internal transient-suppression diodes included for inductive-load protection. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000