AS8650

Datasheet AS8650 High-efficient Power Management Device with High-speed CAN Interface 1 General Description The AS8650 is a companion IC which combines power management functions and a fully conforming high speed CAN Transceiver in one high performance analog device for automotive applications. The AS8650 is powered by the battery, provides 4 output voltage levels of which 3 outputs can be individually programmed in the range of 1.8V to 3.3V with a maximum current consumption up to 120mA at the LDO voltage regulator outputs. An integrated DCDC converter with a very high efficiency for the 5V output supplies the 3 voltage regulators and ensures a voltage stability of ± 2.5%. The combination of DCDC converter with low-drop-out voltage regulators makes the AS8650 suitable for all Automotive Control Units where power efficiency is a must. The AS8650 provides a high-speed CAN interface up to 1Mbps communication rate conforming to ISO 11898. The AS8650 provides wake-up via remote wake-up at CAN bus lines and a local wake pin. The watchdog unit provides three different timing functions: start-up, window- and time-out watchdog; configurable via the SPI and I2C interface. Voltage monitoring is implemented for the battery supply, DCDC output and the 3 LDO regulator outputs. Undervoltage will be signalled on the INTN pin to the microcontroller. All diagnostics and status flags can be accessed with the SPI interface. The product is available in a 36-pin QFN (6x6x0.9) package. 2 Key Features DCDC converter for 5V output with very high efficiency 2 programmable voltage regulators in the range of 1.8V to 3.3V High-speed CAN interface (ISO 11898) with remote wake-up Comprehensive voltage monitoring Configurable watchdog functions for start-up, operation, and standby Automatic thermal shutdown protection Excellent EMC performance with outstanding switching technology for the DCDC converter Ambient temperature range from -40°C to +105°C in maximum load conditions Lead-free 36-pin QFN (6x6x0.9) package 3 Applications The AS8650 provides high efficient and flexible power supply together with state-of-the-art high speed CAN Interface for automotive control units.The device is pin compatible with AS8550 (LIN interface) in order to change from CAN to LIN easy. Figure 1. AS8650 Block Diagram VSUP I2C_EN CSSPI SCLKI2C / SCLKSPI SDAI2C / SDISPI SDOSPI INTN Configurable Voltage Regulator High-speed CAN Transceiver Digital Logic Configurable Voltage Regulator Configurable Voltage Regulator I2C SPI DC / DC Converter 5V AS8650 FB LX V5V_LDO1 V5V_LDO2 V5V_LDO3 VREG CANH SPLIT CANL RxD TxD VREG RESET Watchdog VREG WAKE GND www.austriamicrosystems.com/AS8650 Revision 1.0 1 - 46 AS8650 Datasheet - C o n t e n t s Contents 1 General Description .................................................................................................................................................................. 2 Key Features............................................................................................................................................................................. 3 Applications............................................................................................................................................................................... 4 Pin Assignments ....................................................................................................................................................................... 4.1 Pin Descriptions.................................................................................................................................................................................... 1 1 1 4 4 5 Absolute Maximum Ratings ...................................................................................................................................................... 6 Electrical Characteristics........................................................................................................................................................... 6.1 Electrical System Specification............................................................................................................................................................. 6.2 DCDC Converter .................................................................................................................................................................................. 6.3 Low Drop Out Regulators ..................................................................................................................................................................... 6.4 CAN Transceiver ................................................................................................................................................................................ 6.5 Undervoltage Detection ...................................................................................................................................................................... 6 7 8 8 9 10 13 6.4.1 Timing Diagrams........................................................................................................................................................................ 12 7 Detailed Description................................................................................................................................................................ 7.1 Operating Modes and States.............................................................................................................................................................. 7.1.1 7.1.2 7.1.3 7.1.4 Normal Mode ............................................................................................................................................................................. Receive-only Mode .................................................................................................................................................................... Standby Mode............................................................................................................................................................................ Sleep Mode................................................................................................................................................................................ 14 14 14 14 14 14 14 17 17 19 19 19 19 19 19 20 21 21 21 21 21 21 22 23 23 23 23 23 23 23 23 23 7.2 Power Management Strategy ............................................................................................................................................................. 7.3 State Diagram..................................................................................................................................................................................... 7.4 Initialization Sequence........................................................................................................................................................................ 7.5 DCDC Converter ................................................................................................................................................................................ 7.6 Voltage Regulator LDO1..................................................................................................................................................................... 7.7 Voltage Regulator LDO2..................................................................................................................................................................... 7.8 Voltage Regulator LDO3..................................................................................................................................................................... 7.9 Over-Temperature Monitor ................................................................................................................................................................. 7.10 Undervoltage Reset.......................................................................................................................................................................... 7.11 Reset Block...................................................................................................................................................................................... 7.12 CAN Transceiver .............................................................................................................................................................................. 7.12.1 7.12.2 7.12.3 7.12.4 7.12.5 7.12.6 7.13.1 7.13.2 7.13.3 7.13.4 7.13.5 7.13.6 7.13.7 7.13.8 BUS Driver............................................................................................................................................................................... Normal Receiver ...................................................................................................................................................................... Low Power Receiver................................................................................................................................................................ Operating Modes ..................................................................................................................................................................... Local Wake-up Event............................................................................................................................................................... Remote Wake-up..................................................................................................................................................................... VSUP_UV_flag ........................................................................................................................................................................ VSUP_POK_flag...................................................................................................................................................................... V5V_UV_flag ........................................................................................................................................................................... V5V_POK_flag......................................................................................................................................................................... VLDO2_UV_flag ...................................................................................................................................................................... VLDO2_POK_flag.................................................................................................................................................................... VLDO3_UV_flag ...................................................................................................................................................................... VLDO3_POK_flag.................................................................................................................................................................... 7.13 Internal Flags.................................................................................................................................................................................... www.austriamicrosystems.com/AS8650 Revision 1.0 2 - 46 AS8650 Datasheet - C o n t e n t s 7.13.9 BUS Wake_up Flag ................................................................................................................................................................. 7.13.10 Local Wake_up Flag .............................................................................................................................................................. 7.13.11 OVT_Warning Flag ................................................................................................................................................................ 7.13.12 OVT_Recover Flag ................................................................................................................................................................ 7.13.13 Bus Failure Flags................................................................................................................................................................... 7.13.14 Local Failure Flags ................................................................................................................................................................ 7.14 Watchdog (WD) ................................................................................................................................................................................ 23 24 24 24 24 24 25 7.14.1 Start-up Watchdog Behavior.................................................................................................................................................... 25 7.14.2 Window Watchdog Behavior.................................................................................................................................................... 25 7.14.3 Time-out Watchdog Behavior .................................................................................................................................................. 26 7.15 Interrupt Generation ......................................................................................................................................................................... 7.16 Status Registers ............................................................................................................................................................................... 26 27 8 Application Information ........................................................................................................................................................... 8.1 Serial Peripheral Interface .................................................................................................................................................................. 28 28 8.1.1 SPI Write Operation................................................................................................................................................................... 29 8.1.2 SPI Read Operation................................................................................................................................................................... 30 8.1.3 SPI Timing Diagram................................................................................................................................................................... 31 8.2 Inter-Integrated Circuit (I2C) Interface................................................................................................................................................ 32 8.2.1 I2C Write Operation ................................................................................................................................................................... 32 8.2.2 I2C Read Operation................................................................................................................................................................... 33 8.3 Digital Timing Specification ................................................................................................................................................................ 8.4 Register Space ................................................................................................................................................................................... 34 38 8.3.1 System Specification and Timings............................................................................................................................................. 37 9 Package Drawings and Markings ........................................................................................................................................... 10 Ordering Information............................................................................................................................................................. 43 45 www.austriamicrosystems.com/AS8650 Revision 1.0 3 - 46 AS8650 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments Figure 2. Pin Assignments (Top View) V5V_LDO3 V5V_LDO2 V5V_LDO1 29 36 35 34 33 32 31 30 VLDO3 28 27 FB LX LX LX VSUP VSUP VSUP GND_DCDC GND WAKE CANH CANL GND_CAN 1 VLDO3FB VLDO2 VLDO2FB VLDO1FB VLDO1 RESERVED RESERVED RESERVED RESET 2 26 3 AS8650 QFN 6x6x0.9 25 4 24 5 23 6 GND (Exposed pad) 22 7 21 8 20 9 10 11 12 13 14 15 16 17 18 19 SPLIT I2C_EN SDAI2C / SDISPI SDOSPI INTN RxD SCLKI2C (SCLKSPI) 4.1 Pin Descriptions Table 1. Pin Descriptions Pin 1, 2, 3 4 5 6 7 8 9 10 Pin Name VSUP GND_DCDC GND WAKE CANH CANL GND_CAN SPLIT Power Supply Input Local wake request (high-voltage input) Analog Input / Output high-voltage High level CAN bus line Low level CAN bus line Power supply Analog Input / Output high-voltage Common-mode stabilization output Power Supply Input Power Supply Pin Type Description www.austriamicrosystems.com/AS8650 Revision 1.0 CSSPI TxD 4 - 46 AS8650 Datasheet - P i n A s s i g n m e n t s Table 1. Pin Descriptions Pin 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33, 34, 35 0 VLDO1 VLDO1FB VLDO2 VLDO2FB VLDO3FB VLDO3 V5V_LDO1 V5V_LDO3 V5V_LDO2 FB (DCDC) LX (DCDC) GND Analog Input Power Supply Input Power Supply Input Reserved Analog Input / Output Power Supply Input Pin with Digital / Analog Input / Open-Drain-Output Power Supply Input Pin with Digital / Analog Input / Open-Drain-Output Regulated voltage output Regulated voltage feedback Regulated voltage output Regulated voltage feedback Regulated voltage feedback Regulated voltage output Step-down converter 5V output, supply for LDO1 Step-down converter 5V output, supply for LDO3 Step-down converter 5V output, supply for LDO2 DCDC output voltage feedback DCDC output Exposed pad (GND) Pin Name I2C_EN SDAI2C / SDISPI SDOSPI SCLKI2C / SCLKSPI CSSPI RxD INTN TxD RESET Pin Type Digital Input Digital Input/Output / Digital Input Digital Output Digital Input Digital input with pull-up Digital output with pull-up Digital Output Digital input with pull-up Digital Output Pin with Digital / Analog Input / Open-Drain-Output Reserved Description I2C/SPI select signal (High = I2C, Low = SPI) Unidirectional for SPI, Bidirectional for I2C SPI data out Serial clock (Multiplexed for I2C and SPI) unidirectional SPI chip select CAN Transceiver receive signal Active low interrupt to µC. Generated if status/ diagnostic is updated. CAN Transceiver transmit signal Digital Output referenced to VLDO1, active low www.austriamicrosystems.com/AS8650 Revision 1.0 5 - 46 AS8650 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 7 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Electrical Parameters Voltage at positive supply pin (VVSUP) Voltage at pin V5V_LDO1, V5V_LDO2, V5V_LDO3, VLDO1, VLDO2, VLDO3, FB, VLDO1FB, VLDO2FB, VLDO3FB Voltage at pin CANH, CANL, SPLIT Voltage at pin LX, WAKE Voltage at pin RESET, INTN, RxD, TxD, CS, SCLK, SDO, SDA/SDI, I2C_EN Input Supply slew-rate (Vsup_slew) Electrostatic Discharge Electrostatic discharge voltage AEC-Q100-002 human body model standard (ESD) Latch-Up Immunity Continuous Power Dissipation Maximum power dissipation (Ptot) Temperature Ranges and Storage Conditions Junction temperature (TJ) Storage temperature (Tstg) Thermal resistance MLF package (Rthj_36) -50 170 +125 30 ºC ºC ºC/W SEMI G42-88 The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). Represents a maximum floor life time of 168h 1.2 W ±2 ±4 ±8 -100 +100 mA kV All pins except VSUP, GND, CANH, CANL, WAKE, SPLIT VSUP, GND, WAKE, SPLIT CANH, CANL AEC-Q100-004 -0.3 -0.3 -40 -0.3 -0.3 40 7 +40 VVSUP + 0.3 4.5 1 V V V V V V/µs Input power supply ramp rate 1 Min Max Units Notes Package body temperature (TBODY) 260 ºC Moisture Sensitivity Level 3 1. All voltages mentioned above are referred with respect to ground reference voltage VGND. www.austriamicrosystems.com/AS8650 Revision 1.0 6 - 46 AS8650 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics Table 3. Electrical Characteristics Symbol Operating Conditions VSUP GND TAMB Positive supply voltage Ground Ambient temperature Normal operating condition In reference to all the voltages Junction temperature (TJ) ≤ 150ºC (at full-load) VSUP = 6V, LDOs at full load, DCDC load = 390mA, CAN dominant Isupp Supply current, normal mode VSUP = 18V, LDOs at full load, DCDC load = 390mA, CAN dominant, not production tested. VSUP = 16V, LDOs at full load, CAN dominant CS VtVt+ Ilil_cs SDO VOH VOL IO SDA / SDI VIH VIL VOL SCLK VIH VIL RESET, INTN VOH VOL IO TxD VIH VIL IO High level input voltage Low level input voltage Output drive current VSUP ≥ 6V 2.0 0.8 1 V V mA High level output voltage Low level output voltage Output drive current VSUP ≥ 6V 2.5 0.4 4 V V mA High level input voltage Low level input voltage Open-drain, external 500Ω pull-up 0.7* VLDO1 0.3* VLDO1 V V High level input voltage Low level input voltage Low level output voltage 0.7* VLDO1 0.3* VLDO1 0.4 V V V High level output voltage Low level output voltage Output drive current VSUP ≥ 6V 2.5 0.4 4 V V mA Negative-Going Threshold Positive-Going Threshold Pull up current VLDO1 = 3.3V In CS pad, Pulled up to VLDO1 1.12 1.77 -60 1.52 2.23 -15 V V µA 6 0 -40 425 mA 105 18 V V ºC Parameter Conditions Min Typ Max Units 150 170 www.austriamicrosystems.com/AS8650 Revision 1.0 7 - 46 AS8650 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics Symbol Ilil RxD VOH VOL IO Ilil High level output voltage Low level output voltage Output drive current Pull-up current VSUP ≥ 6V TxD pulled up to VLDO1 with control RxD pulled up to VLDO1 -60 2.5 0.4 1 -15 V V mA µA Parameter Pull-up current Conditions TxD pulled up to VLDO1 with control RxD pulled up to VLDO1 Min -60 Typ Max -15 Units µA 6.1 Electrical System Specification -40°C < TJ < 150°C Table 4. Electrical System Specification Symbol IDDnom IDDrecv IDDstby IDDsleep Parameter Current consumption normal mode Current consumption receive-only mode Current consumption standby mode Current consumption sleep mode Conditions No load, VSUP = 12V, CAN recessive No load, VSUP = 12V, CAN recessive No load, VSUP = 12V No load, VSUP = 12V Min Typ 3.5 1 135 75 Max 6 2 270 150 Units mA mA µA µA 6.2 DCDC Converter -40°C < TJ < 150°C; all voltages are with respect to ground, normal operating mode, unless otherwise mentioned. Table 5. DCDC Converter Symbol VSUP V5V ILXS IV5V RON VFB Lireg_dc Parameter Battery Voltage Range Output Voltage LX current limit DCDC output current LX switch on-resistance Reference Voltage for FB Line regulation Step from VIN = 6V to VIN2 = 18V, ILOAD = 100mA Lireg = 100*(VOUT1-VOUT2) / [VOUT2*(VIN1-VIN2)] ILOAD step from 90mA to 10mA VSUP = 12V Loreg = 100*(V_90mA-V_10mA) / V_90mA (bondwire resistance included) 4.75 -0.1 0.8 5 For inductor 22µH and capacitor 100µF Conditions Min 6 4.75 0.8 Typ 12 5 1 Max 18 5.25 1.25 500 1 5.25 +0.1 Units V V A mA Ω V %/V Loreg_dc LX_ind V5V_cer1 V5V_esr1 V5V_cer2 V5V_esr2 Csup Csup_esr Load regulation Output inductor Output ceramic capacitor 1 ESR of ceramic capacitor 1 Output ceramic capacitor 2 ESR of ceramic capacitor 2 Input capacitor (ceramic) -0.9 10 10 0 +0.9 22 100 0.05 220 0.01 100 1 % µH µF Ω nF Ω µF Ω X7R type For EMC suppression 100 22 www.austriamicrosystems.com/AS8650 Revision 1.0 8 - 46 AS8650 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.3 Low Drop Out Regulators -40°C < Tj < 150°C; all voltages are with respect to ground, normal operating mode, unless otherwise mentioned. The LDO block is a linear voltage regulator, which provides a regulated (band-gap stabilized) output voltage from the DCDC converter output voltage (V5V). Table 6. VLDO1 Block Specifications Symbol V5V IOUTLDO1 VLDO1 ICC_SH dVLDO1 LOREG_NM tldo CL2 ESR2 CL1 ESR1 1. Please note that the VLDO1 is not programmable. Table 7. VLDO2 Block Specifications Symbol V5V IOUTLDO2 VLDO2 ICC_SH dVLDO2 LOREG_NM tldo CL2 ESR2 CL1 ESR1 1. 3.3V to 1.8V output. Output Capacitor (Ceramic) Parameter Input Voltage Range Output current Output Voltage Range Output Short Circuit Current Line Regulation Load Regulation Start-up time Guaranteed by design. Not production tested. VOUT (typ) depends on the trim code as in OTP register mapping. Default code gives 2.8V Normal mode ΔVLDO2/ΔV5V (static) for the input range, ILOAD = 100mA ΔVLDO2 (for 120mA > ILOAD > 1mA) Guaranteed by design (includes start-up time of DCDC converter) X7R type X7R type 2 0.02 100 -8 -0.15 Conditions Min 4.75 0 0.975* VOUT VOUT Typ 5 Max 5.25 120 1.025* VOUT 300 8 +0.15 80 5 0.1 220 0.01 Units V mA V mA mV/V mV/mA ms µF Ω nF Ω 1 1 Parameter Input Voltage Range Output current Output Voltage Range Output Short Circuit Current Line Regulation Load Regulation Start-up time Conditions Guaranteed by design. Not production tested. Normal mode ΔVLDO1/ΔV5V (static) for the input range, ILOAD = 100mA ΔVLDO1 (for 100mA > ILOAD > 1mA), V5V = 5V Guaranteed by design (includes start-up time of DCDC converter) X7R type Min 4.75 0 3.217 Typ 5 Max 5.25 100 Units V mA V mA mV/V mV/mA ms µF Ω nF Ω 3.3 3.383 300 -8 -0.15 8 +0.15 80 2 0.02 100 5 0.1 220 0.01 Output Capacitor (Ceramic) X7R type www.austriamicrosystems.com/AS8650 Revision 1.0 9 - 46 AS8650 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 8. VLDO3 Block Specifications Symbol V5V IOUTLDO3 VLDO3 ICC_SH dVLDO3 LOREG_NM tldo CL2 ESR2 CL1 ESR1 1. 3.3V to 1.8V output. Parameter Input Voltage Range Output current Output Voltage Range Output Short Circuit Current Line Regulation Load Regulation Start-up time Output Capacitor (Ceramic) Output Capacitor (Ceramic) Guaranteed by design. Not production tested. VOUT (typ) depends on the trim code as in OTP register mapping. Default code gives 1.8V Normal mode ΔVLDO3/ΔV5V (static) for the input range, ILOAD = 100mA ΔVLDO3 (for 100mA > ILOAD > 1mA) Guaranteed by design (includes start-up time of DCDC converter) X7R type X7R type 2 0.02 100 -8 -0.15 Conditions Min 4.75 0 0.975* VOUT VOUT Typ 5 Max 5.25 100 1.025* VOUT 300 8 +0.15 80 5 0.1 220 0.01 Units V mA V mA mV/V mV/mA ms µF Ω nF Ω 1 6.4 CAN Transceiver 6V < VSUP < 18V; -40°C < Tj < 150ºC; all voltages are with respect to ground; 4.75V < V5V_LDO1 < 5.25V; RL=60Ω. Table 9. DC Electrical Characteristics Symbol Driver CANH_dom CANL_dom VO_dom_m Dominant Output Voltage Matching Dominant Output Voltage V5V_LDO1-V_CANH-V_CANL Differential output voltage V_CANH-V_CANL Recessive output voltage V_CANH, V_CANL Short circuit output current Recessive output current 45Ω < RL < 60Ω, V_TxD = 0V (dominant) No load; V_TxD = VLDO1 (recessive) V_TxD = VLDO1; No bus load, Normal mode No bus load, Stand-by mode V_TxD = 0V, V_CANH = 0V V_TxD = 0V, V_CANL = 40V -27V < V_CAN < 40V -12V < V_CANH < 12V -12V < V_CANL < 12V Receive only mode (CAN receiver) -12V < V_CANH < 12V -12V < V_CANL < 12V Stand-by mode (low-power receiver) V_TxD = 0V 3 0.5 -0.1 1.5 -50 2 -0.1 -160 +50 -2.5 4.25 1.75 0.15 3 50 3 0.1 -50 +160 +2.5 V V V V mV V V mA mA mA Parameter Conditions Min Typ Max Units VO_diff VO_rec IO_short IO_rec Receiver 0.5 0.9 V V_RxD_th Differential receiver threshold voltage 0.4 1.15 V www.austriamicrosystems.com/AS8650 Revision 1.0 10 - 46 AS8650 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 9. DC Electrical Characteristics Symbol V_RxD_hys I_RxD_LEAK R_IN_cm R_IN_cm_m R_IN_diff VO_SPLIT Parameter Differential receiver hysteresis voltage Input leakage current Common mode input resistance Common mode input resistance matching Differential input resistance Output voltage on split pin Conditions -12V < V_CANH < 12V -12V < V_CANL < 12V Receive only mode (CAN receiver) V5V_LDO1 = 0V; V_CANH = V_CANL = 5V Tested in Receive only mode V_CANH = V_CANL (Tested in Receive only mode) Tested in Receive only mode Normal mode -500µA < I_SPLIT < 500µA Stand-by mode 0V < V_SPLIT < 35V (Not production tested) Stand-by mode -22V < V_SPLIT < 0 (Not production tested) Min 20 100 15 -3 25 0.3* V5V_LDO1 -5 Typ Max 130 250 35 +3 75 0.7* V5V_LDO1 +5 Units mV µA kΩ % kΩ V µA IL_SPLIT Leakage current on split pin -1 +1 mA Table 10. AC Electrical Characteristics Symbol t_TxD_BUS_on t_TxD_BUS_off t_BUS_on_RxD t_BUS_off_RxD t_TxD_RxD WAKE UP via BUS t_BUS_WR BUS Diagnostic t_OC_CANH t_LC_CANH t_OC_CANL t_LC_CANL Time to detect over current CANH Time to detect low current CANH Time to detect over current CANL Time to detect low current CANL V_TxD = 0V, V_CANH = 0V (Not production tested) V_TxD = 0V, V_CANH = 40V (Not production tested) V_TxD = 0V, V_CANL = 40V (Not production tested) V_TxD = 0V, V_CANL = 0V (Not production tested) 60 60 60 60 µs µs µs µs Dominant time for wake-up detection via bus 0.75 5 µs Parameter Delay TxD to bus dominant Delay TxD to bus recessive Delay bus dominant to RxD Delay bus recessive to RxD Propagation Delay TxD to RxD Conditions Min 10 10 15 20 40 Typ Max 110 140 115 160 255 Units ns ns ns ns ns Table 11. Temperature Limiter Symbol Tjshut Tjrecv Tjwarn Parameter Shut down temperature Recovery temperature Over-temperature warning flag set Conditions Junction temperature when IC shuts down Junction temperature below which state machine returns from shutdown/warning Junction temperature beyond which the warning flag is set Min 150 125 140 Typ 170 140 157 Max 185 155 175 Units ºC ºC ºC www.austriamicrosystems.com/AS8650 Revision 1.0 11 - 46 AS8650 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.4.1 Timing Diagrams Figure 3. Timing Diagram and Hysteresis of CAN Receiver TxD CANH_dom Vo_rec CANL_dom 0.9V Vin_diff 0.5V RxD t_TxD_BUS_on t_BUS_on_RxD t_TxD_RxD t_TxD_RxD t_TxD_BUS_off t_BUS_off_RxD 2.5V 0.4V V_RxD V_RxD_hys V_RxD_th (low) V_RxD_th (high) Vin_diff www.austriamicrosystems.com/AS8650 Revision 1.0 12 - 46 AS8650 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.5 Undervoltage Detection Table 12. Undervoltage Detection Symbol VSUP_POR VSUP_RESET VSUP_POKTH VSUP_UVTH V5V_POKTH V5V_UVTH VLDO_POKTH VLDO_UVTH trr tRes Parameter VSUP Power on Reset threshold on VSUP Power on Reset threshold off VSUP undervoltage threshold off VSUP undervoltage threshold on (CAN bus in recessive state) V5V undervoltage threshold off V5V undervoltage threshold on LDO undervoltage threshold off (VLDO1, VLDO2 and VLDO3) LDO undervoltage threshold on (VLDO1, VLDO2 and VLDO3) Spike filter on VLDO1 Reset delay time Conditions Rising edge of VSUP (Master Reset for Device) VSUP rising edge. (Brown out reset threshold) VSUP falling edge. (Brown out reset threshold) Rising edge of V5V Falling edge of V5V Percent value is with respect to LDO output. Rising edge of LDO Percent value is with respect to LDO output. Falling edge of LDO To remove disturbance Min 5.09 4.49 4.95 4.625 4.16 3.8 87 78 2 4 Typ 5.5 4.85 5.35 5.0 4.5 4.1 89 80 4 8 Max 5.91 5.21 5.75 5.375 4.84 4.4 91 82 8 12 Units V V V V V V % % µs ms www.austriamicrosystems.com/AS8650 Revision 1.0 13 - 46 AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description The AS8650 consists of the following components on chip: DCDC converter with 5V outputs that supplies the three LDO voltage regulators and the CAN Transceiver One voltage regulator for 3.3V output voltage and two programmable voltage regulators in the range of 3.3V to 1.8V CAN bus Transceiver according to ISO 11898 Integrated RESET unit with a power-on-reset delay and a programmable watchdog time 7.1 Operating Modes and States The AS8650 provides four main operating modes normal, receive only, standby, and sleep. In normal mode, the CAN Transceiver can be disabled in case of over-temperature condition. The detailed transition table for each mode is shown in the subsequent pages. 7.1.1 Normal Mode In normal mode DCDC converter, the three voltage regulators, BUS Transceiver, and Window Watchdog are turned on with full functionality. All the LDO regulators are capable of delivering maximum load current possible as per their respective ratings. The BUS Transceiver is capable of sending the TxD data from the microcontroller to the CANH at the maximum rate. 7.1.2 7.1.3 Receive-only Mode Standby Mode In this mode, the CAN transmitter is disabled. The CAN receiver, the three voltage regulators, and over-temperature monitor circuit are enabled. This is the mode after power up. The Standby mode is a functional low-power mode where the CAN Transceiver is disabled. The bus wake-up (low power receiver) circuit, LDO1, and over-temperature monitor circuit are enabled. Both LDO2 and LDO3 can be enabled or disabled (default state) using the host command. The AS8650 can enter normal mode, sleep mode or receive only mode through host command. 7.1.4 Sleep Mode Sleep mode is the current saving mode that is entered by host command or by over-temperature condition. The DCDC converter, the three voltage regulators, CAN Transceiver, the reset, and window watchdog unit are all switched off. The bus wake-up (low power receiver) circuit, oscillator, and over-temperature monitor circuit are active. The bus is in recessive state (high). The only wake-up possible is through remote wake-up (through the bus lines) or local wake up (through the WAKE pin) as described in the WAKE specification. In the case of entering sleep mode due to over-temperature condition (T > Tjshut), the device can come out of sleep only after the temperature falls back below the return temperature Tjrecv and any one of the wake up events mentioned above. 7.2 Power Management Strategy The detailed block diagram and the power management strategy are shown in Figure 4. Internal Regulator. This module is powered externally by the VSUP. All the critical modules that needs to be kept always on, work on this supply. Some of the important modules among them are Over-temperature monitor, Local Wake block, Internal Power-on Reset module, Internal Oscillator, complete mode-control unit, Undervoltage comparators of three external LDOs. DCDC Converter. This is the main supply regulator for all the internal blocks. A step-down hysteretic buck converter is used to generate 5V output from VSUP. This 5V output is then used to generate all the three LDOs. This high-efficiency step-down DCDC converter contains the following features: Current limited operation Thermal shutdown LDO1. This is the main I/O supply. This is generated internally from the 5V DCDC converter output and gives a regulated 3.3V output to powerup the external micro-controller. All the I/Os that interface with the micro-controller work on this supply. LDO2 and LDO3. These are two regulators that are generated from the 5V DCDC converter output. Both the LDOs can be programmed via I2C or SPI settings in the range from 3.3V to 1.8V. www.austriamicrosystems.com/AS8650 Revision 1.0 14 - 46 VSUP GND POR Pre-Reg 3.3V & 5.0V Osc DCDC Converter 5V FB LX por clk osc_en start done ldo1_en ldo1_uvb OTM otm_en loc_wake tx_en tx rx_en rx flags ldo2_en ldo2_uvb ldo3_en Mode Control / Reset Generation ldo3_uvb WAKE Local WAKE LDO2 (120mA) UV Comp V2P8 CANH SPLIT CANL CAN Transceiver LDO3 (100mA) UV Comp V1P8 Level Shifter Definer OTP Level Shifter Level Shifter Definer Level Shifter RESET INTN TxD RxD CSSPI SCLKI2C / SCLKSPI SDAI2C / SDISPI SDOSPI I2C_EN LDO1 Pre-reg DCDC 5V Window WatchDog Digital Interface AS8650 Definer Definer Definer Level Shifter Definer www.austriamicrosystems.com/AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n Revision 1.0 otm_160 otm_170 LDO1 (100mA) UV Comp V5V V3P3 15 - 46 Figure 4. Power Management Strategy AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n Table 13. Power Management Strategy for AS8650 Control States Analog Blocks DCDC Converter Oscillator Internal Regulator OTM LDO1 LDO2 LDO3 CAN TX CAN RX Low Power RX LOCAL WAKE SPLIT Generation Digital Blocks WWD Digital Interface Power-up ON ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF OFF Normal ON ON ON ON ON ON ON 2 2 RX Only ON ON ON ON ON ON ON 2 2 Standby ON ON ON ON ON OFF OFF 1 1 Sleep OFF ON ON ON OFF OFF OFF OFF OFF ON ON ON OFF OFF 1 ON ON OFF OFF ON ON ON OFF ON OFF OFF ON ON ON OFF OFF ON ON ON ON ON 1. Can be turned ON using Device configuration register 2. Can be turned OFF using Device Configuration register www.austriamicrosystems.com/AS8650 Revision 1.0 16 - 46 AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n 7.3 State Diagram Figure 5. State Machine Model VSUP_UV_flag = 1 OR V5V_UV_flag =1 à BUS transceiver disabled VSUP_UV_flag =1 OR V5V_UV_flag= 1 à BUS transceiver disabled Host command (go to ReceiveOnly) Normal Host command (go to Normal) Ho st c Receive Only TEMP>Tjwarn à BUS transmitter disabled BUS transmitter will be enabled on TEMP < Tjrecv om m Host command (go to ReceiveOnly) an d to Host command (go to Sleep) No rm a l) Ho st co st c Ho m om (go and p) lee to S mm an d( go t oS tan db y) Sleep TEMP > Tjshut à BUS wake disabled Host command (go to Sleep) Standby From any state star t up Power-up Power Off _P UP VS = ET ES _R OR =0 7.4 Initialization Sequence After this, DCDC converter is switched ON, on receiving PG (power good) signal from DCDC converter, LDO1 regulator is switched ON. If VLDO1 > VLDO1_POKTH threshold, VLDO1_RESET is generated. After this, active-low PORN_2_OTP is generated. The rising edge of PORN_2_OTP loads contents of fuse onto the OTP latch after load access time TLoad. The LOAD_OTP_IN_PREREG signal loads the content of OTP latch into the pre-regulator domain register. The Reset timeout is also started. The RESET signal is de-asserted after Reset timeout period TRes. After the RESET is high, startup watch dog will start. If microcontroller gives trigger within startup window the device enters into Standby mode. If microcontroller misses the trigger, RESET signal is generated and again Reset timeout will start. If microcontroller misses to give the startup watchdog trigger for 3 consecutive times, then the device enters into Sleep mode. On receiving Normal mode command from microcontroller, device turns ON the LDO2 and LDO3 regulators. When VLDO2 and VLDO3 reach their respective power-ok (POK) threshold values, device interrupts microcontroller. The circuit is designed such that the state machine initializes correctly even for very slow ramp rates on VSUP of the order of 0.5V/min. www.austriamicrosystems.com/AS8650 Revision 1.0 V3 P3 _R ES 3P OR O timeo ut wat R c hd og tim eou t V3P 3 V 3p TEMP< Tjrecv AND BUS Wake OR Local Wake _RE SET == 1 Rese & t tim e ou t Host command (go to Standby) (g o Normal OR Receive_only OR Standby state ET = =0 17 - 46 AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n The power initialization sequence diagram is shown in Figure 6. After activating the power supply on VSUP pin, the VSUP_POR_RESET flag becomes inactive (high) while the voltage exceeds the VSUP_POR threshold. The DCDC output voltage V5V exceeds the V5V_POKTH thresholds after the DCDC settling time and the first voltage regulator (LDO1) will be activated with the V5V_POK set. If the voltage output at LDO1 (set to 2.5V on power-up) reaches the VLDO1_POKTH threshold, the PORN_2_OTP flag is set and OTP register setting for the LDO1 is read. Consequently the output voltage will be regulated to the actual OTP settings. The initialization phase of the device is terminated after the preset output voltage level threshold is exceeded and the reset timeout is expired. After entering Stand-by mode the host controller can switch the device in any operation mode through the I2C or SPI interface. Figure 6. Initialization Sequence VSUP_POR VSUP VSUP_POR_RESET V5V_POKTH V5V Tdcdc = DCDC settling time V5V_POK VLDO1_POKTH VLDO1 VLDO1_POKTH Tldo = LDO settling time VLDO1_RESET PORN_2_OTP LOAD_OTP_IN_ PREREG 6 Cycles of RC- Oscillator RESET Tres = Reset Timeout DEVICE STATE INITIALIZATION STARTUP WATCHDOG STANDBY MODE VLDO2_POKTH NORMAL MODE VLDO2 VLDO3_POKTH VLDO3 INTN Tldo = LDO settling time www.austriamicrosystems.com/AS8650 Revision 1.0 18 - 46 AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n 7.5 DCDC Converter The high-efficiency, high-voltage, hysteretic step-down DCDC converter, operates in asynchronous mode and delivers 500mA of output load to drive the three internal LDOs and the CAN Transceiver. The low-power architecture extends hold-up time in battery-backed and critical applications where maximum up-time over a wide input supply voltage range is needed, while still providing for high efficiencies of up to 90% during peak current demands. 7.6 Voltage Regulator LDO1 The stability of the voltage output is below ±2.5% over the full input range and temperature for load current up to 100 mA at 3.3V. Power Input to this LDO is the V5V_LDO1 pin. This LDO is activated in Normal, Receive only or Standby mode. It is switched OFF in Sleep mode. 7.7 Voltage Regulator LDO2 The stability of the voltage output is below ±2.5% over input range and temperature for load current up to 100 mA. The voltage regulator is programmable between 3.3V and 1.8V via I2C or SPI interface. Power Input to this LDO is the V5V_LDO2 pin. LDO2 is activated in Normal and Receive Only mode. 7.8 Voltage Regulator LDO3 The stability of the voltage output is below ±2.5% over input range and temperature for load current up to 100 mA. The voltage regulator is programmable between 3.3V and 1.8V via I2C or SPI interface. Power Input to this LDO is the V5V_LDO3 pin. LDO3 is activated in Normal and Receive Only mode. 7.9 Over-Temperature Monitor In Normal mode, if the junction temperature reaches the over-temperature threshold Tjwarn, a warning flag is set in the diagnostic register which can be accessed via the I2C and the SPI interface and an interrupt is signalled on INTN pin. The CAN transmitter is disabled and the device remains in Normal mode. If the junction temperature falls below Tjrecv, the CAN transmitter is enabled. The warning flag is cleared in the diagnostic register and an interrupt is signalled at the INTN pin. If the junction temperature exceeds the over-temperature threshold Tjshut, the device enters sleep mode irrespective of the current mode and bus wake receiver (Low power receiver) is disabled. As soon as the temperature falls below Tjrecv, the bus wake receiver (Low power receiver) is switched on. 7.10 Undervoltage Reset Undervoltage on VSUP (Brown out Indication). If VSUP voltage falls below VSUP_UVTH threshold, the VSUP_UV_flag is set and an interrupt at INTN is generated. In this case the device enters into the Stand-by mode. The LDO1 voltage regulator remains activated. Two scenarios are possible at this stage: VSUP is recovering: If VSUP exceeds the VSUP_POKTH threshold, the VSUP_POK_flag is set and the device remains in Stand-by mode. VSUP is still falling: In this case the device continues to stay in Stand-by mode. If voltage falls below VSUP_RESET threshold, then the device enters Power-Off and the logic is reset. Undervoltage on V5V. If the V5V falls below V5V_UVTH threshold, the V5V_UV_flag is set. Once V5V returns to V5V_POKTH threshold value, V5V_POK_flag is set. In case a flag is set, an interrupt is generated at the INTN pin. If undervoltage on V5V occurs in Normal or Receive only modes then CAN Transceiver is disabled and the device remains in its operation mode. Undervoltage on LDO1. If the voltage level of LDO1 falls below the VLDO1_UVTH threshold value and device is not in Sleep mode, the device enters into power-up state while RESET signal is asserted and the voltage regulator is still active. Once the VLDO1_POKTH threshold is reached, RESET signal is de-asserted after reset timeout period and device enters into Standby mode. Undervoltage on LDO2. If the voltage level of the LDO2 falls below the VLDO2_UVTH threshold value a VLDO2_UV_flag is set. An indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on INTN pin. Once VLDO2 returns to VLDO2_POKTH threshold value, VLDO2_POK_flag is set. An indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on INTN pin. Undervoltage on LDO3. If the voltage level of the LDO3 falls below the VLDO3_UVTH threshold value a VLDO3_UV_flag is set. An indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on INTN pin. Once VLDO3 returns to VLDO3_POKTH threshold value, VLDO3_POK_flag is set. An indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on INTN pin. www.austriamicrosystems.com/AS8650 Revision 1.0 19 - 46 AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 7. Power-up and Undervoltage Sequence VSUP_POR VSUP_UVTH VSUP VSUP_POR_RESET VSUP_UV_flag VSUP_POK_flag VSUP Supply VLDO2 VSUP recovering VSUP still falling VSUP recovering VSUP still falling VLDO2_POK_flag VLDO2_UV_flag LDO2 Supply VLDO2_POKTH VSUP_POKTH VSUP_RESET VLDO2_UVTH V5V_POKTH V5V_UVTH VLDO3_POKTH VLDO3_UVTH V5V V5V_POK_flag V5V_UV_flag DCDC Supply VLDO3 VLDO3_POK_flag VLDO3_UV_flag LDO3 Supply VLDO1_POKTH VLDO1_UVTH VLDO1 VLDO1_RESET LDO1 Supply 7.11 Reset Block The reset block generates an external RESET signal to reset the microcontroller and all other external circuits. The reset functionality is explained in Figure 8. The reset block consists of a digital buffer at the output. The RESET signal is affected by VLDO1_RESET (during overload, reset on VLDO1) and watch dog output. All conditions which cause a drop of the VLDO1 voltage will be detected from the low voltage reset unit which in-turn generates a reset signal. Figure 8. Reset Block Functional Waveform VVSUP_UV VSUP VLDO1_POR VLDO1_UV T>Tjshut TTrec(wake) >Tdom(wake) >Trec(wake) WAKE_remote_flag Remote wake detected 7.13 Internal Flags The AS8650 supports internal flags to indicate the failures in the system. If any of these flag is set an interrupt is generated on INTN pin. 7.13.1 VSUP_UV_flag This is a VSUP undervoltage flag. This flag is set when VSUP falls below the VSUP_UVTH threshold. When this flag is set the device enters into standby mode and BUS Transceiver is switched off to save power. When VSUP recovers and raises above VSUP_POKTH threshold the VSUP_UV_flag is reset. 7.13.2 VSUP_POK_flag This is a VSUP power ok flag. This indicates the VSUP recovery from undervoltage condition. When the VSUP rises above VSUP_POKTH threshold, this flag is set. This indicates the microcontroller that undervoltage condition on battery is cleared. 7.13.3 V5V_UV_flag This is a V5V undervoltage flag. This flag is set when V5V falls below the V5V_UVTH threshold. When this flag is set the device enters into Standby mode and BUS Transceiver is switched off to save power. When V5V recovers and raises above V5V_POKTH threshold the V5V_UV_flag is reset. 7.13.4 V5V_POK_flag This is a V5V power ok flag. This indicates the V5V recovery from undervoltage condition. When the V5V rises above V5V_POKTH threshold, this flag is set. This indicates the microcontroller that undervoltage condition on DCDC converter is cleared. 7.13.5 VLDO2_UV_flag This is a VLDO2 undervoltage flag. This flag is set when VLDO2 falls below the VLDO2_UVTH threshold. When VLDO2 recovers and raises above VLDO2_POKTH threshold the VLDO2_UV_flag is reset. 7.13.6 VLDO2_POK_flag This is a VLDO2 power ok flag. This indicates the VLDO2 recovery from undervoltage condition. When the VLDO2 rises above VLDO2_POKTH threshold this flag is set. This indicates the microcontroller that undervoltage condition on LDO2 is cleared. 7.13.7 VLDO3_UV_flag This is a VLDO3 undervoltage flag. This flag is set when VLDO3 falls below the VLDO3_UVTH threshold. When VLDO3 recovers and raises above VLDO3_POKTH threshold the VLDO3_UV_flag is reset. 7.13.8 VLDO3_POK_flag This is a VLDO3 power ok flag. This indicates the VLDO3 recovery from undervoltage condition. When the VLDO3 rises above VLDO3_POKTH threshold this flag is set. This indicates the microcontroller that undervoltage condition on LDO3 is cleared. 7.13.9 BUS Wake_up Flag The BUS Wake_up flag is set when the device detects a remote wake-up (BUS message) request. The remote wake-up request is detected when pattern shown in Figure 11 is found on wake_remote port of low power receiver. This indicates the microcontroller about the Bus wake event. www.austriamicrosystems.com/AS8650 Revision 1.0 23 - 46 AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n 7.13.10 Local Wake_up Flag The Local Wake_up flag is set when the device detects a local wake-up request on WAKE pin. A local wake-up request is detected when a logic state change on pin WAKE as shown in Figure 9. This indicates the microcontroller about the local wake event. 7.13.11 OVT_Warning Flag The OVT_Warning flag is set when temperature exceeds Tjwarn. This indicates the microcontroller about temperature exceeding warning levels. 7.13.12 OVT_Recover Flag The OVT_Recover flag is set when temperature falls back below Tjrecv. This indicates the microcontroller about temperature falling back below recovery levels. 7.13.13 Bus Failure Flags The bus failure flag is set if the CAN Transceiver detects a bus line short-circuit condition to VSUP, V5V_LDO1 or GND. Such possible conditions are indicated to microcontroller through these flags. All these flags are cleared on microcontroller read. If the fault condition still exist after microcontroller read, the particular flag is set again. The device still be working in the current state. The microcontroller takes appropriate action on reading of these flags. CANH_short_GND. This flag indicates Over Current condition on pin CANH. For example short to ground on pin CANH. When the output current on pin CANH exceeds the threshold OC_CANH_th then the output OC_CANH switches on high level after a filter time t_OC_CANH. CANH_short_VSUP. This flag indicates Low Current on pin CANH. For example open load or short to VSUP on pin CANH. When the output current on pin CANH falls below the threshold LC_CANH_th then the output LC_CANH switches on high level after a filter time t_LC_CANH. CANL_short_VSUP. This flag indicates Over Current on pin CANL. For example short to VSUP on pin CANL. When the output current on pin CANL exceeds the threshold OC_CANL_th, then the output OC_CANL switches on high level after a filter time t_OC_CANL. CANL_short_GND. This flag indicates Low Current on pin CANL. For example open load or short to ground on pin CANL. When the output current on pin CANL falls the threshold LC_CANL_th then the output LC_CANL switches on high level after a filter time t_LC_CANL. 7.13.14 Local Failure Flags The AS8650 prevents the system from four kinds of local failures without disturbing the BUS network. The four failures are TxD dominant clamping, RxD recessive clamping, TxD & RxD short, and bus dominant clamping. All these failures are indicated to microcontroller through flags. TxD_Dom_Clamp flag. A permanent LOW-level on pin TxD (due to a hardware or software application failure) would drive the BUS into a permanent dominant state, blocking BUS network communication. If pin TxD remains at a LOW level for longer than the TxD dominant time-out period TTxDC(dom), the device disables the transmitter of BUS Transceiver and TxD_Dom_Clamp flag is set. The device prevents such BUS network lock-up by disabling the transmitter of the Transceiver. The device will not change the functional state. The transmitter remains disabled until the local failure flag is cleared by host command. The flag is cleared on microcontroller read. RxD_Rec_Clamp flag. If pin RxD is shorted to VLDO1, the RxD pin is permanently clamped to recessive state. The BUS controller can not see the bus dominant state and start sending message thinking bus is idle. This disturbs the BUS. This RxD recessive clamping is detected by the device when BUS is at dominant state. On detection of this a failure RxD_Rec_Clamp flag is set and the transmitter is disabled. The flag is cleared on microcontroller read. The transmitter is enabled by host command. TxD_RxD_Short flag. The TxD_RxD short circuit would result in a dead-lock situation clamping the bus dominant. For example the Transceiver receives a dominant signal, RxD outputs a dominant level. Because of the short circuit, TxD reflects a dominant signal, retaining the dominant bus state. As a result TxD and the bus are clamped continuously dominant. The resulting effect is the same as for the continuously clamped dominant TxD signal. The TxD dominant timeout interrupts the deadlock situation by disabling the transmitter and the TxD_RxD short condition is differentiated. The bus becomes recessive again and TxD will be recessive if it is not driven by microcontroller. However, the failure scenario may still exist and with the next dominant signal on the bus the described procedure will start again. The device keeps the transmitter off after detection of TxD_RxD short fault and keeps updating this flag status. The microcontroller has to send 2 consecutive low pulses of duration 500ns with high period of 500ns in-between, in regular intervals to check short circuit recovery. This way a local TxD/RxD short circuit will not disturb the communication of the remaining bus system. BUS_Dom_Clamp flag. In the case of a short circuit from BUS to GND, the circuit for the BUS receiver senses dominant signal continuously even if there is no dominant transmitting node. The result may be a permanently dominant clamped bus. The device detects and reports a Bus Dominant Clamping situation to microcontroller through BUS_Dom_Clamp flag. If the receiver detects a bus dominant phase of longer than the bus dominant time out TBUSC(dom) BUS_Dom_Clamp flag is set. The flag is cleared on microcontroller read. www.austriamicrosystems.com/AS8650 Revision 1.0 24 - 46 AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n 7.14 Watchdog (WD) The WD has the following three monitory timing functions: Start-up watchdog: Gives opportunity to microcontroller to initialize the system. Window watchdog: Detects too early or too late microcontroller software response (loops and hangs). Time-out watchdog: Detects too very long response from microcontroller. 7.14.1 Start-up Watchdog Behavior Following any reset event the watchdog is used to monitor the ECU start-up procedure. Once the reset is released the watchdog counter will start. In case the watchdog is not properly served (a trigger from microcontroller) within TWD(init), another reset is forced on RESET pin and the monitoring procedure is restarted. The watchdog will give three opportunities to microcontroller to initialize the system. In case the watchdog is not properly served for three times, then the system enters into sleep mode. 7.14.2 Window Watchdog Behavior Whenever the device enters Normal mode, the Window mode of the watchdog is activated. This ensures that the microcontroller operates within the required speed; a too fast as well as a too slow operation will be detected. Watchdog triggering using the Window watchdog is illustrated in Figure 12. Figure 12. Window Watchdog Triggering Twwd_period Twd_no_trig NON-TRIGGER WINDOW Trigger restarts period SPI TRIGGER 50% Twd_trig TRIGGER WINDOW 100% Last Trigger Point Earliest Trigger Point Latest Trigger Point Trigger restarts period ( with new period if desired) NON-TRIGGER WINDOW New Period TRIGGER WINDOW 50% 100% SPI TRIGGER Unwanted Trigger (RESET generated, watchdog enter Start-up mode) Earliest Trigger Point Latest Trigger Point The AS8650 provides 8 different period timings. This timing can be changed through digital interface when desired. The period can be changed within any valid trigger window. Whenever the watchdog is triggered within the window time Twd_trig, the timer will be reset to start a new period. The watchdog window is defined to be between 50% and 100% of the nominal programmed watchdog period. Any too early (trigger in nontrigger window) or too late watchdog trigger will result an immediate system reset on RESET pin and watchdog entering Start-up watchdog mode. During undervoltage condition on VLDO1 the watchdog timer is disabled. www.austriamicrosystems.com/AS8650 Revision 1.0 25 - 46 AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n 7.14.3 Time-out Watchdog Behavior Whenever the AS8650 operates in Standby mode, active watchdog operates in Time-out watchdog mode. The watchdog has to be triggered within the actual programmed period time Twd_tout_period. The device provides 8 different possible periods for programming through digital interface. If the microcontroller fails to trigger the watchdog within trigger range then the system reset is generated on RESET pin and watchdog enters into Start-up watchdog mode. The time-out watchdog function is illustrated in Figure 13. Figure 13. Time-out Watchdog Triggering Twwd_period Twd_no_trig NON-TRIGGER WINDOW Trigger restarts period SPI TRIGGER 50% Twd_trig TRIGGER WINDOW 100% Last Trigger Point Earliest Trigger Point Latest Trigger Point Trigger restarts period ( with new period if desired) NON-TRIGGER WINDOW New Period TRIGGER WINDOW 50% 100% SPI TRIGGER Unwanted Trigger (RESET generated, watchdog enter Start-up mode) Earliest Trigger Point Latest Trigger Point 7.15 Interrupt Generation The pin INTN is an interrupt output. The INTN is forced LOW if one bit in the Interrupt register is set. The Interrupt register bits are cleared when the microcontroller clears the corresponding interrupt source register. The Interrupt register will also be cleared during a system reset (RESET LOW). As there are microcontrollers with level sensitive or edge sensitive interrupt port, pin INTN will be HIGH for at least TINTN after any of the interrupt source register is cleared. The Interrupt source register is cleared through write operation by overwriting 1 in to respective set bits position. Without further interrupts within TINTN pin INTN stays HIGH, otherwise it will revert to LOW again. The Interrupt register indicates the cause of an interrupt event. There are two levels of interrupt registers. First level register indicates the source region of interrupt and the second level register indicates the exact source of interrupt. With this structured interrupt, the microcontroller can trace source of interrupt by two read operations instead of polling for source of interrupt and also interrupts can be prioritized by microcontroller. The interrupt register structure is given in Figure 14. The register is cleared through digital interface write operation and upon any reset event. The hardware ensures no interrupt event is lost in case there is a new interrupt forced while reading the register. www.austriamicrosystems.com/AS8650 Revision 1.0 26 - 46 AS8650 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 14. Interrupt Register Structure Interrupt Source Registers CANH_Short_GND D1 CANL_Short_GND BUS_Dom_Clamp OVT_Recovery Local Wake_up OVT_Warning Reserved Reserved Reserved D7 D6 D5 D4 D3 D2 D1 D0 R R R R D3 D2 Wake_up D1 D0 D7 D6 D5 D4 D3 D2 D0 Interrupt Register R R R R R I3 Supply Related interrupt I2 wake-up, temperature and LDO timeout Interrupt I1 BUS and Local failure Interrupt 7.16 Status Registers The AS8650 has three Flag status registers and one RESET reason register. The Flag status registers indicate the current status of flags which are related to respective interrupt source registers. The Flag status registers are Bus status register, Temperature status register and Supply status register. The microprocessor can read these registers any time to check the status of device. The function of each flag is listed in register space description in subsequent sections. A RESET reason register indicates the reasons for RESET generation. Once the RESET pin goes low, the reason of this reset event is stored in RESET reason register. When RESET is released microprocessor can read this register to know the cause for last RESET signal. The RESET reason register is cleared once microprocessor reads this register through read operation. The bits functionality of this register is explained in register space description table. www.austriamicrosystems.com/AS8650 Revision 1.0 CANH_Short_VCC VSUP_POK_flag V1P8_POK_flag V2P8_POK_flag VSUP_UV_flag V5V_POK_flag V1P8_UV_flag V2P8_UV_flag V5V_UV_flag Reserved TxD_RxD_Short CANL_Short_VCC TxD_Dom_Clamp RxD_Rec_Clamp 27 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8 Application Information Device Interfaces. There are two ways to communicate with AS8650, one is 4 wires SPI and other is I2C. The selection between these two interfaces is through I2C_EN pin, as shown in Table 15. The pins CS, SCLK, SDI, and SDO are used for SPI interface. For I2C interface, SCLK is used as I2C Clock and SDA is used as I2C data line. Pins SCLKI2C / SCLKSPI and SDAI2C / SDISPI are multiplexed for both SPI and I2C interface. Since I2C_EN is a digital input pin, it has to be connected either to VLDO1 or GND. Note: I2C_EN should not be changed during a I2C/SPI Read/Write operation. Maximum switching delay between I2C and SPI is 8µs. Table 15. Device Interface Selection I2C_EN LOW HIGH Description Interface is 4-wire SPI Interface is I2C 8.1 Serial Peripheral Interface The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller. The SPI is configured for half-duplex data transfer. The SPI provides access to configuration registers, control registers, and diagnostic registers. The modes of the AS8650 are changed by writing required code in to mode control register through SPI. The SPI is also used to enter into test and OTP modes. This interface is only slave interface and only master can initiate SPI operation. The SPI can work on both the clock polarities. The polarity of the clock depends on the value of SCLK at the falling edge of CS. At the falling edge of CS if SCLK is “1” then the SPI is positive edge triggered and if the SCLK is “0” then SPI is negative edge triggered logic (see Table 16). Table 16. SPI Clock Polarity CS LOW LOW SCLK HIGH LOW Description Serial data is transferred at falling edge and sampled at rising edge of SCLK Serial data is transferred at rising edge and sampled at falling edge of SCLK The SPI protocol frame is divided in to two fields, the header field and the data field. The header field is 1 byte long containing a read/write command bit, 5 address bits and 2 reserved bits. The data field is of one data byte. The SPI frame format is shown in Figure 15. In the data phase MSB is sent first and LSB is sent last. Figure 15. SPI Frame Format Header Field 1 byte Data Field R/W 0 0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Bits 0– 1– WRITE READ 5 bits Address www.austriamicrosystems.com/AS8650 Revision 1.0 28 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.1.1 SPI Write Operation The SPI write operation begins with clock polarity selection at negative edge of CS, given in Table 16. Once the clock polarity is selected the SPI write command is given by providing ‘0’ in R/W bit of the header field in first sampling edge at SDI pin. The 5 bits address of register to be written is provided at SDI pin in next five consecutive sampling edges of SCLK. The first 2 bits in header fields are reserved and set to 0. The data to be written is followed by last bit of header field. With each sampling edge a bit is sampled starting from MSB to LSB. During complete SPI write operation the CS has to be low. The SPI write operation ends with positive edge of CS. The wave form for SPI write operation with single data byte is shown in Figure 16 and Figure 17. Figure 16. SPI Write Operation with Negative Clock Polarity and 1 Byte of Data Field CS SCLK SDI R1 R0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO Sampling Edge High Impedance Sate Figure 17. SPI Write Operation with Positive Clock Polarity and 1 Byte of Data Field CS SCLK R1 R0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDI SDO Sampling Edge High Impedance Sate www.austriamicrosystems.com/AS8650 Revision 1.0 29 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.1.2 SPI Read Operation The SPI read operation also begins with clock polarity selection at negative edge of CS, given in Table 16. Once the clock polarity is selected the SPI read command is given by providing ‘1’ in R/W bit of the header field in first sampling edge at SDI pin. The 5 bits address of register to be read is provided at SDI pin in next five consecutive sampling edges of SCLK. The first 2 bits in header fields are reserved and set to 0. The read data is followed by last bit of header field on SDO pin. With each sampling edge a bit can be read on SDO pin starting from MSB to LSB. During complete SPI read operation the CS has to be low. The SPI read operation ends with positive edge of CS. The wave form for SPI read operation with single data byte is shown in Figure 18 and Figure 19. Figure 18. SPI Read Operation with Negative Clock Polarity and 1 Byte of Data Field CS SCLK SDI R1 R0 A4 A3 A2 A1 A0 SDO D7 D6 D5 D4 D3 D2 D1 D0 Sampling Edge High Impedance Sate Figure 19. SPI Read Operation with Positive Clock Polarity and 1 Byte of Data Field CS SCLK SDI R1 R0 A4 A3 A2 A1 A0 SDO D7 D6 D5 D4 D3 D2 D1 D0 Sampling Edge High Impedance Sate www.austriamicrosystems.com/AS8650 Revision 1.0 30 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.1.3 SPI Timing Diagram Figure 20. Timing Diagram for SPI Write Operation CS ... tCPS tCPHD CLK polarity tSCLKH tSCLKL ... tCSH SCLK tDIS tDIH SDI DATAI DATAI ... DATAI SDO ... Figure 21. Timing Diagram for SPI Read Operation CS tSCLKH tSCLKL SCLK SDI DATAI DATAI tDOD tDOHZ SDO DATAO (D7 N ) DATAO (D0 0 ) www.austriamicrosystems.com/AS8650 Revision 1.0 31 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.2 Inter-Integrated Circuit (I2C) Interface I2C is a bidirectional 2 line bus interface with a serial data line (SDA) and a serial clock line (SCLK) for inter IC control. This interface is only slave interface and only microcontroller can start and stop the I2C operation. The overview of I2C protocol is shown in Figure 22. A HIGH to LOW transition on SDA line while SCLK is HIGH is the START (S) condition and a LOW to HIGH transition on SDA line while SCLK is HIGH is the STOP (P) condition, as shown in Figure 22. The START and STOP conditions should always be generated by the microcontroller. After the START condition, microcontroller has to make sure that data on SDA line must be stable during the HIGH period of SCLK. The data should only change when SCLK line is LOW. The Bus is busy after the START condition and it is free after the STOP condition. Any number of data bytes can be transmitted between START and STOP. Each byte is followed by an acknowledgement (which is the ninth bit). The data transmitter always receives an acknowledgement from the data receiver at end of each byte. The data transmitter releases the SDA bus at start of LOW period of 8th clock pulse and data receiver acknowledges by pulling the SDA to LOW during the LOW period of the SCLK. The Data receiver releases the bus at start of LOW period of 9th clock pulse of the SCLK and data transmitter gets the data bus.The AS8650 does not support general call address, START byte and high-speed mode. Figure 22. I2C Bus Protocol SDA MSB LSB 2 3 4 5 6 7 8 R/W 9 ACK 1 2 3 4 5 6 7 8 9 ACK 1 2 3 4 5 6 7 8 9 ACK S or P SCLK S 1 7 bit Slave address 8 bit Data 8 bit Data 8.2.1 I2C Write Operation After the START condition, microcontroller has to send, in the first byte, the 7-bit slave address and 0 into the R/W bit as shown in Figure 23. The microcontroller has to send the address of the register to be written in the second byte. The first 3 MSB bits are reserved and remaining 5 bits are used as address bits. The data is sent starting from MSB to LSB. The AS8650 sends acknowledgement on 9th clock pulse. In the next byte (3rd byte) microcontroller has to send the data to be written into addressed register. If it is a single write operation, after receiving the acknowledgment from AS8650, microcontroller has to send START or STOP condition, as shown in Figure 23. In case of auto increment write operation, microcontroller should not generate START or STOP condition after the third byte. If microcontroller continuously writes then address pointer rolls back to the starting register address after reaching the last register address. Data bytes coming from the microcontroller are written at the consecutive address locations, starting from the address sent in first data byte. After each data byte, direction of the bus line changes and AS8650 acknowledges by pulling the SDA line LOW. To terminate the write operation microcontroller has to generate STOP or repeated START condition. For details, see Figure 24. Figure 23. I2C Write Operation Slave address acknowledge from slave A register address A4 A3 A2 acknowledge from slave data to register acknowledge from slave SDA MSB LSB A1 A0 A A SCLK S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S or P R/W www.austriamicrosystems.com/AS8650 Revision 1.0 32 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 24. I2C Auto-increment Write Operation Slave address acknowledge From slave A register address A4 A3 A2 acknowledge From slave A1 A0 data to register acknowledge From slave A data to register + n SDA Master transmitter SCLK S A MSB 1 2 3 4 5 6 LSB 7 8 R/W 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S or P 8.2.2 I2C Read Operation After the START condition, microcontroller has to send, in the first byte, the 7-bit slave address and 0 into the R/W bit as shown in Figure 25. The microcontroller has to send the address of the register to be written in the second byte. The first 3 MSB bits are reserved and remaining 5 bits are used as address bits. The data is sent starting from MSB to LSB. After receiving the acknowledgement on the 9th clock pulse, microcontroller has to send on the SDA line repeated START or STOP, as shown in Figure 25. If microcontroller sends STOP then microcontroller has to send START again. If microcontroller sends repeated START then there is no need to generate START again. The microcontroller again has to send the 7-bit slave address and writes 1 into the R/W bit (8th bit). Now AS8650 sends data of the corresponding addressed register in the next eight clock cycles. In case of single read, microcontroller does not acknowledge on the 9th clock pulse and generates START or STOP condition after the ninth clock pulse. If it is an auto increment read operation, microcontroller acknowledges on the 9th clock pulse and AS8650 sends data from the consecutive address locations, see Figure 25. If microcontroller continuously reads then address pointer rolls back to the starting register address after reaching the last register address. In the data phase MSB is sent first and LSB is sent last. After each data byte, microcontroller has to send the acknowledgement. The microcontroller can terminate the auto read operation by not generating acknowledgement for the last byte that was sent by the AS8650 and generates STOP or repeated START condition after the 9th clock pulse. Figure 25. I2C Read Operation Slave address acknowledge from slave 0 A register address A4 acknowledge from slave A SDA MSB LSB 2 3 4 A3 A2 A1 A0 SCLK S 1 5 6 7 8 W 9 1 2 3 4 5 6 7 8 9 S or P acknowledge from slave Slave address Data byte acknowledge from master A SDA MSB LSB 2 3 4 1 A SCLK S 1 5 6 7 8 R 9 1 2 3 4 5 6 7 8 9 S or P www.austriamicrosystems.com/AS8650 Revision 1.0 33 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 26. I2C Auto-increment Read Operation Slave address acknowledge from slave 0 A acknowledge register address from slave A 4 A 3 A 2 A 1 A 0 SDA MSB LSB 2 3 4 5 6 A SCLK S 1 78 W 9 1 2 3 4 5 6 7 8 9 S or P No acknowledge from master Slave address acknowledge from slave 1 A Data byte 1 acknowledge from master A Data byte n Last data byte SDA MSB LSB 2 3 4 5 6 A SCLK S 1 78 R 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S or P 8.3 Digital Timing Specification SPI Protocol. Table 17. SPI Timing Parameters Symbol General BRSPI TSCLKH TSCLKL tDIS tDIH TCSH tDOD tDOHZ Bit rate Clock high time Clock low time Data in setup time Data in hold time CS hold time Data out delay Data out to high impedance delay Clock setup time (CLK polarity) Clock hold time (CLK polarity) Time for the SPI to release the SDO bus Setup time of SCLK with respect to CS falling edge Hold time of SCLK with respect to CS falling edge 500 500 20 10 40 80 80 1 Mbps ns ns ns ns ns ns ns Parameter Conditions Min Typ Max Units Write Operation Parameters Read Operation Parameters Timing Parameters for SCLK Polarity Identification tCPS tCPHD 20 20 ns ns www.austriamicrosystems.com/AS8650 Revision 1.0 34 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n I2C Protocol. Electrical characteristics of SDA & SCLK bus lines for F/S mode Table 18. I2C Electrical Parameters Symbol Parameter LOW level input voltage: Standard Min Max Min Fast Max Units VIL VIH Vhys VOL1 tof tSP Ii VLDO1related input levels VLDO1-related input levels Hysteresis of Schmitt trigger input LOW level output voltage (open drain or open collector) at 3mA sink current HIGH level input voltage: 0.3V*LDO1 0.7V*LDO1 n/a n/a 0.4 250 20 + 0.1Cb 0.7V*LDO1 0.05V*LDO1 0.3V*LDO1 V V V 0.4 250 V ns (lab tested only) ns µA Output fall time from VIHmin to VILmax with a bus capacitance from 10pF to 400pF Pulse width of spikes which must be suppressed by the input filter (see Footnote 2) (see Footnote 1) (see Footnote 2) n/a -10 n/a 10 -10 50 Input current of each I/O pin with an input voltage between 0.1VLDO1 and 0.9VLDO1 maximum Capacitance for each I/O pin (see Footnote 3) (see Footnote 3) 10 Ci 10 10 pF (guaranteed by design) 1. Cb = capacitance of one bus line in pF. 2. The maximum tf for the SDA and SCLK bus lines quoted in Table 19 (300ns) is longer than the specified maximum tof for the output stages (250ns). This allows for any series protection resistors to be connected between the SDA/SCLK pins and the SDA/SCLK bus lines without exceeding the maximum specified tf. 3. I/O pins of Fast-mode devices must not obstruct the SDA and SCLK lines if VLDO1 is switched off. Characteristics of the SDA and SCLK Bus Lines for F/S Mode I2C Bus. Table 19. I2C Timing Parameters Standard Symbol fSCLK tHD_STA tLOW tHIGH tSU_STA tSU_DAT tHD_DAT tr Parameter SCLK clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCLK clock HIGH period of the SCLK clock Set-up time for a repeated START condition Data set-up time Data hold-time Min 0 4 4.7 4.0 4.7 250 Max 100 Min 0 0.6 1.3 0.6 0.6 100 (see Footnote 2) Fast Max (see Footnote 1) 400 Units kHz µs µs µs µs ns 0 0 3450 900 (see Footnote 5) (see Footnote 3) (see Footnote 5) (see Footnote 3) 1000 20+ 0.1Cb (see Footnote 4) 300 ns ns Rise time of SDA and SCLK signals www.austriamicrosystems.com/AS8650 Revision 1.0 35 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Table 19. I2C Timing Parameters Standard Symbol Parameter Min 4.0 4.7 0.1V*LDO1 0.2V*LDO1 Max 300 400 Min 20+ 0.1Cb (see Footnote 4) 0.6 1.3 0.1V*LDO1 0.2V*LDO1 Fast Max (see Footnote 1) 300 400 Units tf tSU_STO tBUF Cb VnL VnH Fall time of SDA and SCLK signals Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) ns µs µs pF 1. All values referred to VIHmin and VIlmax levels (see Table 18). 2. A fast mode I2C bus device can be used in Standard mode I2C bus system, but the requirement tSU_DAT ≥ 250ns must then be met. This will automatically be the case if the device do not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDA line trmax. TSU_DAT = 1000 + 250 = 1250ns (according to standard mode I2C bus specification) before the SCLK line released. 3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 4. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times according toTable 18 allowed. 5. This device internally provides a hold time of at least 300ns for the SDA signal to bridge the undefined region of the falling edge of the SCLK. Figure 27. Definition of I2C Timing Parameters SDA tr tLOW tr tSU_DAT tf tHD_DAT tSP tf tBUF SCLK S tHIGH tSU_STA Sr tHD_STA tSU_STO P S www.austriamicrosystems.com/AS8650 Revision 1.0 36 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.3.1 System Specification and Timings Parameter Minimum dominant pulse for CAN wake-up detection (remote wake) Minimum recessive pulse for CAN wake-up detection (remote wake) Time between edge on WAKE pin to local wake detection Time between edge on WAKE pin to WAKE_LOCAL signal (Filter on WAKE pin) Remote wake detection time from the valid pattern detection INTN pin high time Local WAKE threshold input TxD dominant time-out period BUS dominant clamping time-out period Start-up Watchdog time-out (initialization time) Window watchdog Trigger window Twwd_period is defined in WWD register 0.375 7 2 600 600 1000 1000 4 1400 1400 0.75 24 Conditions Min Typ Max Units Table 20. System Timing Parameters Symbol Wake-up Timing Tdom(wake) Trec(wake) TL_wake TLW_filter TR_wake TINTN V_LWUTH TTxDC(dom) TBUSC(dom) 5 5 32 5 µs µs µs µs µs µs V µs µs Local Failure Related Timing Watchdog Timing & Timeouts TWD(init) Twd_trig 300 0.5 0.625 ms Twwd_period www.austriamicrosystems.com/AS8650 Revision 1.0 37 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.4 Register Space The AS8650 register space consists of configuration registers, control registers and diagnostic registers. All of these registers are accessible through SPI or I2C commands. Table 21. Configuration Registers Addr 0x00 0x01 0x02 Register Name Reserved Reserved WD Access Control Register 0000_0000 POR_VLDO1 D[7:0] D[7:6] R/W POR Value Bit Type Description Reserved Reserved 0101_10 WD Configuration Register access Enabled 10 Else WD Configuration Register access disabled 01 WD disabled Else WD enabled Time-out Watchdog mode Window period Twd_tout_period. (Accuracy of the timings is ±25%) 000 001 010 D[5:3] 011 100 101 0x03 WD Configuration Register 0000_1001 POR_VSUP R/W 110 111 80 ms 160 ms 320 ms 480 ms 800 ms 1000 ms 2000 ms 4000 ms Window Watchdog mode Window period Twwd_period (50% of above value is trigger window) 000 001 010 D[2:0] 011 100 101 110 111 D[7:1] 0x04 WD Trigger Register 0000_0000 POR_VLDO1 D[0] W 10 ms 40 ms 80 ms 120 ms 160 ms 240 ms 320 ms 400 ms Reserved Watchdog trigger bit. The microcontroller set this bit within the required window of watchdog timer. After this internal counter is reset and this bit is cleared internally. www.austriamicrosystems.com/AS8650 Revision 1.0 38 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Table 21. Configuration Registers Addr Register Name POR Value Bit D[7] D[6] D[5] D[4] 0110_1101 POR_VSUP D[3] D[2] D[1] D[0] D[7:6] 0 1 R/W 10 00 D[1:0] 01 10 11 D[7:3] 0 D[2] 1 0 0x07 Interrupt Register 0000_0000 POR_VSUP D[1] R 1 0 D[0] 1 No Interrupt Supply Related Interrupt. The source of interrupt is known by reading interrupt source register 3 No Interrupt Wake-up & temperature Related Interrupt. The source of interrupt is known by reading interrupt source register 2 No Interrupt BUS & Local Failure Related Interrupt. The source of interrupt is known by reading interrupt source register 1 R/W Type 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description LDO3 disable in Standby mode LDO3 enable in Standby mode LDO3 disable in Receive only mode LDO3 enable in Receive only mode LDO3 disable in Normal mode LDO3 enable in Normal mode LDO2 disable in Standby mode LDO2 enable in Standby mode LDO2 disable in Receive only mode LDO2 enable in Receive only mode LDO2 disable in Normal mode LDO2 enable in Normal mode DCDC disable in sleep mode DCDC enable in sleep mode BUS with low slew rate BUS with high slew rate Reserved Device state (Read-only values) D[5:4] 0x06 Mode Control Register 0000_0000 POR_VSUP Device in STAND BY Mode Device in NORMAL Mode Device in RECEIVE ONLY Mode Reserved STAND BY Mode NORMAL Mode RECEIVE ONLY Mode SLEEP Mode Reserved 0x05 Device Configuration Register D[3:2] www.austriamicrosystems.com/AS8650 Revision 1.0 39 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Table 21. Configuration Registers Addr Register Name POR Value Bit D[7] D[6] D[5] D[4] 0x08 Interrupt Source Register 1 0000_0000 POR_VSUP D[3] D[2] D[1] D[0] D[7:4] 0 D[3] 1 0 0x09 Interrupt Source Register 2 0000_0000 POR_VSUP D[2] 1 0 1 0 D[0] 1 No Interrupt Interrupt due to junction temperature falling back below Tjrecv No Interrupt Interrupt due to junction temperature exceeding Tjwarn No Interrupt Interrupt due to Local Wake up event on WAKE pin No Interrupt Interrupt due to Wake up by BUS message (remote wake) R/W Type 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 No Interrupt Interrupt due to BUS clamped to dominant No Interrupt Interrupt due to short TxD & RxD pins No Interrupt Interrupt due to RxD pin clamped to Recessive No Interrupt Interrupt due to TxD pin clamped to Dominant No Interrupt Interrupt due to CANL pin shorted to VCC No Interrupt Interrupt due to CANL pin shorted to GND No Interrupt Interrupt due to CANH pin shorted to GND No Interrupt Interrupt due to CANH pin shorted to VCC Reserved Description D[1] www.austriamicrosystems.com/AS8650 Revision 1.0 40 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Table 21. Configuration Registers Addr Register Name POR Value Bit D[7] D[6] D[5] D[4] 0x0A Interrupt Source Register 3 0000_0000 POR_VSUP D[3] D[2] D[1] D[0] 0x0B Reserved 0000_0000 POR_VSUP D[7:0] D[7] D[6] D[5] 0x0C BUS Status Register 0000_0000 POR_VSUP D[4] D[3] D[2] D[1] D[0] D[7:2] 0x0D Temperature Status Register 0000_0000 POR_VSUP D[1] D[0] D[7] D[6] D[5] 0x0E Supply status Register 1010_1010 POR_VSUP D[4] D[3] D[2] D[1] D[0] R R R R/W Type 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 No Interrupt Interrupt due to VLDO3_POK_flag set No Interrupt Interrupt due to VLDO3_UV_flag set No Interrupt Interrupt due to VLDO2_POK_flag set No Interrupt Interrupt due to VLDO2_UV_flag set No Interrupt Interrupt due to V5V_POK_flag set No Interrupt Interrupt due to V5V_UV_flag set No Interrupt Interrupt due to VSUP_POK_flag set No Interrupt Interrupt due to VSUP_UV_flag set Reserved BUS clamped to dominant TxD & RxD pins short RxD pin clamped to Recessive TxD pin clamped to Dominant CANL pin shorted to VCC CANL pin shorted to GND CANH pin shorted to GND CANH pin shorted to VCC Reserved OTM 140 Recovery flag OTM 160 Warning flag VLDO3_POK_flag VLDO3_UV_flag VLDO2_POK_flag VLDO2_UV_flag V5V_POK_flag V5V_UV_flag VSUP_POK_flag VSUP_UV_flag Description www.austriamicrosystems.com/AS8650 Revision 1.0 41 - 46 AS8650 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Table 21. Configuration Registers Addr Register Name POR Value Bit D[7] D[6] D[5] 0x0F RESET Reason Register 0000_0000 POR_VSUP D[4] D[3] D[2] D[1] D[0] 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 Backup Register 0000_0000 POR_VSUP D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] R/W R Type Description These bits are cleared on microcontroller read Reserved SLEEP Mode exit by Local Wake up on WAKE pin SLEEP Mode exit by Remote wake Window Watchdog failure Timeout Watchdog failure Start-up Watchdog failure Undervoltage on VLDO1 OTM Shutdown flag OTP_BITS[32:25] / MCU Backup Data OTP_BITS[40:33] / MCU Backup Data OTP_BITS[48:41] / MCU Backup Data OTP_BITS[56:49] / MCU Backup Data {1’b0,OTP_BITS[63:57]} / MCU Backup Data {2'd0, Slave address[6:1]}/MCU Backup Data 10bit_slave_address[3:0]/MCU Backup Data MCU Backup Data www.austriamicrosystems.com/AS8650 Revision 1.0 42 - 46 AS8650 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 9 Package Drawings and Markings The device is available in a 36-pin QFN (6x6x0.9) package. Figure 28. Drawings and Dimensions AS8650 YYWWIXX Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters, angle is in degrees. 3. Dimension b applies to metallized terminal and is measured between 0.25 and 0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.15mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional. 6. N is the total number of terminals. Symbol A A1 A3 L L1 b D E e D2 E2 aaa bbb ccc ddd eee fff N Min 0.80 0 0.35 0 0.18 4.60 4.60 - Nom 0.90 0.02 0.20 REF 0.40 0.25 6.00 BSC 6.00 BSC 0.50 BSC 4.70 4.70 0.15 0.10 0.10 0.05 0.08 0.10 36 Max 1.00 0.05 0.45 0.15 0.30 4.80 4.80 - Marking: YYWWIXX. YY Last two digits of the current year www.austriamicrosystems.com/AS8650 WW Manufacturing Week I Assembly plant identifier Revision 1.0 XX Assembly traceability code 43 - 46 AS8650 Datasheet - R e v i s i o n H i s t o r y Revision History Revision 1.0 Date 29 Nov, 2010 Owner hgl Description Initial release Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com/AS8650 Revision 1.0 44 - 46 AS8650 Datasheet - O r d e r i n g I n f o r m a t i o n 10 Ordering Information The devices are available as the standard products shown in Table 22. Table 22. Ordering Information Ordering Code AS8650-ZQFP-0001 1 Marking AS8650 Description AS8650 Power Management device with high-speed CAN Interface (standard configuration) Delivery Form Tape & Reel Package 36-pin QFN (6x6x0.9) 1. The AS8650 provides various configuration options during production. For more information, please contact our sales office. Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Technical Support is available at http://www.austriamicrosystems.com/Technical-Support For further information and requests, please contact us mailto: sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com/AS8650 Revision 1.0 45 - 46 AS8650 Datasheet - C o p y r i g h t s Copyrights Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com/AS8650 Revision 1.0 46 - 46