AT7910EKB-E

Features • SpaceWire Router – Logical to Physical addressing translation – Priority Management – Header Deletion Capability Eight Bidirectional SpaceWire links – Full duplex communication – Data rate from 2 up to 200 Mbit/s in each direction Two External Interfaces – Dedicated Input and Output FIFOs – 9-bit wide Interface Configuration Port – Read/Write Accesses to internal registers – Accessible from both the spacewire links (8 channels) and the external interfaces – Remote Memory Access Protocol (RMAP) support Time Code Interface – Master/Slave Capability Error/Status Interface Operating range – Voltages • 3V to 3.6V – Temperature • - 55°C to +125°C Maximum Power consumption – All spacewire links active at 200Mbit/s : 4W -TBC Radiation Performance – Total dose tested successfully up to 300 Krad (Si) – No single event latchup below a LET of 80 MeV/mg/cm2 ESD better than 2000V Quality Grades – QML-Q or V with SMD Package: 196pins MQFPF Mass: 12grams • • • SpW-10X SpaceWire Router AT7910E • • • • • • • • • 7796B–AERO–08/08 1. Description The SpW-10X SpaceWire routing switch is capable of connecting many nodes, providing a means of routing packets between the nodes connected to it. It comprises eight SpaceWire link interfaces and a routing matrix. The routing matrix enables packets arriving at one link interface to be transferred to and sent out of another link interface on the routing switch. The AT7910E was designed by Austrian Aerospace (Austria) and the University of Dundee (Scotland). It is manufactured using the SEU hardened cell library from Atmel MH1RT CMOS 0.35µm radiation hardened sea of gates technology. For any technical question relative to the functionality of the AT7910E please contact Atmel technical support at assp-applab.hotline@nto.atmel.com. This document must be read in conjunction with the University of Dundee “SpaceWire Router SpW-10X User Manual” available at www.atmel.com. The SpaceWire router comprises the following functional logic blocks: • Eight SpaceWire bi-directional serial ports. • Two external parallel input/output ports each comprising an input FIFO and an output FIFO. • A non-blocking crossbar switch connecting any input port to any output port. • An internal configuration port accessible via the crossbar switch from the external parallel input/output port or the SpaceWire input/output ports. • A routing table accessible via the configuration port which holds the logical address to output port mapping. • Control logic to control the operation of the switch, performing arbitration and group adaptive routing. • Control registers than can be written and read by the configuration port and which hold control information e.g. link operating speed. • An external time-code interface comprising tick_in, tick_out and current tick count value • Internal status/error registers accessible via the configuration port • External status/error signals A block diagram of the routing switch is given in the following figure: 2 AT7910E 7796B–AERO–08/08 AT7910E Figure 1-1. SpaceWire Router Block Diagram Control Logic SpaceWire Port 1 SpaceWire Port 2 SpaceWire Port 3 SpaceWire Port 4 SpaceWire Port 5 SpaceWire Port 6 SpaceWire Port 7 SpaceWire Port 8 Input FIFO Output FIFO Routing Table Status/Error Registers Status Outputs Control Registers Non-blocking Crossbar Switch SpaceWire Interfaces Configuration Port External Input/Output External Input/Output External Port Input FIFO Output FIFO External Port Time-Code Interface Time-Code Inputs / Outputs 1.1 SpaceWire Ports The SpaceWire router has eight bi-directional SpaceWire links each conformant to the SpaceWire standard. Each SpaceWire link is controlled by an associated link register and routing control logic. Packets received on SpaceWire links are routed by the routing control logic to the configuration port, other SpaceWire link ports or the external FIFO ports depending on the packet address. Packets with invalid addresses are discarded by the SpaceWire router. The SpaceWire link status is recorded in the associated link register and error status is held by the router until cleared by a configuration command. 1.2 External Ports The SpaceWire router has two bi-directional parallel FIFO interfaces that can be used to connect the router to an external host system. The external port FIFO is two data characters deep. Each FIFO is written to or read from synchronously with the 30MHz system clock. An eight-bit data interface and an extra control bit for end of packet markers are provided by each external port FIFO. Packets received by the external port are routed by the routing control logic to the configuration port, SpaceWire link ports or the other external port depending on the packet address. Packets with invalid addresses are discarded by the SpaceWire router. 3 7796B–AERO–08/08 1.3 Configuration Port The SpaceWire router has one configuration port which performs read and write operations to internal router registers. Packets are routed to the configuration port when a packet with a leading address byte equal to zero is received. The Remote Memory Access Protocol (RMAP) is used to access the configuration port. If an invalid command packet is received then the error is flagged to an associated status register and the packet is discarded. 1.4 Routing table The SpaceWire router routing table is set by the router command packets to assign logical addresses to physical destination ports on the router. A group of destination ports can be set, in each routing table location, to enable group adaptive routing. When a packet is received with a logical address the routing table is checked by the routing control logic and the packet is routed to the destination port when the port is ready. Routing table locations are set to invalid at power on or at reset. The routing table logical addresses can also be set to support high priority and header deletion. High priority packets are routed before low priority packets and header deletion of logical addresses can be used to support regional logical addressing. An invalid routing address will cause the packet to be spilled by the control logic. 1.5 Routing control logic and crossbar The routing control logic is responsible for arbitration of output ports, group adaptive routing and the crossbar switching. Arbitration is performed when two or more source ports are requesting to use the same destination port. A priority based arbitration scheme with two priority levels, high and low, is used where high priority packets are routed before low priority packets. Fair arbitration is performed on packets which have the same priority levels to ensure each packet gets equal access to the output port. Group adaptive routing control selects one of a number of output ports for sending out the source packet. 1.6 Time Code Processing An internal time-code register is used in the router to allow the router to be a time-code master or a time-code slave. In master mode the time-code interface is used to provide a tick-in to the SpaceWire routing causing time-codes to be propagated through the network. Two modes of time master operation are supported, an automatic mode where a time-code is propagated on each external tick-in and a normal mode where the time-code is propagated dependent on the external time-in signal. In time-code slave mode a valid received time-code, one plus the value of the router time-code register, causes a tick-out to be sent to the SpaceWire links and the external time-code interface. The time-code is propagated to all time-code ports except the port on which the time-code was received. If the time-code received is not one plus the value of the time-code register then the time-code register is updated but the tick-out is not performed. 4 AT7910E 7796B–AERO–08/08 AT7910E 1.7 Control/Status Registers The control and status registers in the SpaceWire router provide the means to control the operation of the router, set the router configuration and parameters or monitor the status of the device. The registers are accessed using RMAP command packets received by the configuration port. 5 7796B–AERO–08/08 2. Pin Configuration Table 1. Pin assignment Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name VDDB CLK RST TESTIOE TESTE FEEDBDIV0 VSSA VDDA FEEDBDIV1 FEEDBDIV2 VSSB VDDPLL VCOBias LOOPFILTER VSSPLL VDDB DIN+1 DIN-1 SIN+1 SIN-1 SOUT-1 SOUT+1 DOUT-1 DOUT+1 DIN+2 DIN-2 SIN+2 SIN-2 VSSB VDDB SOUT-2 SOUT+2 DOUT-2 DOUT+2 DIN+3 DIN-3 SIN+3 SIN-3 SOUT-3 SOUT+3 Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name VSSB VSSA VDDA VDDB DOUT-3 DOUT+3 DIN+4 DIN-4 LVDS_REF SIN+4 SIN-4 SOUT-4 SOUT+4 DOUT-4 DOUT+4 VSSA VDDA VSSB VDDB DIN+5 DIN-5 SIN+5 SIN-5 SOUT-5 SOUT+5 DOUT-5 DOUT+5 DIN+6 DIN-6 SIN+6 SIN-6 VSSB VDDB SOUT-6 SOUT+6 DOUT-6 DOUT+6 DIN+7 DIN-7 SIN+7 Pin Number 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name SIN-7 SOUT-7 SOUT+7 VSSB VDDB DOUT-7 DOUT+7 DIN+8 DIN-8 SIN+8 VSSA VDDA SIN-8 SOUT-8 SOUT+8 DOUT-8 DOUT+8 VSSB VDDB EXTOUTDATA9_0 EXTOUTDATA9_1 EXTOUTDATA9_2 EXTOUTDATA9_3 EXTOUTDATA9_4 VSSA VDDA EXTOUTDATA9_5 VSSB VDDB EXTOUTDATA9_6 EXTOUTDATA9_7 EXTOUTDATA9_8 EXTOUTEMPTY9 EXTOUTREAD9 EXTINDATA9_0 EXTINDATA9_1 EXTINDATA9_2 EXTINDATA9_3 EXTINDATA9_4 EXTINDATA9_5 Pin Number 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name EXTINDATA9_6 EXTINDATA9_7 EXTINDATA9_8 EXTINFULL9 VSSB VDDB EXTINWRITE9 EXTOUTDATA10_0 EXTOUTDATA10_1 EXTOUTDATA10_2 EXTOUTDATA10_3 EXTOUTDATA10_4 EXTOUTDATA10_5 VSSB VDDB EXTOUTDATA10_6 EXTOUTDATA10_7 EXTOUTDATA10_8 EXTOUTEMPTY10 VSSA VDDA EXTOUTREAD10 EXTINDATA10_0 EXTINDATA10_1 EXTINDATA10_2 EXTINDATA10_3 EXTINDATA10_4 EXTINDATA10_5 EXTINDATA10_6 EXTINDATA10_7 EXTINDATA10_8 EXTINFULL10 EXTINWRITE10 VSSA VDDA VSSB VDDB EXTTICKIN EXTTIMEIN0 EXTTIMEIN1 Pin Number 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 Name EXTTIMEIN2 EXTTIMEIN3 EXTTIMEIN4 EXTTIMEIN5 EXTTIMEIN6 EXTTIMEIN7 SELEXTTIME TIMECTRRST EXTTICKOUT EXTTIMEOUT0 EXTTIMEOUT1 EXTTIMEOUT2 EXTTIMEOUT3 VSSB VDDB EXTTIMEOUT4 EXTTIMEOUT5 EXTTIMEOUT6 EXTTIMEOUT7 STATMUXADDR0 STATMUXADDR1 STATMUXADDR2 STATMUXADDR3 VSSB VDDB STATMUXOUT0 STATMUXOUT1 STATMUXOUT2 VSSA VDDA STATMUXOUT3 STATMUXOUT4 STATMUXOUT5 STATMUXOUT6 STATMUXOUT7 VSSB 6 AT7910E 7796B–AERO–08/08 AT7910E 3. Pin Description Table 2. Pin description Signal Name(1)(3) VDDA VDDB VDDPLL VSSA VSSB VSSPLL LVDSRef VCOBias LoopFilter Ground for the device LVDS Power reference for the device Bias for the PLL VCO (Rvco) Internal PLL filter POWER POWER 3.3V Power for the device POWER Type(2) Function Buffer type CLK RST FEEDBDIV[2:0] I I I System Clock - Provides the reference clock for all the AT7910E modules except the SpaceWire interface receivers Asynchronous active low system reset PLL feedback divider configuration - Set the internal PLL output clock rate CMOS3V3 CMOS3V3 CMOS3V3 DOUT+[1:8] DOUT-[1:8] SOUT+[1:8] SOUT-[1:8] DIN+[1:8] DIN-[1:8] SIN+[1:8] SIN-[1:8] O O I I Differential output pair - Data part of Data-Strobe SpaceWire link 1 to 8. Differential output pair - Strobe part of Data-Strobe SpaceWire link 1 to 8. Differential input pair - Data part of Data-Strobe SpaceWire link 1 to 8. Differential input pair - Strobe part of Data-Strobe SpaceWire link 1 to 8. LVDS+ LVDSLVDS+ LVDSLVDS+ LVDSLVDS+ LVDS- EXTOUTDATA9[8:0] O Output data from external port zero FIFO. Bit eight determines the data type data, EOP or EEP Input data from external port zero FIFO. Bit eight determines the data type data, EOP or EEP FIFO ready signal for external output port zero. When high the FIFO has data. When low the FIFO is empty Asserted Low to read from the external output port zero FIFO. FIFO ready signal for external input port zero. When high there is space in the FIFO so it can be written to. When low the FIFO is full. Asserted Low to write to the external input port zero FIFO. Output data from external port one FIFO. Bit eight determines the data type data, EOP or EEP Input data from external port one FIFO. Bit eight determines the data type data, EOP or EEP FIFO ready signal for external output port one. When high the FIFO has data. When low the FIFO is empty CMOS3V3 EXTINDATA9[8:0] I CMOS3V3 EXTOUTEMPTY9 EXTOUTREAD9 EXTINFULL9 EXTINWRITE9 EXTOUTDATA10[8:0] O I O I O CMOS3V3 CMOS3V3 CMOS3V3 CMOS3V3 CMOS3V3 EXTINDATA10[8:0] I CMOS3V3 EXTOUTEMPTY10 O CMOS3V3 7 7796B–AERO–08/08 Signal Name(1)(3) EXTOUTREAD10 EXTINFULL10 EXTINWRITE10 Type(2) I O I Function Asserted Low to read from the external output port one FIFO. FIFO ready signal for external input port one. When high there is space in the FIFO so it can be written to. When low the FIFO is full. Asserted Low to write to the external input port one FIFO. Buffer type CMOS3V3 CMOS3V3 CMOS3V3 EXTTICKIN I The rising edge of the EXT_TICK_IN signal is used to indicate when a timecode is to be sent EXT_TIME_IN(7:0) provides the value of the time-code to be distributed by the router If SEL_EXT_TIME is high on the rising edge of EXT_TICK_IN the value on EXT_TIME_IN(7:0) is loaded into the internal time-code register and propagated by the router. This signal causes the internal time-code counter to be reset to zero. The falling edge of EXT_TICK_OUT is used to indicated the reception of a time-code. Received time-code value which is valid when EXT_TICK_OUT is asserted. CMOS3V3 EXTTIMEIN[7:0] I CMOS3V3 SELEXTTIME I CMOS3V3 TIMECTRRST EXTTICKOUT EXTTIMEOUT[7:0] I O O CMOS3V3 CMOS3V3 CMOS3V3 STATMUXADDR[3:0] I Select the error indication status signals to be output on STAT_MUX_OUT After reset the STAT_MUX_OUT pins are inputs which define the power on configuration status of the router. After the power on reset configuration of the router has been read from STAT_MUX_OUT the pins are driven as outputs by the router. CMOS3V3 STATMUXOUT[7:0] I/O CMOS3V3 TESTEN TESTIOEN I I Shall be tied to ground Shall be tied to ground CMOS3V3 CMOS3V3 Notes: 1. Groups of pins represent busses where the highest number is the MSB. 2. O = Output; I = Input; I/O = Input/Output 3. XXX = active low signal 8 AT7910E 7796B–AERO–08/08 AT7910E 4. Interfaces The AT7910E provides a routing capability between eight SpaceWire links according to the SpaceWire Standard ECSS-E-50-12A. In addition for use as a node interface, the AT7910E integrates other interfaces such as: • External ports • Configuration port • Time-code interface • Control/Status interface 4.1 Spacewire ports The SpaceWire router has eight bi-directional SpaceWire links each compliant with the SpaceWire standard ECSS-E-50-12A. Each SpaceWire link is controlled by an associated link register and routing control logic. Network level error recovery is performed when an error is detected on the SpaceWire link as defined in the SpaceWire standard. Packets received on SpaceWire links are routed by the routing control logic to the configuration port, other SpaceWire link ports or the external FIFO ports. Packets with invalid addresses are discarded by the SpaceWire router dependent on the packet address. The SpaceWire link status is recorded in the associated link register and error status is held by the router until cleared by a configuration command. 4.2 External ports The SpaceWire router has two bi-directional parallel FIFO interfaces to an external host system. Each FIFO is written to or read from synchronously to the 30MHz system clock. An eight-bit data interface and an extra control bit for end of packet markers are provided by each external port FIFO. Packets received by the external port are routed by the routing control logic to the configuration port, SpaceWire link ports or the other external port dependent on the packet address. Packets with invalid addresses are discarded by the SpaceWire router. 4.3 Configuration port The SpaceWire router has one configuration port which performs read and write operations to internal router registers. Packets are routed to the configuration port when a packet with a leading address byte of zero is received. The SpaceWire Router supports the Remote Memory Access Protocol (RMAP) as command packet format. If an invalid command packet is received then the error is flagged to the associated status register and the packet is discarded. 9 7796B–AERO–08/08 4.4 Time-code interface An internal time-code register is used in the router to allow the router to be a time-code master or a time-code slave. In master mode the time-code interface is used to provide a tick-in to the SpaceWire routing causing time-codes to be propagated through the network. Two modes of time master operation are supported, an automatic mode where a time-code is propagated on each external tick-in and a normal mode where the time-code is propagated dependent on the external time-in signal. In time-code slave mode a valid received time-code, one plus the value of the router time-code register, causes a tick-out to be sent to the SpaceWire links and the external time-code interface. The time-code is propagated to all time-code ports except the port on which the time-code was received. If the time-code received is not one plus the value of the time-code register then the time-code register is updated but the tick-out is not performed. In this way, circular network paths do not cause a constant stream of time-codes to be sent in a loop. 4.5 Control/Status interface The control and status registers in the SpaceWire router provide the means to control the operation of the router, set the router configuration and parameters or monitor the status of the device. The registers are accessed using RMAP commands packets received by the configuration port. 10 AT7910E 7796B–AERO–08/08 AT7910E 5. Typical Applications The AT7910E SpaceWire router is perfectly suited for development of applications requiring a standalone router, a terminal node with SpaceWire interface or a mixed configuration of the two previous ones. 5.1 Stand-alone router The AT7910E SpaceWire Router may be used as a stand-alone router with up to eight SpaceWire links connected to it. Configuration of the routing tables etc. may be done by sending SpaceWire packets containing configuration commands to the router. Figure 5-1. AT7910E as SpaceWire router 5.2 Node interface The SpaceWire Router has two external ports which enable the device to be used as a node interface. The equipment to be connected to the SpaceWire network is attached to one or both external ports. One or more SpaceWire ports are used to provide the connection into the SpaceWire network. Unused SpaceWire ports may be disabled and their outputs tri-stated to save power. In this arrangement configuration of the routing tables and other parameters may be done by sending configuration packets from the local host via an external port or from a remote network manager via a SpaceWire port. 11 7796B–AERO–08/08 Figure 5-2. AT7910E as SpaceWire node interface 5.3 Embedded router The SpaceWire Router device can also be used to provide a node with an embedded router. In this case the external ports are used to provide the local connections to the node and the SpaceWire ports are used to make connections to other ports in the network. Figure 5-3. AT7910E as Embedded Router 12 AT7910E 7796B–AERO–08/08 AT7910E 6. PLL Filter The AT7910E uses an internal PLL to provide the base transmit clock signal for the SpaceWire interfaces. External components are required to implement the PLL loop filter and to provide a bias for the PLL VCO. Note that RVCO, C and C0 are all connected to a quiet common ground track. Dedicated decoupling capacitors are also required for the PLL power supply. Figure 6-1. PLL filter and decoupling capacitors Table 6-1. PLL filter recommended components R C C0 RVCO 10kΩ ± 5%, ¼W 120pF, ± 5% 3.3pF, ± 5% 4.7kΩ for 100-150MHz operation 1.8kΩ for 150-200MHz operation Table 6-2. PLL decoupling capacitors Cpll1 Cpll2 100nF, ± 5% 1µF, ± 5% 13 7796B–AERO–08/08 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Table 7-1. Supply Voltage I/O Voltage Operating Temperature Range (Ambient) Junction Temperature Storage Temperature Range Thermal resistance Junction to case TA TJ Tstg RThJC Absolute Maximum Ratings Symbol VCC Value -0.5 to +4 -0.5 to VCC + 0.5 -55 to +125 175 -65 to +150 5 Unit V V °C °C °C °C/W Parameter Stresses above those listed may cause permanent damage to the device. 7.2 DC Electrical Characteristics Table 7-2. 3.3V operating range DC Characteristics Symbol VCC VIH VIL VOH VOL IOS 2.4 0.4 23 13 Min. 3.0 2.0 0.8 Max. 3.6 Unit V V V V V mA mA IOL = 3, 6, 12mA / VCC = VCC(min) IOH = 3, 6, 12mA / VCC = VCC(min) VOUT = VCC VOUT = GND Conditions Parameter Operating Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Short circuit current 7.3 Power consumption Maximum power consumption figures at Vcc = 3.6V are presented in the following table. Table 7-3. 3.3V Power Consumption Operation Mode ICCSB - Standby ICCOP1 - 200Mb/s on SpaceWire links ICCOP - 100Mb/s on SpaceWire links ICCOP1 - 10Mb/s on SpaceWire links 1 Power consumption [W] 2 1.3 - TBC 3.8 - TBC 1.9 - TBC 0.9 - TBC Notes: 1. Dynamic power with all interfaces active including external ports. 2. If a SpW IF is not active (switched off) assume a reduction of the static and dynamic power by 5%. 14 AT7910E 7796B–AERO–08/08 AT7910E 7.4 AC Electrical Characteristics The following table gives the worst case timings measured by Atmel on the 3.0V to 3.6V operating range Table 7-4. 3.3V operating range timings(1) Parameter Propagation delay CLK Low to DOUT0 High Propagation delay CLK Low to DOUT1 High Propagation delay CLK Low to DOUT2 High Propagation delay CLK Low to DOUT3 High Propagation delay CLK Low to DOUT4 High Propagation delay CLK Low to DOUT5 High Propagation delay CLK Low to DOUT6 High Propagation delay CLK Low to DOUT7 High Propagation delay CLK Low to DOUT0 Low Propagation delay CLK Low to DOUT1 Low Propagation delay CLK Low to DOUT2 Low Propagation delay CLK Low to DOUT3 Low Propagation delay CLK Low to DOUT4 Low Propagation delay CLK Low to DOUT5 Low Propagation delay CLK Low to DOUT6 Low Propagation delay CLK Low to DOUT7 Low Propagation delay CLK Low to SOUT0 High Propagation delay CLK Low to SOUT1 High Propagation delay CLK Low to SOUT2 High Propagation delay CLK Low to SOUT3 High Propagation delay CLK Low to SOUT4 High Propagation delay CLK Low to SOUT5 High Propagation delay CLK Low to SOUT6 High Propagation delay CLK Low to SOUT7 High Propagation delay CLK Low to SOUT0 Low Propagation delay CLK Low to SOUT1 Low Propagation delay CLK Low to SOUT2 Low Propagation delay CLK Low to SOUT3 Low Propagation delay CLK Low to SOUT4 Low Symbol Tp0 Tp1 Tp2 Tp3 Tp4 Tp5 Tp6 Tp7 Tp8 Tp9 Tp10 Tp11 Tp12 Tp13 Tp14 Tp15 Tp16 Tp17 Tp18 Tp19 Tp20 Tp21 Tp22 Tp23 Tp24 Tp25 Tp26 Tp27 Tp28 Min. Max. 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 7796B–AERO–08/08 Parameter Propagation delay CLK Low to SOUT5 Low Propagation delay CLK Low to SOUT6 Low Propagation delay CLK Low to SOUT7 Low Symbol Tp29 Tp30 Tp31 Min. Max. 16 16 16 Unit ns ns ns Note: 1. The timing parameters presented in the above table are measured under production configuration (PLL bypassed and test mode enabled). During normal operation (PLL active and test mode disabled) the propagation delay is directly linked to the PLL . Then, the timing figures are not applicable under application conditions. For guaranteed timings refer to the “ Switching Characteristics ” section of the ‘SpW-10X SpaceWire Router User Manual’. 16 AT7910E 7796B–AERO–08/08 AT7910E 8. Package Drawings 8.1 MQFPF196 Here is a presentation of the mechanical outline of the 196 pins Ceramic Quad Flat Pack (CQFP 196) package used for the AT7910E. Figure 8-1. MQFPF 196 package 17 7796B–AERO–08/08 9. Ordering Information Part-number AT7910EKB-E AT7910EKB-MQ AT7910EKB-SV Temperature Range 25°C -55°C to +125°C -55°C to +125°C Package MQFPF196 MQFPF196 MQFPF196 Quality Flow Engineering sample Mil Level B (*) Space Level B (*) (*) according to Atmel Quality flow document 4288, see Atmel web site. 10. Document Revision History 10.1 7796 Rev. B. 1. Corrected pinout error: pin 190 is VDDA and not VSSB. See Table 1 on page 6. 18 AT7910E 7796B–AERO–08/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support aero@nto.atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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