AT91SAM9XE128_1

Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP instruction Extensions, ARM Jazelle® Technology for Java® Acceleration – 8 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 200 MIPS at 180 MHz – Memory Management Unit – EmbeddedICE™, Debug Communication Channel Support Additional Embedded Memories – One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed – One 32 Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16 Kbyte (for AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed – 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128, AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024 Pages of 512 Bytes Respectively. • 128-bit Wide Access • Fast Read Time: 45 ns • Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms • 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash Security Bit Enhanced Embedded Flash Controller (EEFC) – Interface of the Flash Block with the 32-bit Internal Bus – Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface External Bus Interface (EBI) – Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash™ USB 2.0 Full Speed (12 Mbits per second) Device Port – On-chip Transceiver, 2,688-byte Configurable Integrated DPRAM USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-pin PQFP Device and Double Port in 217-ball LFBGA Device – Single or Dual On-chip Transceivers – Integrated FIFOs and Dedicated DMA Channels Ethernet MAC 10/100 Base-T – Media Independent Interface or Reduced Media Independent Interface – 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Image Sensor Interface – ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate – 12-bit Data Interface for Support of High Sensibility Sensors – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format Bus Matrix – Six 32-bit-layer Matrix – Remap Command Fully-featured System Controller, including – Reset Controller, Shutdown Controller – Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-time Timer • AT91 ARM Thumb Microcontrollers AT91SAM9XE128 AT91SAM9XE256 AT91SAM9XE512 Preliminary • • • • • • • • 6254B–ATARM–29-Apr-09 • Reset Controller (RSTC) – Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control • Clock Generator (CKGR) – Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 3 to 20 MHz On-chip Oscillator, One Up to 240 MHz PLL and One Up to 100 MHz PLL Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Two Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and support for Debug Communication Channel, Programmable ICE Access Prevention – Mode for General Purpose Two-wire UART Serial Communication Periodic Interval Timer (PIT) – 20-bit Interval Timer Plus 12-bit Interval Counter Watchdog Timer (WDT) – Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-Time Timer (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler One 4-channel 10-bit Analog to Digital Converter Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC,) – 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output Peripheral DMA Controller Channels (PDC) Two-slot Multimedia Card Interface (MCI) – SDCard/SDIO and MultiMediaCard™ Compliant – Automatic Protocol Control and Fast Automatic Data Transfers with PDC One Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support – Full Modem Signal Control on USART0 One 2-wire UART Two Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects – Synchronous Communications Two Three-channel 16-bit Timer/Counters (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability – High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2 Two Two-wire Interfaces (TWI) – Master, Multi-master and Slave Mode Operation – General Call Supported in Slave Mode – Connection to PDC Channel to Optimize Data Transfers in Master Mode Only • • • • • • • • • • • • • • • • 2 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary • IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins • Required Power Supplies: – 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL – 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os) – 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os) • Available in a 208-pin PQFP Green and a 217-ball LFBGA Green Package 1. AT91SAM9XE128/256/512 Description The AT91SAM9XE128/256/512 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM, 128, 256 or 512 Kbytes of Flash and a wide range of peripherals. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits a security bit and MMU protect the firmware from accidental overwrite and preserve its confidentiality. The AT91SAM9XE128/256/512 embeds an Ethernet MAC, one USB Device Port, and a USB Host Controller. It also integrates several standard peripherals, like six UARTs, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and a MultiMedia/SD Card Interface. The AT91SAM9XE128/256/512 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator. The AT91SAM9XE128/256/512 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide range of memory devices. The pinout and ball-out are fully compatible with the AT91SAM9260 with the exception that the pin BMS is replaced by the pin ERASE. 3 6254B–ATARM–29-Apr-09 2. AT91SAM9XE128/256/512 Block Diagram The block diagram shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-PQFP package and the unavailable pins are highlighted in “Multiplexing on PIO Controller A” on page 37, “Multiplexing on PIO Controller B” on page 38, “Multiplexing on PIO Controller C” on page 39. The USB Host Port B is also not available. Table 2-1 on page 4 defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package. Table 2-1. Unavailable Signals in 208-pin PQFP Device PIO PA30 PA31 PB12 PB13 PC2 PC3 PC12 Peripheral A HDPB HDMB SCK2 SCK0 TWD1 TWCK1 AD2 AD3 IRQ0 Peripheral B RXD4 TXD4 ISI_D10 ISI_D11 PCK1 SPI1_NPCS3 NCS7 4 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 Figure 2-1. MASTER E AS ER JT AG NT R TD ST TDI TMO TC S RTK CK ET EX T CK ECXE N ER ERRS -E XC T ERXE -EC XE K RO ET X0 -E L R -R M X0 ER XD D- X M C ETX 3 V D 3 F1 IO 00 TST Transc. Transc. In-Circuit Emulator System Controller JTAG Selection and Boundary Scan FIQ IRQ0-IRQ2 AIC DBGU ICache 16 Kbytes MMU Bus Interface DCache 8 Kbytes ARM926EJ-S Processor USB OHCI FIFO DMA DMA D FIFO DMA 10/100 Ethernet MAC DRXD DTXD PCK0-PCK1 I PDC PLLRCA PLLA PMC Filter PLLB XIN XOUT OSC WDT PIT 6-layer Matrix RC 4GPREG AT91SAM9XE128/256/512 Block Diagram OSCSEL XIN32 XOUT32 PIOA PIOB PIOC ROM 32 Kbytes Fast SRAM 16 or 32 Kbytes Peripheral Bridge OSC RTT SHDN WKUP Flash 128, 256 or 512 Kbytes SHDC VDDBU POR 24-channel Peripheral DMA VDDCORE POR APB RSTC BOD NRST PDC PDC PDC USART0 USART1 USART2 USART3 USART4 SPI0 SPI1 TC0 TC1 TC2 TC3 TC4 TC5 PDC PDC SSC PDC 4-channel 10-bit ADC MCI TWI0 TWI1 IS I_ M IS CK I_ IS PC I_ K I SI DO _V -I IS SY SI_ D I_ HS NC 7 YN C H D HD PA M A Image Sensor Interface EBI CompactFlash NAND Flash SDRAM Controller DPRAM USB Device Static Memory Controller ECC Controller Transceiver HD P HD B M B TW CT TW D RTS0- CK C SC S0- TS R3 RX K0- TS S3 TD C XD0-R K3 0- XD TX 5 DD S5 DCR0 D R0 DT I0 R0 M CD B0 -M CD M CD MC B3 A0 CD -M B C M DA CC 3 D MA CC K NP NPCS NPCS3 NPCS2 C1 SP S0 MC OK TC M SI IS L O TI K0 O -T TAC IO 0-T LK TC B0 IOA2 L -T 2 TI K3 IOB OTI A3 TC 2 O -T LK B 3- IO 5 TI A5 O B5 TK TF TD RD RF RK SPI0_, SPI1_ A D0 -A AD D3 TR IG AD VR EF VD DA NA G ND AN A D D DDM P 6254B–ATARM–29-Apr-09 SE L SLAVE D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21/NANDALE A22/NANDCLE D16-D31 NWAIT A23-A24 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1-CFCE2 NCS2, NCS6, NCS7 NCS3/NANDCS AT91SAM9XE128/256/512 Preliminary 5 3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Name Signal Description List Function Type Power Supplies Active Level Reference Voltage Comments VDDIOM VDDIOP0 VDDIOP1 VDDBU VDDANA VDDPLL VDDCORE GND GNDPLL GNDANA GNDBU EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply Peripherals I/O Lines Power Supply Backup I/O Lines Power Supply Analog Power Supply PLL Power Supply Core Chip and Embedded Memories Power Supply Ground PLL Ground Analog Ground Backup Ground Power Power Power Power Power Power Power Ground Ground Ground Ground Clocks, Oscillators and PLLs 1.65V to 1.95V or 3.0V to 3.6V 3.0V to 3.6V 1.65V to 3.6V 1.65V to 1.95V 3.0V to 3.6V 1.65V to 1.95V 1.65V to 1.95V XIN XOUT XIN32 XOUT32 OSCSEL PLLRCA PCK0 - PCK1 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Slow Clock Oscillator Selection PLL A Filter Programmable Clock Output Input Output Input Output Input Input Output Shutdown, Wakeup Logic VDDIOP0 VDDBU Accepts between 0V and VDDBU. SHDN WKUP Shutdown Control Wake-Up Input Output Input ICE and JTAG Low VDDBU VDDBU Driven at 0V only. Accepts between 0V and VDDBU. Pull-Up resistor (100 kΩ) No pull-up resistor, Schmitt trigger No pull-up resistor, Schmitt trigger NTRST TCK TDI TDO TMS JTAGSEL Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Input Input Input Output Input Input Low VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDBU No pull-up resistor, Schmitt trigger Pull-down resistor (15 kΩ). 6 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary Table 3-1. Signal Name RTCK Signal Description List (Continued) Function Return Test Clock Type Output Flash Memory Active Level Reference Voltage VDDIOP0 Comments ERASE Flash and NVM Configuration Bits Erase Command Input Reset/Test High VDDIOP0 Pull-down resistor (15 kΩ) NRST Microcontroller Reset I/O Low VDDIOP0 Open-drain output, Pull-Up resistor (100 kΩ). Inserted in the Boundary Scan. Pull-down resistor (15 kΩ) TST Test Mode Select Input Debug Unit - DBGU VDDBU DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Advanced Interrupt Controller - AIC VDDIOP0 VDDIOP0 IRQ0 - IRQ2 FIQ External Interrupt Inputs Fast Interrupt Input Input Input PIO Controller - PIOA - PIOB - PIOC VDDIOP0 VDDIOP0 PA0 - PA31 PB0 - PB30 PC0 - PC31 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C I/O I/O I/O External Bus Interface - EBI VDDIOP0 VDDIOP0 VDDIOP0 Pulled-up input at reset (100kΩ)(1) Pulled-up input at reset (100kΩ)(1) Pulled-up input at reset (100kΩ)(1) D0 - D31 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low VDDIOM VDDIOM VDDIOM Pulled-up input at reset 0 at reset Static Memory Controller - SMC NCS0 - NCS7 NWR0 - NWR3 NRD NWE NBS0 - NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output Low Low Low Low Low VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM 7 6254B–ATARM–29-Apr-09 Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Reference Voltage Comments CompactFlash Support CFCE1 CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines Output Output Output Output Output Output Output Low Low Low Low Low Low VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM NAND Flash Support NANDCS NANDOE NANDWE NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable Output Output Output Low Low Low VDDIOM VDDIOM VDDIOM SDRAM Controller SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Output Output Output Output Output Output Output Multimedia Card Interface MCI MCCK MCCDA MCDA0 MCDA3 MCCDB MCDB0 MCDB3 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot A Data Multimedia Card Slot B Command Multimedia Card Slot B Data Output I/O I/O I/O I/O VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Low Low High Low VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx TXDx RXDx RTSx CTSx DTR0 DSR0 USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send USART0 Data Terminal Ready USART0 Data Set Ready I/O I/O Input Output Input Output Input VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 8 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary Table 3-1. Signal Name DCD0 RI0 Signal Description List (Continued) Function USART0 Data Carrier Detect USART0 Ring Indicator Type Input Input Synchronous Serial Controller - SSC Active Level Reference Voltage VDDIOP0 VDDIOP0 Comments TD RD TK RK TF RF SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Output Input I/O I/O I/O I/O Timer/Counter - TCx VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O VDDIOP0 VDDIOP0 VDDIOP0 Serial Peripheral Interface - SPIx_ SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1SPIx_NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Low Low VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Two-Wire Interface TWDx TWCKx Two-wire Serial Data Two-wire Serial Clock I/O I/O USB Host Port HDPA HDMA HDPB HDMB USB Host Port A Data + USB Host Port A Data USB Host Port B Data + USB Host Port B Data + Analog Analog Analog Analog USB Device Port DDM DDP USB Device Port Data USB Device Port Data + Analog Analog VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 9 6254B–ATARM–29-Apr-09 Table 3-1. Signal Name Signal Description List (Continued) Function Type Ethernet 10/100 Active Level Reference Voltage Comments ETXCK ERXCK ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 Transmit Clock or Reference Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output Force 100Mbit/sec. Input Input Output Output Output Input Input Input Input Input Output I/O Output High VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 MII only, REFCK in RMII MII only ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII MII only MII only Image Sensor Interface ISI_D0ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK Image Sensor Data Image sensor Reference clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data clock Input output input input input Analog to Digital Converter AD0-AD3 ADVREF ADTRG Analog Inputs Analog Positive Reference ADC Trigger Analog Analog Input Fast Flash Programming Interface PGMEN[2:0] PGMNCMD PGMRDY PGMNOE PGMNVALID PGMM[3:0] PGMD[15:0] Note: Programming Enabling Programming Command Programming Ready Programming Read Data Direction Programming Mode Programming Data Input Input Output Input Output Input I/O Low High Low Low VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDANA VDDANA VDDANA Digital pulled-up inputs at reset VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 1. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the peripheral multiplexing tables. 10 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 4. Package and Pinout The AT91SAM9XE128/256/512 is available in a 208-pin PQFP Green package (0.5mm pitch) or in a 217-ball LFBGA Green package (0.8 mm ball pitch). 4.1 208-pin PQFP Package Outline Figure 4-1 shows the orientation of the 208-pin PQFP package. A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Characteristics” of the product datasheet. Figure 4-1. 208-pin PQFP Package Outline (Top View) 156 157 105 104 208 1 52 53 11 6254B–ATARM–29-Apr-09 4.2 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208-pin PQFP Package Pinout Pinout for 208-pin PQFP Package Signal Name PA24 PA25 PA26 PA27 VDDIOP0 GND PA28 PA29 PB0 PB1 PB2 PB3 VDDIOP0 GND PB4 PB5 PB6 PB7 PB8 PB9 PB14 PB15 PB16 VDDIOP0 GND PB17 PB18 PB19 TDO TDI TMS VDDIOP0 GND TCK NTRST NRST RTCK VDDCORE GND ERASE OSCSEL TST JTAGSEL GNDBU XOUT32 XIN32 VDDBU WKUP SHDN HDMA HDPA VDDIOP0 Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Signal Name GND DDM DDP PC13 PC11 PC10 PC14 PC9 PC8 PC4 PC6 PC7 VDDIOM GND PC5 NCS0 CFOE/NRD CFWE/NWE/NWR0 NANDOE NANDWE A22 A21 A20 A19 VDDCORE GND A18 BA1/A17 BA0/A16 A15 A14 A13 A12 A11 A10 A9 A8 VDDIOM GND A7 A6 A5 A4 A3 A2 NWR2/NBS2/A1 NBS0/A0 SDA10 CFIOW/NBS3/NWR3 CFIOR/NBS1/NWR1 SDCS/NCS1 CAS Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Signal Name RAS D0 D1 D2 D3 D4 D5 D6 GND VDDIOM SDCK SDWE SDCKE D7 D8 D9 D10 D11 D12 D13 D14 D15 PC15 PC16 PC17 PC18 PC19 VDDIOM GND PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 GND VDDCORE VDDPLL XIN XOUT GNDPLL NC GNDPLL PLLRCA VDDPLL GNDANA Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal Name ADVREF PC0 PC1 VDDANA PB10 PB11 PB20 PB21 PB22 PB23 PB24 PB25 VDDIOP1 GND PB26 PB27 GND VDDCORE PB28 PB29 PB30 PB31 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VDDIOP0 GND PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 VDDIOP0 GND PA18 PA19 VDDCORE GND PA20 PA21 PA22 PA23 Table 4-1. 12 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 4.3 217-ball LFBGA Package Outline Figure 4-2 shows the orientation of the 217-ball LFBGA package. A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Characteristics” of the product datasheet. Figure 4-2. 217-ball LFBGA Package Outline (Top View) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGH J K LMNPRTU Ball A1 13 6254B–ATARM–29-Apr-09 4.4 Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 217-ball LFBGA Package Pinout Pinout for 217-ball LFBGA Package Signal Name CFIOW/NBS3/NWR3 NBS0/A0 NWR2/NBS2/A1 A6 A8 A11 A13 BA0/A16 A18 A21 A22 CFWE/NWE/NWR0 CFOE/NRD NCS0 PC5 PC6 PC4 SDCK CFIOR/NBS1/NWR1 SDCS/NCS1 SDA10 A3 A7 A12 A15 A20 NANDWE PC7 PC10 PC13 PC11 PC14 PC8 WKUP D8 D1 CAS A2 A4 A9 A14 BA1/A17 A19 NANDOE PC9 PC12 DDP HDMB NC VDDIOP0 SHDN D9 D2 RAS D0 Table 4-2. Pin D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H8 H9 H10 H14 H15 H16 H17 J1 J2 J3 J4 J8 J9 J10 Signal Name A5 GND A10 GND VDDCORE GND VDDIOM GND DDM HDPB NC VDDBU XIN32 D10 D5 D3 D4 HDPA HDMA GNDBU XOUT32 D13 SDWE D6 GND OSCSEL ERASE JTAGSEL TST PC15 D7 SDCKE VDDIOM GND NRST RTCK TMS PC18 D14 D12 D11 GND GND GND VDDCORE TCK NTRST PB18 PC19 PC17 VDDIOM PC16 GND GND GND Pin J14 J15 J16 J17 K1 K2 K3 K4 K8 K9 K10 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Signal Name TDO PB19 TDI PB16 PC24 PC20 D15 PC21 GND GND GND PB4 PB17 GND PB15 GND PC26 PC25 VDDIOP0 PA28 PB9 PB8 PB14 VDDCORE PC31 GND PC22 PB1 PB2 PB3 PB7 XIN VDDPLL PC23 PC27 PA31 PA30 PB0 PB6 XOUT VDDPLL PC30 PC28 PB11 PB13 PB24 VDDIOP1 PB30 PB31 PA1 PA3 PA7 PA9 PA26 PA25 Pin P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name PB5 NC GNDANA PC29 VDDANA PB12 PB23 GND PB26 PB28 PA0 PA4 PA5 PA10 PA21 PA23 PA24 PA29 PLLRCA GNDPLL PC0 PC1 PB10 PB22 GND PB29 PA2 PA6 PA8 PA11 VDDCORE PA20 GND PA22 PA27 GNDPLL ADVREF PC2 PC3 PB20 PB21 PB25 PB27 PA12 PA13 PA14 PA15 PA19 PA17 PA16 PA18 VDDIOP0 14 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 5. Power Considerations 5.1 Power Supplies The AT91SAM9XE128/256/512 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal. • VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The expected voltage range is selectable by software. • VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from 3.0V and 3.6V, 3V or 3.3V nominal. • VDDIOP1 pin: Powers the Peripherals I/O lines involving the Image Sensor Interface; voltage ranges from 1.65V and 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. • VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.65V to 1.95V, 1.8V nominal. • VDDPLL pins: Power the PLL cells and the main oscillator; voltage ranges from 1.65V and 1.95V, 1.8V nominal. • VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V and 3.6V, 3.3V nominal. The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and their associated I/O lines in the multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDCORE, VDDIOM, VDDIOP0 and VDDIOP1 pins power supplies. Separated ground pins are provided for VDDBU, VDDPLL and VDDANA. These ground pins are respectively GNDBU, GNDPLL and GNDANA. 15 6254B–ATARM–29-Apr-09 6. I/O Line Considerations 6.1 ERASE Pin The pin ERASE is used to re-initialize the Flash content and the NVM bits. It integrates a permanent pull-down resistor of about 15 kΩ, so that it can be left unconnected for normal operations. This pin is debounced on the RC oscillator or 32,768 Hz to improve the glitch tolerance. Minimum debouncing time is 200 ms. 6.2 I/O Line Drive Levels The PIO lines PA0 to PA31 and PB0 to PB31 and PC0 to PC3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently with a total of 350 mA on all I/O lines. Refer to the “DC Characteristics” section of the product datasheet. 6.3 Shutdown Logic Pins The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than 1 MΩ. The resisitor value is calculated according to the regulator enable implementation and the SHDN level. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 7. Processor and Architecture 7.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • DSP Instruction Extensions • 5-Stage Pipeline Architecture: – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W) • 8 KB Data Cache, 16 KB Instruction Cache – Virtually-addressed 4-way Associative Cache – Eight words per line – Write-through and Write-back Operation – Pseudo-random or Round-robin Replacement • Write Buffer – Main Write Buffer with 16-word Data Buffer and 4-address Buffer 16 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary – DCache Write-back Buffer with 8-word Entries and a Single Address Entry – Software Control Drain • Standard ARM v4 and v5 Memory Management Unit (MMU) – Access Permission for Sections – Access Permission for large pages and small pages can be specified separately for each quarter of the page – 16 embedded domains • Bus Interface Unit (BIU) – Arbitrates and Schedules AHB Requests – Separate Masters for both instruction and data access providing complete Matrix system flexibility – Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) 7.2 Bus Matrix • 6-layer Matrix, handling requests from 6 masters • Programmable Arbitration strategy – Fixed-priority Arbitration – Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master • Burst Management – Breaking with Slot Cycle Limit Support – Undefined Burst Length Support • One Address Decoder provided per Master – Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one for internal flash boot, one after remap • Boot Mode Select – Non-volatile Boot Memory can be internal ROM or internal Flash – Selection is made by General purpose NVM bit sampled at reset • Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or Flash) – Allows Handling of Dynamic Exception Vectors 7.2.1 Matrix Masters The Bus Matrix of the AT91SAM9XE128/256/512 manages six Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. 17 6254B–ATARM–29-Apr-09 Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. Table 7-1. Master 0 Master 1 Master 2 Master 3 Master 4 Master 5 List of Bus Matrix Masters ARM926™ Instruction ARM926 Data Peripheral DMA Controller USB Host Controller Image Sensor Controller Ethernet MAC 7.2.2 Matrix Slaves Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 List of Bus Matrix Slaves Internal Flash Internal SRAM Internal ROM USB Host User Interface External Bus Interface Reserved Internal Peripherals 7.2.3 Masters to Slaves Access All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the Ethernet MAC to the internal peripherals. Thus, these paths are forbidden or simply not wired, and shown as “–” in the following table. Table 7-3. AT91SAM9XE128/256/512 Masters to Slaves Access Master 0 and 1 ARM926 Instruction and Data 2 Periphera DMA Controller – X X – X – X 3 ISI Controller – X – – X – – 4 Ethernet MAC X X – – X – – X – – X – – 5 USB Host Controller Slave 0 1 2 3 4 Internal Flash Internal SRAM Internal ROM UHP User Interface External Bus Interface Reserved Internal Peripherals X X X X X – X 7.3 Peripheral DMA Controller • Acting as one Matrix Master • Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. • Next Pointer Support, forbids strong real-time constraints on buffer management. 18 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary • Twenty-four channels – Two for each USART – Two for the Debug Unit – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – Two for the Two Wire Interface – One for Multimedia Card Interface – One for Analog To Digital Converter The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): – TWI0 Transmit Channel – TWI1 Transmit Channel – DBGU Transmit Channel – USART4 Transmit Channel – USART3 Transmit Channel – USART2 Transmit Channel – USART1 Transmit Channel – USART0 Transmit Channel – SPI1 Transmit Channel – SPI0 Transmit Channel – SSC Transmit Channel – TWI0 Receive Channel – TWI1 Receive Channel – DBGU Receive Channel – USART4 Receive Channel – USART3 Receive Channel – USART2 Receive Channel – USART1 Receive Channel – USART0 Receive Channel – ADC Receive Channel – SPI1 Receive Channel – SPI0 Receive Channel – SSC Receive Channel – MCI Transmit/Receive Channel 7.4 Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel 19 6254B–ATARM–29-Apr-09 • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 20 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 8. Memories Figure 8-1. AT91SAM9XE128/256/512 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF Internal Memory Mapping 0x0000 0000 Boot Memory (1) Notes : (1) Can be ROM or Flash depending on GPNVM[3] 256M Bytes 0x10 0000 ROM 0x10 8000 Reserved 32K Bytes 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 256M Bytes 0x20 0000 Flash 0x28 0000 Reserved 128, 256 or 512K Bytes 0x2000 0000 EBI Chip Select 1/ SDRAMC 256M Bytes 0x30 0000 SRAM 0x30 8000 Reserved 0x50 0000 32K Bytes 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 256M Bytes UHP 0x50 4000 Reserved 16K Bytes 0x4000 0000 EBI Chip Select 3/ NANDFlash EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 EBI Chip Select 6 256M Bytes 0x0FFF FFFF 0x4FFF FFFF 0x5000 0000 256M Bytes 0x5FFF FFFF 0x6000 0000 Peripheral Mapping 256M Bytes 0xF000 0000 0x6FFF FFFF 0x7000 0000 256M Bytes Reserved 0xFFFA 0000 TCO, TC1, TC2 0xFFFA 4000 UDP 0xFFFA 8000 16K Bytes 16K Bytes 16K Bytes 16K Bytes System Controller Mapping 0xFFFF C000 Reserved 0xFFFF E800 ECC 512 Bytes 0x7FFF FFFF 0x8000 0000 EBI Chip Select 7 0x8FFF FFFF 256M Bytes 0xFFFA C000 MCI TWI0 0xFFFB 0000 USART0 0xFFFB 4000 USART1 0xFFFB 8000 USART2 0xFFFB C000 SSC 0xFFFC 0000 ISI 0xFFFC 4000 EMAC 0xFFFC 8000 0xFFFF EA00 SDRAMC 0xFFFF EC00 512 Bytes 0x9000 0000 16K Bytes 0xFFFF EE00 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF F600 16K Bytes 0xFFFF F800 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FA00 SMC MATRIX 0xFFFF EF10 0xFFFF F000 CCFG AIC 0xFFFF F200 DBGU 0xFFFF F400 PIOA 512 Bytes 512 Bytes 512 Bytes 512 Bytes 512 Bytes Undefined (Abort) 1,518M Bytes 0xFFFC C000 SPI0 PIOB 512 bytes SPI1 0xFFFD 0000 USART3 0xFFFD 4000 PIOC 512 bytes EEFC 0xFFFF FC00 PMC TWI1 0xFFFF FD00 RSTC 0xFFFF FD10 TC3, TC4, TC5 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 WDTC SHDC RTTC PITC 0xFFFF FD50 0xFFFF FD60 16K Bytes 0xFFFF FFFF USART4 512 bytes 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 0xFFFD 8000 0xFFFD C000 0xFFFE 0000 0xEFFF FFFF ADC 0xFFFE 4000 0xF000 0000 Internal Peripherals 0xFFFF FFFF Reserved 256M Bytes 0xFFFF C000 SYSC 0xFFFF FFFF GPBR Reserved 21 6254B–ATARM–29-Apr-09 A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. The bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in order to simplify the mappings, all the masters have a similar address decoding. Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap, refer to Table 8-3, “Internal Memory Mapping,” on page 26 for details. A complete memory map is presented in Figure 8-1 on page 21. 8.1 8.1.1 Embedded Memories AT91SAM9XE128 • 32 KB ROM – Single Cycle Access at full matrix speed • 16 KB Fast SRAM – Single Cycle Access at full matrix speed • 128 KB Embedded Flash 8.1.2 AT91SAM9XE256 • 32 KB ROM – Single Cycle Access at full matrix speed • 32 KB Fast SRAM – Single Cycle Access at full matrix speed • 256 KB Embedded Flash 8.1.3 AT91SAM9XE512 • 32 KB ROM – Single Cycle Access at full matrix speed • 32 KB Fast SRAM – Single Cycle Access at full matrix speed • 512 KB Embedded Flash 8.1.4 ROM Topology The embedded ROM contains the Fast Flash Programming and the SAM-BA boot programs. Each of these two programs is stored at 16 KB Boundary and the program executed at address 22 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary zero depends on the combination of the TST pin and PA0 to PA2 pins. Figure 8-2 shows the contents of the ROM and the program available at address zero. Figure 8-2. ROM Boot Memory Map 0x0000 0000 0x0000 0000 0x0000 0000 SAM-BA Program SAM-BA Program FFPI Program 0x0000 7FFF 0x0000 3FFF 0x0000 3FFF FFPI Program ROM TST=0 TST=1 PA0=1 PA1=1 PA2=0 8.1.4.1 Fast Flash Programming Interface The Fast Flash Programming Interface programs the device through a serial JTAG interface or a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high and PA2 is tied low. Table 8-1. Signal Name PGMEN0 PGMEN1 PGMEN2 PGMNCMD PGMRDY PGMNOE PGMNVALID PGMM[3:0] PGMD[15:0] Signal Description PIO PA0 PA1 PA2 PA4 PA5 PA6 PA7 PA8..PA10 PA12..PA27 Type Input Input Input Input Output Input Output Input Input/Output Active Level High High Low Low High Low Low Comments Must be connected to VDDIO Must be connected to VDDIO Must be connected to GND Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset 8.1.4.2 SAM-BA® Boot Assistant The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port. 23 6254B–ATARM–29-Apr-09 • Communication through the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-detection. • Communication through the USB Device Port is depends on crystal selected: – limited to an 18,432 Hz crystal if the internal RC oscillator is selected – supports a wide range of crystals from 3 to 20 MHz if the 32,768 Hz crystal is selected The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). 8.1.5 Embedded Flash The Flash of the AT91SAM9XE128/256/512 is organized in 256/512/1024 pages of 512 bytes directly connected to the 32-bit internal bus. Each page contains 128 words. The Flash contains a 512-byte write buffer allowing the programming of a page. This buffer is write-only as 128 32-bit words, and accessible all along the 1 MB address space, so that each word can be written at its final address. The Flash benefits from the integration of a power reset cell and from a brownout detector to prevent code corruption during power supply changes, even in the worst conditions. 8.1.5.1 Enhanced Embedded Flash Controller The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Enhanced Embedded Flash Controller (EEFC) is a slave for the bus matrix and is configurable through its User Interface on the APB bus. It ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit wide memory interface increases performance, four 32-bit data are read during each access, this multiply the throughput by 4 in case of consecutive data. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic programming of the access parameters of the Flash (number of wait states, timings, etc.) 8.1.5.2 Lock Regions The memory plane of 128, 256 or 512 Kbytes is organized in 8, 16 or 32 locked regions of 32 pages each. Each lock region can be locked independently, so that the software protects the first memory plane against erroneous programming: If a locked-regions erase or program command occurs, the command is aborted and the EEFC could trigger an interrupt. The Lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 24 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary Figure 8-3. Flash First Memory Plane Mapping 0x0020 0000 Locked Region 0 Page 0 Locked Regions Area 128, 256 or 512 Kbytes 256, 512 or 1024 Pages Page 31 512 bytes Locked Region 7, 15 or 31 0x0021 FFFF or 0x0023 FFFF or 0x0027 FFFF 32 bits wide 16 KBytes 8.1.5.3 GPNVM Bits The AT91SAM9XE128/256/512 features four GPNVM bits that can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface. Table 8-2. GPNVMBit[#] 0 1 2 3 General-purpose Non volatile Memory Bits Function Security Bit Brownout Detector Enable Brownout Detector Reset Enable Boot Mode Select (BMS) 8.1.5.4 Security Bit The AT91SAM9XE128/256/512 features a security bit, based on a specific GPNVM bit, GPNVMBit[0]. When the security is enabled, access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. 25 6254B–ATARM–29-Apr-09 8.1.5.5 Non-volatile Brownout Detector Control Two GPNVM bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state. • GPNVMBit[1] is used as a brownout detector enable bit. Setting GPNVMBit[1] enables the BOD, clearing it disables the BOD. Asserting ERASE clears GPNVMBit[1] and thus disables the brownout detector by default. • GPNVMBit[2] is used as a brownout reset enable signal for the reset controller. Setting GPNVMBit[2] enables the brownout reset when a brownout is detected, clearing GPNVMBit[2] disables the brownout reset. Asserting ERASE disables the brownout reset by default. 8.1.6 Boot Strategies Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the GPNVMBit[3] state at reset. Table 8-3. Internal Memory Mapping REMAP = 0 Address GPNVMBit[3] clear 0x0000 0000 ROM GPNVMBit[3] set Flash SRAM REMAP = 1 The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted. Refer to the section “AT91SAM9XE Bus Matrix” in the product datasheet for more details. When REMAP = 0, a non volatile bit stored in Flash memory (GPNVMBit[3]) allows the user to lay out to 0x0, at his convenience, the ROM or the Flash. Refer to the section “Enhanced Embedded Flash Controller (EEFC)” in the product datasheet for more details. Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 21. The AT91SAM9XE Matrix manages a boot memory that depends on the value of GPNVMBit[3] at reset. The internal memory area mapped between address 0x0 and 0x0FFF FFFF is reserved for this purpose. If GPNVMBit[3] is set, the boot memory is the internal Flash memory If GPNVMBit[3] is clear (Flash reset State), the boot memory is the embedded ROM. After a Flash erase, the boot memory is the internal ROM. 8.1.6.1 GPNVMBit[3] = 0, Boot on Embedded ROM The system boots using the Boot Program. • Boot on slow clock (On-chip RC or 32,768 Hz) • Auto baudrate detection • SAM-BA Boot in case no valid program is detected in external NVM, supporting – Serial communication on a DBGU – USB Device Port 26 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 8.1.6.2 GPNVMBit[3] = 1, Boot on Internal Flash • Boot on slow clock (On-chip RC or 32,768 Hz) The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz, the user must take the following steps: 1. Program the PMC (main oscillator enable or bypass mode) 2. Program and start the PLL 3. Switch the main clock to the new value. 8.2 External Memories The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256 MB memory area assigned. Refer to the memory map in Figure 8-1 on page 21. 8.2.1 External Bus Interface • Integrates three External Memory Controllers: – Static Memory Controller – SDRAM Controller – ECC Controller • Additional logic for NANDFlash • Full 32-bit External Data Bus • Up to 26-bit Address Bus (up to 64 MB linear) • Up to 8 chip selects, Configurable Assignment: – Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 – Static Memory Controller on NCS3, Optional NAND Flash support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support – Static Memory Controller on NCS6-NCS7 8.2.2 Static Memory Controller • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported (4- up to 32-byte page size) • Multiple device adaptability – Compliant with LCD Module – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported 27 6254B–ATARM–29-Apr-09 8.2.3 SDRAM Controller • Supported devices: – Standard and Low Power SDRAM (Mobile SDRAM) • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency of 1, 2 and 3 supported • Auto Precharge Command not used 8.2.4 Error Corrected Code Controller • Hardware error corrected code generation – Detection and correction by software • Supports NAND Flash and SmartMedia devices with 8- or 16-bit data path • Supports NAND Flash and SmartMedia with page sizes of 528,1056, 2112 and 4224 bytes specified by software • Supports 1 bit correction for a page of 512, 1024, 2112 and 4096 bytes with 8- or 16-bit data path • Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 bytes with 8-bit data path • Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 bytes with 8-bit data path 28 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 9. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories. The System Controller’s peripherals are all mapped within the highest 16 KB of address space, between addresses 0xFFFF E800 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB. Figure 9-1 on page 30 shows the System Controller block diagram. Figure 8-1 on page 21 shows the mapping of the User Interfaces of the System Controller peripherals. 29 6254B–ATARM–29-Apr-09 9.1 System Controller Block Diagram AT91SAM9XE128/256/512 System Controller Block Diagram System Controller irq0-irq2 fiq periph_irq[2..24] efc2_irq pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset cal gpnvm[1] VDDCORE BOD por_ntrst jtag_nreset flash_poe NRST flash_wrdis VDDBU VDDBU POR VDDBU Powered SLCK Real-Time Timer rtt_irq rtt_alarm UHPCK Shutdown Controller periph_clk[20] periph_nreset periph_irq[20] 4 General-Purpose Backup Registers USB Host Port cal gpnvm[1..3] Reset Controller gpnvm[2] bod_rst_en rstc_irq periph_nreset proc_nreset backup_nreset security_bit(gpnvm0) flash_poe Embedded Flash VDDCORE Powered Advanced Interrupt Controller int proc_nreset PCK debug Debug Unit Periodic Interval Timer Watchdog Timer dbgu_irq dbgu_txd pit_irq jtag_nreset Boundary Scan TAP Controller nirq nfiq por_ntrst ntrst ARM926EJ-S Figure 9-1. wdt_irq wdt_fault WDRPROC MCK periph_nreset gpnvm[3] Bus Matrix flash_wrdis VDDCORE POR SLCK backup_nreset SLCK SHDN WKUP OSCSEL XIN32 XOUT32 RC OSC SLOW CLOCK OSC SLCK XIN XOUT PLLRCA int MAIN OSC PLLA PLLB MAINCK backup_nreset rtt0_alarm UDPCK periph_clk[2..27] pck[0-1] Power Management Controller PCK UDPCK UHPCK MCK periph_clk[10] periph_nreset periph_irq[10] USB Device Port PLLACK PLLBCK periph_nreset pmc_irq idle periph_clk[6..24] periph_nreset periph_nreset periph_clk[2..4] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PIO Controllers periph_irq[2..4] irq0-irq2 fiq dbgu_txd Embedded Peripherals periph_irq[6..24] in out enable 30 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 9.2 Reset Controller • Based on two Power-on reset cells – One on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset • Controls the internal resets and the NRST pin output – Allows shaping a reset signal for the external devices 9.3 Brownout Detector and Power-on Reset The AT91SAM9XE128/256/512 embeds one brownout detection circuit and power-on reset cells. The power-on reset are supplied with and monitor VDDCORE and VDDBU. Signals (flash_poe and flash_wrdis) are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brownouts occur on the VDDCORE power supply. The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device. The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE. When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot-), the brownout output is immediately activated. For more details on Vbot, see the table “Brownout Detector Characteristics” in the section “AT91SAM9XE128/256/512 Electrical Characteristics” in the full datasheet. When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + Vhyst), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs. The VDDCORE threshold voltage has a hysteresis of about 50 mV typical, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.55V with an accuracy of ± 2% and is factory calibrated. The brownout detector is low-power, as it consumes less than 12 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1 µA. The deactivation is configured through the GPNVMBit[1] of the Flash. Additional information can be found in the “Electrical Characteristics” section of the product datasheet. 9.4 Shutdown Controller • Shutdown and Wake-Up logic – Software programmable assertion of the SHDN pin – Deassertion Programmable on a WKUP pin level change or on alarm 31 6254B–ATARM–29-Apr-09 9.5 Clock Generator • Embeds a low power 32,768 Hz slow clock oscillator and a low-power RC oscillator selectable with OSCSEL signal – Provides the permanent slow clock SLCK to the system • Embeds the main oscillator – Oscillator bypass feature – Supports 3 to 20 MHz crystals • Embeds 2 PLLs – PLL A outputs 80 to 240 MHz clock – PLL B outputs 70 MHz to 130 MHz clock – Both integrate an input divider to increase output accuracy – PLLB embeds its own filter 9.6 Power Management Controller • Provides: – the Processor Clock PCK – the Master Clock MCK, in particular to the Matrix and the memory interfaces – the USB Device Clock UDPCK – independent peripheral clocks, typically at the frequency of MCK – 2 programmable clock outputs: PCK0, PCK1 • Five flexible operating modes: – Normal Mode, processor and peripherals running at a programmable frequency – Idle Mode, processor stopped waiting for an interrupt – Slow Clock Mode, processor and peripherals running at low frequency – Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt – Backup Mode, Main Power Supplies off, VDDBU powered by a battery 9.7 Periodic Interval Timer • Includes a 20-bit Periodic Counter, with less than 1 µs accuracy • Includes a 12-bit Interval Overlay Counter • Real Time OS or Linux®/WindowsCE® compliant tick generator 9.8 Watchdog Timer • 16-bit key-protected only-once-Programmable Counter • Windowed, prevents the processor to be in a dead-lock on the watchdog access 9.9 Real-time Timer • Real-time Timer with 32-bit free-running back-up counter • Integrates a 16-bit programmable prescaler running on slow clock • Alarm Register capable to generate a wake-up of the system through the Shutdown Controller 32 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 9.10 General-purpose Back-up Registers • Four 32-bit backup general-purpose registers 9.11 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive • Three External Sources plus the Fast Interrupt signal • 8-level Priority Controller – Drives the Normal Interrupt of the processor – Handles priority of the interrupt sources 1 to 31 – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per interrupt source – Interrupt Vector Register reads the corresponding current Interrupt Vector • Protect Mode – Easy debugging by preventing automatic operations when protect modeIs are enabled • Fast Forcing – Permits redirecting any normal interrupt source on the Fast Interrupt of the processor 9.12 Debug Unit • Composed of two functions – Two-pin UART – Debug Communication Channel (DCC) support • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE Interface 33 6254B–ATARM–29-Apr-09 9.13 Chip Identification • Chip ID: – 0x329AA3A0 for the SAM9XE512 – 0x329A93A0 for the SAM9XE256 – 0x329973A0 for the SAM9XE128 • JTAG ID: 05B1_C03F • ARM926 TAP ID: 0x0792603F 34 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 10. Peripherals 10.1 User Interface The Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 21. 10.2 Peripheral Identifier The AT91SAM9XE128/256/512 embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the AT91SAM9XE128/256/512. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 AT91SAM9XE128/256/512 Peripheral Identifiers Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC ADC US0 US1 US2 MCI UDP TWI0 SPI0 SPI1 SSC TC0 TC1 TC2 UHP EMAC ISI US3 US4 TWI1 TC3 TC4 TC5 AIC AIC AIC Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C Analog-to-digital Converter USART 0 USART 1 USART 2 Multimedia Card Interface USB Device Port Two Wire Interface 0 Serial Peripheral Interface 0 Serial Peripheral Interface1 Synchronous Serial Controller Reserved Reserved Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 USB Host Port Ethernet MAC Image Sensor Interface USART 3 USART 4 Two Wire Interface 1 Timer/Counter 3 Timer/Counter 4 Timer/Counter 5 Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller External Interrupt FIQ IRQ0 IRQ1 IRQ2 Note: Setting AIC, SYSC, UHP, ADC and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion. 35 6254B–ATARM–29-Apr-09 10.2.1 10.2.1.1 Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-time Timer • the Watchdog Timer • the Reset Controller • the Power Management Controller • Enhanced Embedded Flash Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.2.1.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.3 Peripheral Signals Multiplexing on I/O Lines The AT91SAM9XE128/256/512 features 3 PIO controllers, PIOA, PIOB, PIOC, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral function which are output only, might be duplicated within the both tables. The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 36 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 10.3.1 PIO Controller A Multiplexing Multiplexing on PIO Controller A PIO Controller A I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30(1) PA31(1) Note: Peripheral A SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 RTS2 CTS2 MCDA0 MCCDA MCCK MCDA1 MCDA2 MCDA3 ETX0 ETX1 ERX0 ERX1 ETXEN ERXDV ERXER ETXCK EMDC EMDIO ADTRG TWD0 TWCK0 TCLK0 TIOA0 TIOA1 TIOA2 SCK1 SCK2 SCK0 ETXER ETX2 ETX3 ERX2 ERX3 ERXCK ECRS ECOL RXD4 TXD4 ETX2 ETX3 MCDB3 MCDB2 MCDB1 Peripheral B MCDB0 MCCDB Comments Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Application Usage Function Comments Table 10-2. 1. Not available in the 208-lead PQFP package. 37 6254B–ATARM–29-Apr-09 10.3.2 PIO Controller B Multiplexing Multiplexing on PIO Controller B PIO Controller B Application Usage Comments Reset State I/O I/O I/O I/O I/O I/O TCLK1 TCLK2 I/O I/O I/O I/O ISI_D8 ISI_D9 ISI_D10 ISI_D11 I/O I/O I/O I/O I/O I/O TCLK3 TCLK4 TIOB4 TIOB5 ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_VSYNC ISI_HSYNC ISI_MCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 Function Comments Peripheral A SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 TWD1 TWCK1 DRXD DTXD TK0 TF0 TD0 RD0 RK0 RF0 DSR0 DCD0 DTR0 RI0 RTS0 CTS0 RTS1 CTS1 PCK0 PCK1 Peripheral B TIOA3 TIOB3 TIOA4 TIOA5 Table 10-3. I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Note: (1) (1) 1. Not available in the 208-lead PQFP package. 38 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 10.3.3 PIO Controller C Multiplexing Multiplexing on PIO Controller C PIO Controller C I/O Line PC0 PC1 PC2(1) PC3(1) PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Note: (1) Table 10-4. Application Usage Comments AD0 AD1 AD2 AD3 Reset State I/O I/O I/O I/O A23 A24 I/O I/O I/O I/O A25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Function Comments Peripheral A Peripheral B SCK3 PCK0 PCK1 SPI1_NPCS3 A23 A24 TIOB2 TIOB1 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW NCS2 IRQ0 FIQ NCS3/NANDCS NWAIT D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 SPI1_NPCS2 SPI1_NPCS1 CFCE1 CFCE2 RTS3 TIOB0 CTS3 SPI0_NPCS1 NCS7 NCS6 IRQ2 IRQ1 SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 EF100 TCLK5 1. Not available in the 208-lead PQFP package. 39 6254B–ATARM–29-Apr-09 10.4 10.4.1 Embedded Peripherals Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors • Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Very fast transfers supported – Transfers with baud rates up to MCK – The chip select line may be left active to speed up transfers on the same device 10.4.2 Two-wire Interface • Master, Multi-master and Slave modes supported • General call supported in Slave mode • Connection to PDC Channel 10.4.3 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – By 8 or by 16 oversampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit 40 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.4.4 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) • Contains an independent receiver and transmitter and a common clock divider • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.4.5 Timer Counter • Six 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels 10.4.6 Multimedia Card Interface • One double-channel Multimedia Card Interface • Compatibility with MultiMedia Card Specification Version 2.2 • Compatibility with SD Memory Card Specification Version 1.0 • Compatibility with SDIO Specification Version V1.0. • Cards clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used • MCI has two slot, each supporting – One slot for one MultiMediaCard bus (up to 30 cards) or – One SD Memory Card • Support for stream, block and multi-block data read and write 41 6254B–ATARM–29-Apr-09 10.4.7 USB Host Port • Compliance with Open HCI Rev 1.0 Specification • Compliance with USB V2.0 Full-speed and Low-speed Specification • Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices • Root hub integrated with two downstream USB ports in the 217-LFBGA package • Two embedded USB transceivers • Supports power management • Operates as a master on the Matrix 10.4.8 USB Device Port • USB V2.0 full-speed compliant, 12 MBits per second • Embedded USB V2.0 full-speed transceiver • Embedded 2,688-byte dual-port RAM for endpoints • Suspend/Resume logic • Ping-pong mode (two memory banks) for isochronous and bulk endpoints • Eight general-purpose endpoints – Endpoint 0 and 3: 64 bytes, no ping-pong mode – Endpoint 1, 2, 6, 7: 64 bytes, ping-pong mode – Endpoint 4 and 5: 512 bytes, ping-pong mode • Embedded pad pull-up 10.4.9 Ethernet 10/100 MAC • Compatibility with IEEE Standard 802.3 • 10 and 100 MBits per second data throughput capability • Full- and half-duplex operations • MII or RMII interface to the physical layer • Register Interface to address, data, status and control registers • DMA Interface, operating as a master on the Memory Controller • Interrupt generation to signal receive and transmit completion • 128-byte transmit and 128-byte receive FIFOs • Automatic pad and CRC generation on transmitted frames • Address checking logic to recognize four 48-bit addresses • Support promiscuous mode where all valid frames are copied to memory • Support physical layer management through MDIO interface control of alarm and update time/calendar data in 10.4.10 Image Sensor Interface • ITU-R BT. 601/656 8-bit mode external interface support • Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats 42 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary • Preview scaler to generate smaller size image 10.4.11 Analog-to-digital Converter • 4-channel ADC • 10-bit 312K samples/sec. Successive Approximation Register ADC • -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity • Individual enable and disable of each channel • External voltage reference for better accuracy on low voltage inputs • Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals 43 6254B–ATARM–29-Apr-09 44 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 11. ARM926EJ-S Processor 11.1 Overview The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multitasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Javapowered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S™ integer core • a Memory Management Unit (MMU) • separate instruction and data AMBA AHB bus interfaces • separate instruction and data TCM interfaces Table 11-1. Reference Document Table Denomination ARM926EJS Technical Reference Manual ARM9EJ-S Technical Reference Manual Owner-Reference ARM Ltd. - DD10198B ARM Ltd. - DD10222B 45 6254B–ATARM–29-Apr-09 11.2 Block Diagram Figure 11-1. ARM926EJ-S Internal Functional Block Diagram External Coprocessors ETM9 CP15 System Configuration Coprocessor External Coprocessor Interface Trace Port Interface Write Data ARM9EJ-S Processor Core Instruction Fetches Read Data Data Address MMU Instruction Address DTCM Interface Data TLB Instruction TLB ITCM Interface Data TCM Instruction TCM Data Address Data Cache AHB Interface and Write Buffer Instruction Address Instruction Cache AMBA AHB 46 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 11.3 11.3.1 ARM9EJ-S Processor ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: • ARM state: 32-bit, word-aligned ARM instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 11.3.2 Switching State The operating state of the ARM9EJ-S core can be switched between: • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC • ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 11.3.3 Instruction Pipelines The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages. 11.3.4 Memory Access The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and stalls the core or forward data. 11.3.5 Jazelle Technology The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. 47 6254B–ATARM–29-Apr-09 Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software. 11.3.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: • User mode is the usual ARM program execution state. It is used for executing most application programs • Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process • Interrupt (IRQ) mode is used for general-purpose interrupt handling • Supervisor mode is a protected mode for the operating system • Abort mode is entered after a data or instruction prefetch abort • System mode is a privileged user mode for the operating system • Undefined mode is entered when an undefined instruction exception occurs Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 48 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 11.3.7 ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers. • 31 general-purpose 32-bit registers • 6 32-bit status registers Table 11-2 shows all the registers in all modes. Table 11-2. User and System Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC ARM9TDMI Modes and Registers Layout Supervisor Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC PC Abort Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ABORT R14_ABORT PC Undefined Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC CPSR CPSR SPSR_SVC CPSR SPSR_ABOR T CPSR SPSR_UNDE F CPSR SPSR_IRQ CPSR SPSR_FIQ Mode-specific banked registers The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val49 6254B–ATARM–29-Apr-09 ues (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines: • constraints on the use of registers • stack conventions • argument passing and result return For more details, refer to ARM Software Development Kit. The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • Eight general-purpose registers r0-r7 • Stack pointer, SP • Link register, LR (ARM r14) • PC • CPSR There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, revision r1p2 page 2-12). 11.3.7.1 Status Registers The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode Figure 11-2. Status Register Format 31 30 29 28 27 24 765 0 NZCVQ J Reserved I FT Mode Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than Mode bits Thumb state bit FIQ disable IRQ disable Figure 11-2 shows the status register format, where: • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags 50 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag. • The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where: – J = 0: The processor is in ARM or Thumb state, depending on the T bit – J = 1: The processor is in Jazelle state. • Mode: five bits to encode the current processor mode 11.3.7.2 11.3.7.3 Exceptions Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types of exceptions are: • Fast interrupt (FIQ) • Normal interrupt (IRQ) • Data and Prefetched aborts (Abort) • Undefined instruction (Undefined) • Software interrupt and Reset (Supervisor) When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the following priority order: • Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. 11.3.7.4 Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 51 6254B–ATARM–29-Apr-09 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: – ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). – THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 11.3.8 ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions • Data processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). For further details, see the ARM Technical Reference Manual referenced in Table 11-1 on page 45. 52 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary Table gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor Coprocessor Data Processing Mnemonic MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR Operation Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word STRH STRB STRBT STRT STM SWPB MRC STC Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor 53 6254B–ATARM–29-Apr-09 11.3.9 New ARM Instruction Set . Table 11-3. Mnemonic BXJ BLX (1) SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB New ARM Instruction Mnemonic List Operation Branch and exchange to Java Branch, Link and exchange Signed Multiply Accumulate 16 * 16 bit Signed Multiply Accumulate Long Signed Multiply Accumulate 32 * 16 bit Signed Multiply 16 * 16 bit Signed Multiply 32 * 16 bit Saturated Add Saturated Add with Double Saturated subtract Saturated Subtract with double Mnemonic MRRC MCR2 MCRR CDP2 BKPT PLD STRD STC2 LDRD LDC2 CLZ Operation Move double from coprocessor Alternative move of ARM reg to coprocessor Move double to coprocessor Alternative Coprocessor Data Processing Breakpoint Soft Preload, Memory prepare to load from address Store Double Alternative Store from Coprocessor Load Double Alternative Load to Coprocessor Count Leading Zeroes Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. 11.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions • Load and Store multiple instructions • Exception-generating instruction Table 11-3 shows the Thumb instruction set, for further details, see the ARM Technical Reference Manual referenced in Table 11-1 on page 45. Table 11-4 gives the Thumb instruction mnemonic list. Table 11-4. Mnemonic MOV ADD SUB CMP TST Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Mnemonic MVN ADC SBC CMN NEG Operation Move Not Add with Carry Subtract with Carry Compare Negated Negate 54 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary Table 11-4. Mnemonic AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC Thumb Instruction Mnemonic List (Continued) Operation Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch Mnemonic BIC ORR LSR ROR BLX BL SWI STR STRH STRB LDRSB STMIA POP BKPT Operation Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right Branch, Link, and Exchange Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack Breakpoint 11.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ARM9EJ-S • Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 11-5. Table 11-5. Register 0 0 0 1 2 3 4 5 5 6 CP15 Registers Name ID Code (1) Read/Write Read/Unpredictable Read/Unpredictable Read/Unpredictable Read/write Read/write Read/write None (1) (1) Cache type(1) TCM status Control Translation Table Base Domain Access Control Reserved Data fault Status (1) Read/write Read/write Read/write Instruction fault status Fault Address 55 6254B–ATARM–29-Apr-09 Table 11-5. Register 7 8 9 9 10 11 12 13 13 14 15 Notes: CP15 Registers Name Cache Operations TLB operations cache lockdown TCM region TLB lockdown Reserved Reserved FCSE PID(1) Context ID Reserved Test configuration (1) (2) Read/Write Read/Write Unpredictable/Write Read/write Read/write Read/write None None Read/write Read/Write None Read/Write 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. 56 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 11.4.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below: 31 30 29 28 27 26 25 24 cond 23 22 21 20 1 19 1 18 1 17 0 16 opcode_1 15 14 13 L 12 11 10 CRn 9 8 Rd 7 6 5 4 1 3 1 2 1 1 1 0 opcode_2 1 CRm • CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. • opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. • Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. • CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. • L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM. 57 6254B–ATARM–29-Apr-09 11.5 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian® OS, WindowsCE®, and Linux®. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 11-6 shows the different attributes of each page in the physical memory. Table 11-6. Mapping Details Mapping Size 1M byte 64K bytes 4K bytes 1K byte Access Permission By Section 4 separated subpages 4 separated subpages Tiny Page Subpage Size 16K bytes 1K byte - Mapping Name Section Large Page Small Page Tiny Page The MMU consists of: • Access control logic • Translation Look-aside Buffer (TLB) • Translation table walk hardware 11.5.1 Access Control Logic The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 11.5.2 Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- 58 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary fied Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 11.5.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Pagemapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual. 11.5.4 MMU Faults The MMU generates an abort on the following types of faults: • Alignment faults (for data accesses only) • Translation faults • Domain faults • Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual. 59 6254B–ATARM–29-Apr-09 11.6 Caches and Write Buffer The ARM926EJ-S contains a 16-Kbyte Instruction Cache (ICache), a 8-Kbyte Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown). 11.6.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 11.6.2 Data Cache (DCache) and Write Buffer ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the 11.6.2.1 60 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 11.6.2.2 Write Buffer The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and writeback region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. 11.6.2.3 Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 11.6.2.4 Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 61 6254B–ATARM–29-Apr-09 11.7 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: • It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. • Each AHB layer becomes simple because it only has one master, so no arbitration or masterto-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. • The arbitration becomes effective when more than one master wants to access the same slave simultaneously. 11.7.1 Supported Transfers The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 11-7 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 11-7. HBurst[2:0] Supported Transfers Description Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT, or WB that has missed in DCache) SINGLE Single transfer • data read (NCNB or NCB) • NC instruction fetch (prefetched and non-prefetched) • page table walk read Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write. Cache linefill INCR4 INCR8 WRAP8 Four-word incrementing burst Eight-word incrementing burst Eight-word wrapping burst 11.7.2 Thumb Instruction Fetches All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time. Address Alignment The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. 11.7.3 62 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 12. AT91SAM9XE Debug and Test 12.1 Overview The AT91SAM9XE features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 63 6254B–ATARM–29-Apr-09 12.2 Block Diagram Figure 12-1. Debug and Test Block Diagram TMS TCK TDI NTRST Boundary Port ICE/JTAG TAP JTAGSEL TDO RTCK Reset and Test POR TST ARM9EJ-S ICE-RT ARM926EJ-S PDC DBGU PIO DTXD DRXD TAP: Test Access Port 64 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 12.3 12.3.1 Application Examples Debug Environment Figure 12-2 on page 65 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 12-2. Application Debug and Trace Environment Example Host Debugger ICE/JTAG Interface ICE/JTAG Connector AT91SAM9XE RS232 Connector Terminal AT91SAM9XE-based Application Board 65 6254B–ATARM–29-Apr-09 12.3.2 Test Environment Figure 12-3 on page 66 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain. Figure 12-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n Chip 2 AT91SAM9XE Chip 1 AT91SAM9XE-based Application Board In Test 12.4 Debug and Test Pin Description Table 12-1. Pin Name Debug and Test Pin List Function Reset/Test Type Active Level NRST TST Microcontroller Reset Test Mode Select ICE and JTAG Input/Output Input Low High NTRST TCK TDI TDO TMS RTCK JTAGSEL Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select Returned Test Clock JTAG Selection Debug Unit Input Input Input Output Input Output Input Low DRXD DTXD Debug Receive Data Debug Transmit Data Input Output 66 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 12.5 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. All the JTAG signals are supplied with VDDIOP0. 12.6 12.6.1 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 12.6.2 Embedded In-circuit Emulator The ARM9EJ-S Embedded In-Circuit Emulator-RT is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a storemultiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of the Embedded ICE-RT. The scan chains are controlled by the ICE/JTAG port. Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded In-Circuit-Emulator-RT, see the ARM document: ARM9EJ-S Technical Reference Manual (DDI 0222A). 12.6.3 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9XE Debug Unit Chip ID value is 0x0198 03A0 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 67 6254B–ATARM–29-Apr-09 12.6.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 12.6.4.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associated control signals. Each AT91SAM9XE input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 12-2.AT91SAM9XE JTAG Boundary Scan Register Bit Number 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 Pin Name A0 Pin Type IN/OUT Associated BSR Cells CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT A1 IN/OUT A10 IN/OUT A11 IN/OUT A12 IN/OUT A13 IN/OUT A14 IN/OUT A15 IN/OUT A16 IN/OUT A17 IN/OUT A18 IN/OUT 68 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 A19 IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT INPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT A2 IN/OUT A20 IN/OUT A21 IN/OUT A22 IN/OUT A3 IN/OUT A4 IN/OUT A5 IN/OUT A6 IN/OUT A7 IN/OUT A8 IN/OUT A9 BMS CAS IN/OUT INPUT IN/OUT D0 IN/OUT D1 IN/OUT D10 IN/OUT D11 IN/OUT D12 IN/OUT D13 IN/OUT 69 6254B–ATARM–29-Apr-09 Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 D14 IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT INPUT D15 IN/OUT D2 IN/OUT D3 IN/OUT D4 IN/OUT D5 IN/OUT D6 IN/OUT D7 IN/OUT D8 IN/OUT D9 IN/OUT NANDOE IN/OUT NANDWE IN/OUT NCS0 IN/OUT NCS1 IN/OUT NRD IN/OUT NRST IN/OUT NWR0 IN/OUT NWR1 IN/OUT NWR3 OSCSEL IN/OUT INPUT 70 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 PA0 IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT PA1 IN/OUT PA10 IN/OUT PA11 IN/OUT PA12 IN/OUT PA13 IN/OUT PA14 IN/OUT PA15 IN/OUT PA16 IN/OUT PA17 IN/OUT PA18 IN/OUT PA19 IN/OUT PA2 IN/OUT PA20 IN/OUT PA21 IN/OUT PA22 IN/OUT PA23 IN/OUT PA24 IN/OUT PA25 IN/OUT PA26 IN/OUT 71 6254B–ATARM–29-Apr-09 Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 PB14 PA4 PA27 IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT PA28 IN/OUT PA29 IN/OUT PA3 IN/OUT internal internal internal internal IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT PA5 IN/OUT PA6 IN/OUT PA7 IN/OUT PA8 IN/OUT PA9 IN/OUT PB0 IN/OUT PB1 IN/OUT PB10 IN/OUT PB11 IN/OUT internal internal internal internal IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT PB15 IN/OUT 72 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 PB16 IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT PB17 IN/OUT PB18 IN/OUT PB19 IN/OUT PB2 IN/OUT PB20 IN/OUT PB21 IN/OUT PB22 IN/OUT PB23 IN/OUT PB24 IN/OUT PB25 IN/OUT PB26 IN/OUT PB27 IN/OUT PB28 IN/OUT PB29 IN/OUT PB3 IN/OUT PB30 IN/OUT PB31 IN/OUT PB4 IN/OUT PB5 IN/OUT 73 6254B–ATARM–29-Apr-09 Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 PC20 PC13 PB6 IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT PB7 IN/OUT PB8 IN/OUT PB9 IN/OUT PC0 IN/OUT PC1 IN/OUT PC10 IN/OUT PC11 IN/OUT internal internal IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT PC14 IN/OUT PC15 IN/OUT PC16 IN/OUT PC17 IN/OUT PC18 IN/OUT PC19 IN/OUT internal internal IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT PC21 IN/OUT PC22 IN/OUT 74 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 PC30 PC23 IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT PC24 IN/OUT PC25 IN/OUT PC26 IN/OUT PC27 IN/OUT PC28 IN/OUT PC29 IN/OUT internal internal IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL OUTPUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT PC31 IN/OUT PC4 IN/OUT PC5 IN/OUT PC6 IN/OUT PC7 IN/OUT PC8 IN/OUT PC9 IN/OUT RAS IN/OUT RTCK OUT SDA10 IN/OUT SDCK IN/OUT 75 6254B–ATARM–29-Apr-09 Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 07 06 05 04 03 02 01 00 SDCKE IN/OUT CONTROL INPUT/OUTPUT CONTROL INPUT/OUTPUT CONTROL OUTPUT INPUT INPUT SDWE IN/OUT SHDN TST WKUP OUT INPUT INPUT 12.6.5 JID Code Register Access: Read-only 31 30 29 28 27 26 25 24 VERSION 23 22 21 20 19 PART NUMBER 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER 7 6 5 4 3 MANUFACTURER IDENTITY 2 1 0 MANUFACTURER IDENTITY 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B13 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B1_303F. 76 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 13. AT91SAM9XE Boot Program 13.1 Overview The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. SAM-BA Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port. 13.2 Flow Diagram The Boot Program implements the algorithm in Figure 13-1. Figure 13-1. Boot Program Algorithm Flow Diagram Start Internal RC Oscillator No Large Crystal Table Yes Main Oscillator Bypass No Reduced Crystal Table Yes Input Frequency Table No USB Enumeration Successful ? No Character(s) received on DBGU ? SAM-BA Boot Yes Run SAM-BA Boot Yes Run SAM-BA Boot 77 6254B–ATARM–29-Apr-09 13.3 Device Initialization Initialization follows the steps described below: 1. FIQ Initialization 2. Stack setup for ARM supervisor mode 3. External Clock Detection 4. Switch Master Clock on Main Oscillator 5. C variable initialization 6. Main oscillator frequency detection if no external clock detected 7. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. a. If Internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is active, Table 13-1 defines the crystals supported by the Boot Program when using the internal RC oscillator. Table 13-1. Reduced Crystal Table (MHz) OSCSEL = 0 3.0 Boot on DBGU Boot on USB Note: Yes Yes 6.0 Yes Yes 18.432 Yes Yes Other Yes No Any other crystal can be used but it prevents using the USB. b. If Internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is bypassed, Table 13-2 defines the frequencies supported by the Boot Program when bypassing main oscillator. Input Frequencies Supported by Software Auto-detection (MHz) OSCSEL = 0 1.0 2.0 Yes Yes 6.0 Yes Yes 12.0 Yes Yes 25.0 Yes Yes 50.0 Yes Yes Other Yes No Table 13-2. Boot on DBGU Boot on USB Note: Yes Yes Any other input frequency can be used but it prevents using the USB. c. If an external 32768 Hz Oscillator is used (OSCSEL = 1) (OSCSEL = 1 and bypass mode), Table 13-3 defines the crystals supported by the Boot Program. Large Crystal Table (MHz) OSCSEL = 1 3.2768 4.9152 6.4 8.0 12.288 16.367667 3.6864 5.0 6.5536 9.8304 13.56 17.734470 3.84 5.24288 7.159090 10.0 14.31818 18.432 4.0 6.0 7.3728 11.05920 14.7456 20.0 Table 13-3. 3.0 4.433619 6.144 7.864320 12.0 16.0 Note: Booting on USB or on DBGU is possible with any of these crystals. 78 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 8. Initialization of the DBGU serial port (115200 bauds, 8, N, 1) only if OSCSEL = 1 9. Enable the user reset 10. Jump to SAM-BA Boot sequence 11. Disable the Watchdog 12. Initialization of the USB Device Port Figure 13-2. Clocks and DBGU Configurations Start No Internal RC Oscillator? (OSCSEL = 0) Yes Scan Large Crystal Table (Table 15.3 &15.4) Scan Reduced Table (Table 15.1 &15.2) MCK = PLLB/2 UDPCK = PLLB/2 "ROMBoot>" displayed on DBGU MCK = Mosc UDPCK = PLLB/2 DBGU not configured No End No (USB) Autobaudrate ? Yes (DBGU) MCK = Mosc UDPCK = PLLB/2 DBGU not configured MCK = PLLB UDPCK = xxxx DBGU configured End End 79 6254B–ATARM–29-Apr-09 13.4 SAM-BA Boot The SAM-BA boot principle is to: – Wait for USB Device enumeration. – In parallel, wait for character(s) received on the DBGU if MCK is configured to 48 MHz (OSCSEL = 1). – If not, the Autobaudrate sequence is executed in parallel (see Figure 13-3). Figure 13-3. AutoBaudrate Flow Diagram Device Setup Character '0x80' received ? Yes No 1st measurement Character '0x80' received ? Yes Character '#' received ? Yes No 2nd measurement No Test Communication Send Character '>' UART operational Run SAM-BA Boot – Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in Table 13-4. 80 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary Table 13-4. Command O o H h W w S R G V Commands Available through the SAM-BA Boot Action write a byte read a byte write a half word read a half word write a word read a word send a file receive a file go display version Argument(s) Address, Value# Address,# Address, Value# Address,# Address, Value# Address,# Address,# Address, NbOfBytes# Address# No argument Example O200001,CA# o200001,# H200002,CAFE# h200002,# W200000,CAFEDECA# w200000,# S200000,# R200000,1234# G200200# V# • Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. – Address: Address in hexadecimal. – Value: Byte, halfword or word to write in hexadecimal. – Output: ‘>’. • Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. – Address: Address in hexadecimal – Output: The byte, halfword or word read in hexadecimal following by ‘>’ • Send a file (S): Send a file to a specified address – Address: Address in hexadecimal – Output: ‘>’. Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. • Receive a file (R): Receive data into a file from a specified address – Address: Address in hexadecimal – NbOfBytes: Number of bytes in hexadecimal to receive – Output: ‘>’ • Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’ • Get Version (V): Return the SAM-BA boot version – Output: ‘>’ 81 6254B–ATARM–29-Apr-09 13.4.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 13.4.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: – = 01 hex – = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) – = 1’s complement of the blk#. – = 2 bytes CRC16 Figure 13-4 shows a transmission using this protocol. Figure 13-4. Xmodem Transfer Example Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Device 13.4.3 USB Device Port A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows®, from Windows 98SE to Windows XP. The CDC document, available at 82 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. 13.4.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 13-5. Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION GET_STATUS SET_FEATURE CLEAR_FEATURE Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. Returns status for the specified recipient. Used to set or enable a specific feature. Used to clear or disable a specific feature. The device also handles some class requests defined in the CDC class. Table 13-6. Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE Handled Class Requests Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 13.4.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAMBA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 83 6254B–ATARM–29-Apr-09 13.4.4 In-Application Programming (IAP) Feature The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the FLASH to be ready (looping while the FRDY bit is not set in the MC_FSR register). Since this function is executed from ROM, this allows FLASH programming (like sector write) to be done by code running in FLASH. The IAP function entry point is retrieved by reading the SWI vector in ROM (0x100008). This funtion takes one argument in parameter: the command to be sent to the EEFC. This function returns the value of the MC_FSR register. IAP software code example: (unsigned int) (*IAP_Function)(unsigned long); void main (void) { unsigned long FlashSectorNum = 200; unsigned long flash_cmd = 0; unsigned long flash_status = 0; /* Initialize the function pointer (retrieve function address from SWI vector) */ IAP_Function = ((unsigned long) (*)(unsigned long)) 0x100008; /* Send your data to the sector */ /* build the command to send to EFC */ flash_cmd = (0x5A 32 kHz) is connected to XIN, then the device will switch on the external clock. Else, XIN input is not considered. An higher frequency on XIN speeds up the programmer handshake. Table 14-18. Reset TAP Controller and Go to Select-DR-Scan TDI X X X X X X Xt TMS 1 1 1 1 1 0 1 Test-Logic Reset Run-Test/Idle Select-DR-Scan TAP Controller State 97 6254B–ATARM–29-Apr-09 14.3.3 Read/Write Handshake The read/write handshake is done by carrying out read/write operations on two registers of the device that are accessible through the JTAG: • Debug Comms Control Register: DCCR • Debug Comms Data Register: DCDR Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A register is read by scanning its address into the address field and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data. Refer to the ARM7TDMI reference manuel for more information on Comm channel operations. Figure 14-5. TAP 8-bit DR Register TDI r/w 4 Address 5 0 31 Data 32 0 TDO Address Decoder Debug Comms Control Register Debug Comms Data Register A read or write takes place when the TAP controller enters UPDATE-DR state. Refer to the IEEE 1149.1 for more details on JTAG operations. • The address of the Debug Comms Control Register is 0x04. • The address of the Debug Comms Data Register is 0x05. The Debug Comms Control Register is read-only and allows synchronized handshaking between the processor and the debugger. – Bit 1 (W): Denotes whether the programmer can read a data through the Debug Comms Data Register. If the device is busy W = 0, then the programmer must poll until W = 1. – Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms Data Register. If R = 1, data previously placed there through the scan chain has not been collected by the device and so the programmer must wait. The write handshake is done by polling the Debug Comms Control Register until the R bit is cleared. Once cleared, data can be written to the Debug Comms Data Register. The read handshake is done by polling the Debug Comms Control Register until the W bit is set. Once set, data can be read in the Debug Comms Data Register. 14.3.4 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 14-3 on page 89. Commands are run by the programmer through the serial interface that is reading and writing the Debug Comms Registers. 98 AT91SAM9XE128/256/512 Preliminary 6254B–ATARM–29-Apr-09 AT91SAM9XE128/256/512 Preliminary 14.3.4.1 Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at any valid address in the memory plane. This address must be word-aligned. The address is automatically incremented. Table 14-19. Read Command Read/Write Write Write Read Read ... Read DR Data (Number of Words to Read)