ATA6025_05

Features • • • • • • • Watchdog Adjustable Over- and Undervoltage Detection of Vcc = 5V Standby Modes On/Off via Ignition Pin VKL15 Internal Time Delay for Output Signal Push-pull Output Driver Interference and Damage Protection According to ISO/CD 7637 ESD Protection Watchdog IC ATA6025 1. Description The ATA6025 is a monolithic circuit based on Atmel’s smart power BCD60-III technology. It is a universal IC for monitoring basic functions of an automotive application. It is possible to monitor the battery voltage (VKL15) and an external 5V voltage regulator. With the independent watchdog the correct function of a microcontroller can be observed. If a failure occurs, the output NOTL switches to high after a time delay. During standby mode the current consumption is reduced to a minimum. Figure 1-1. Block Diagram RREF VBG VCC oscillator on chip trimming OSC VCCH VCC over- & undervoltage detection IBias standby mode BIAS current 5V regulator VBG POR & Bandgap Reference VB monitoring VDD POR VBOK NOTL Short circuit 2.5 mA protected VB VCCL up &down counter 400ms NL High at counter end NL Low at counter zero POR VDD VKL15 VDD NVKL15 failure watchdog fwd Watchdog WD standby mode OSC Input Test mode 1 or 2 CLK High at counter zero OSC divided by 4 GND Rev. 4716C–AUTO–09/05 2. Pin Configuration Figure 2-1. Pinning SO8 NOTL VB GND RREF 1 2 3 4 8 7 6 5 VCC CLK WD VKL15 Table 2-1. Pin 1 2 3 4 5 6 7 8 Pin Description Symbol NOTL VB GND RREF VKL15 WD CLK VCC Function Push-pull output driver Voltage supply Ground Reference voltage to adjust oscillator frequency via resistor Rset Input for standby modes on/of via ignition KL15 Input for watchdog signal from microcontroller Clock output signal, open drain Input for monitoring 5V power supply 2 ATA6025 4716C–AUTO–09/05 ATA6025 3. Functional Description 3.1 Voltage Supply The IC can be supplied directly from Vbattery. If the voltage at the VB pin is lower than the threshold of VVBlo = 5.76 V, the internal signal VBOK is set to low. If VBOK is low, the monitor function of the IC is completely disabled and the output NOTL is switched off in all cases (see Figure 8-3 on page 10). If the voltage at pin VKL15 is low, the IC is in standby mode and reduces the current consumption at pin VB < 100 µA. 3.2 Oscillator The frequency fCLK of the internal oscillator is defined by the external resistor RSET and the internal capacitor. Thus, it is possible to vary the oscillator frequency between 4 kHz and 24 kHz. 3.3 VKL15 Monitoring This input is used to monitor the battery voltage at ignition pin VKL15. If the voltage VKL15lo < 1.8V, the internal signal NVKL15 is set to high (see Figure 8-3 on page 10). The IC switches to standby mode. During standby mode the monitor function is disabled and the output NOTL is switched off after the time delay tDelay. If the output NOTL is switched on and the voltage at VKL15 switches suddenly to low, the internal timer starts and switches the NOTL off after a time delay of tDelay = 400 ms. 3.4 VCC Over-/Undervoltage Via the VCC input an external 5V voltage regulator is continuously monitored. If the voltage at pin VCC exceeds the voltage of VCChon > 6.3V, the failure bit VCCH is set high. If the voltage at pin VCC decreases to a value below VCClon < 4V, the internal failure bit VCCL will be set to high (see Figure 8-1 on page 9). This failure bit starts the internal counter and switches the output NOTL on after the time delay of typically tDelay= 400 ms. If the VCC voltage is inside the tolerance VCCloff < VVCC < VCChoff the failure signal will be reset and the internal counter counts back to zero. After a time delay of typically tDelay = 400 ms, the output NOTL is switched off again. 3.5 Watchdog A microcontroller can be monitored by a digital window watchdog which accepts an incoming trigger signal TWD of a constant frequency at pin WD for correct operation. If the pulse width TWD between two alternate edges exceeds the time window of ToWD > 8.9 ms or if there is no watchdog signal, the failure signal fwd (failure watchdog) is set. In case the pulse width TWD between two alternate edges falls below the time window of TuWD < 2.6 ms, the failure signal fwd (failure watchdog) is also set. With this fwd signal the internal up counter is activated and after a time delay of tDelay = 400 ms, the output NOTL is switched to high. If NOTL is high, 16 successive correct watchdog signals T WD w ithin the pulse width of TuWD < TWD < ToWD are needed to create the internal signal nfwd (no failure watchdog) to start the down counter. After a time delay of tDelay= 400 ms, the output NOTL is switched to low (see Figure 8-2 on page 9). 3 4716C–AUTO–09/05 3.6 Time Delay The internal time delay is generated by an up/down counter. The clock for the counter is disabled if the voltage at the supply pin VB < 5.76V. In this case, the internal signal VBOK will be set to low and the output NOTL is directly switched to low. The direction of counting is set by the watchdog or VCC over- and undervoltage detection. If the VCC monitoring detects an undervoltage condition, the failure signal VCCL (VCC low voltage) is set and starts the up counter. If the VCC monitoring detects an overvoltage condition, the failure signal VCCH (VCC high voltage) is set and starts the up counter. A failure at the watchdog sets the internal fwd signal (failure watchdog) to high and starts the up counter. If the counter’s final value is reached, a Flip Flop is set and switches the output NOTL to high. If no failure signal is set and the window watchdog has counted successive 16 alternate WDI edges then the down counter is started. If the counter reaches the zero value the Flip Flop receives a reset command and switches the output NOTL off. The down counter is also started if the voltage at input VKL15 is low and switches the output NOTL after tDelay = 400 ms to low (see Figure 8-3 on page 10). 3.7 Output NOTL If the voltage at VKL15 is high and if a failure signal is set, the output NOTL switches to high after the internal time delay. The output is short circuit protected with a current limitation of ISCNOTL = 15 mA. The maximum output voltage is limited to VCNOTL = 22V (see Figure 8-4 on page 10). 3.8 Test Mode The pin CLK is normally open or connected to GND. If the internal clock frequency is to be checked, the CLK pin has to be connected with an external resistor Rex = 5 kΩ to a 5V supply. The measured value is the clock frequency divided by four. 4 ATA6025 4716C–AUTO–09/05 ATA6025 4. Truth Table VVB VVB < 5.76V VVCC Do not care VVCC < 4V WDI Do not care Do not care Do not care 7.26V < VVB < 17.5V 4.8V < VVCC < 5.2V VVCC > 6.3V VVCC > 6.3V VVCC < 4V No watchdog failure Watchdog failure Do not care Do not care Do not care 22V< VVB < 40V 4.8V < VVCC < 5.2V VVCC > 6.3V VVCC > 6.3V No watchdog failure Watchdog failure Do not care VKL15 Low High Low High Low High High Low High Low High Low High High Low High Mode Standby, NOTL low NOTL low Standby, NOTL low NOTL high Standby, NOTL low NOTL low NOTL high Standby, NOTL low NOTL high Standby, NOTL low NOTL high (maximum 22 V) Standby, NOTL low NOTL low NOTL high (maximum 22 V) Standby, NOTL low NOTL high 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Voltage at pins VCC, WD Voltage at pins RREF, CLK Voltage at pin NOTL Voltage at pin KL15 (in series with external resistor of 50 kΩ 1%) Maximum current at pin VCC Maximum current at pin VB Maximum current in pins CLK, RREF, VKL15, NOTL Maximum current at pin WD ESD classification HBM ESD S.5.1 ESD classification MM JEDEC A115A Power dissipation Chip temperature Operating ambient temperature Storage temperature IWD all pins all pins PV TJ Tamb TStg –40 –40 –55 Symbol VVB VVCC, VWDI VRREF, VCLK VNOTL VKL15 IVCC IVB Min. –0.3 –0.3 –0.5 –0.3 –0.1 –100 –10 –100 –1 2000 200 300 +150 +125 +150 Max. +40 +30 +6 +22 +40 +0.1 +10 +100 +1 Unit V V V V V mA mA mA mA V V mW °C °C °C 5 4716C–AUTO–09/05 6. Thermal Resistance Parameters Thermal resistance from junction to ambient Symbol RthJA Value 160 Unit K/W 7. Electrical Characteristics VVB = 7.2V to 17.5V, RKL15 = 50 kΩ 1%, RSET = 22 kΩ 1%, Tamb = –40 to 125°C, unless otherwise specified No. 0 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Current Consumption and ESD Clamping VVKL15 > 4.5V Current consumption in VVB =17.5V NOTL = high normal mode INOTL = –2.5 mA Standby: Current consumption in VVKL15 < 1.8V VVB = 17.5V standby mode NOTL = low Negative ESD clamping to GND, IVB = –10 mA pin VB Positive ESD clamping pin RREF Positive ESD clamping pin CLK Positive ESD clamping pin VB Positive ESD clamping pin VKL15 Positive ESD clamping pin NOTL Positive ESD clamping pin WD Positive ESD clamping pin VCC Reference Voltage Voltage at RREF Possible values of resistor RREF Oscillator Oscillator frequency Oscillator frequency is variable in a range VB Monitoring High level threshold Low level threshold Hysteresis 2 2 2 VVBhi VVBlo VVBhys 5.94 5.76 0.2 7.26 7.04 V V V A A A RSET = 22 kW ±1% at pin CLK with pull-up-resistor to +5 V RSE = 10 kΩ to 50 kΩ ±1% 7 fCLK fCLK 9 10 11 kHz A 4 4 VRREF RRREF 1.14 10 1.22 22 1.3 50 V kΩ A A to GND, IRREF = 5 mA to GND, ICLK = 20 mA to GND, IVB = 5 mA to GND, IVKL15 = 1.6 mA to GND, INOTL = 20 mA to GND, IWD = 0.7 mA to GND, IVCC = 0.5 mA 0.1 2 IVB 10 mA A 0.2 2 IVBstby 100 µA A 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.10 1 1.1 1.2 2 2.1 2 4 7 2 5 1 6 8 VNVB VPRREF VPCLK VPVB VPVKL15 VPNOTL VPWD VPVCC –1.4 4 6 41 41 31 35 35 –0.3 8 10 65 65 55 55 55 V V V V V V V V A A A A A A A A 2.2 4 4.1 4.2 4.3 7 3.96 24.2 kHz A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 6 ATA6025 4716C–AUTO–09/05 ATA6025 7. Electrical Characteristics (Continued) VVB = 7.2V to 17.5V, RKL15 = 50 kΩ 1%, RSET = 22 kΩ 1%, Tamb = –40 to 125°C, unless otherwise specified No. 5 5.1 5.2 5.3 5.4 6 Parameters VKL15 Monitoring Input resistor at VKL15 Low voltage threshold High voltage threshold Hysteresis VCC Monitoring Pull-down resistor to GND at pin VCC Undervoltage detection low level Undervoltage detection high level Overvoltage detection high level Overvoltage detection low level Hysteresis of underand overvoltage detection Oscillator Test Pull-down-resistor Saturation voltage Short current Saturation voltage NOTL switched off Short current NOTL if switched off Maximum output voltage NOTL Saturation voltage NOTL switched on; guaranteed down to VB low level threshold Short current NOTL if switched off Time delay of internal up and down counter CLK = high, VCLK = 0V to 4.5V ICLK = 1.6 mA, CLK = low VCLK = 5V, CLK = low INOTL = 1.8 mA NOTL off VNOTL = VVB NOTL off 17.5V < VVB < 30V INOTL = –2.5 mA NOTL on VsatNOTLon = VVB – VNOTL VVKL15 = VVB INOTL = –2.5 mA NOTL on VNOTL = 0 V NOTL = on 7 7 7 RpdCLK VsCLK IscCLK 6 15 0.4 10 kΩ V mA A A A VVB = 17.5V VVKL15 = 0V or VVKL15 = VVB VVCC = 5V kΩ RKL15 = 50 kΩ ±1% RKL15 = 50 kΩ ±1% 5 5 5 5 RiKL15 VKL15lo VKL15hi VKL15hys 0.2 18 1.8 4.5 1 70 kΩ V V V A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 6.1 8 RpdVCC 50 350 A 6.2 6.3 6.4 6.5 8 8 8 8 VCCIon VCCIoff VCCIoff VCChoff VCChys 4 4.8 6.3 5.2 V V V V A A A A 6.6 9 9.1 9.2 9.3 10 10.1 10.2 8 0.2 V A Push-pull Output NOTL 1 1 VsatNOTLoff IscNOTLoff VNOTLmax 17.5 1 15 V mA A A 10.3 1 22 V A 10.4 1 VsatNOTLon 0.25 V A 10.5 10.7 1 1 IscNOTLon tDelay –50 360 400 450 mA ms A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7 4716C–AUTO–09/05 7. Electrical Characteristics (Continued) VVB = 7.2V to 17.5V, RKL15 = 50 kΩ 1%, RSET = 22 kΩ 1%, Tamb = –40 to 125°C, unless otherwise specified No. 10.8 Parameters Rise time at pin NOTL switch on Fall time at pin NOTL switch off Watchdog Pull-down-resistor Voltage threshold low Voltage threshold high Hysteresis Acceptable low WD pulse width for failure Acceptable high WD pulse width for failure VhysWD = VhighWD – VlowWD Pulse = high or low RSET = 22 kΩ ±1% Pulse = high or low RSET = 22 kΩ ±1% VVB = VKL15 = 17.5V 6 6 6 6 6 6 RpdWD VlowWD VhighWD VhysWD TuWD ToWD 0.5 2.6 7.1 3 8 3.3 8.9 30 1 3.5 200 kΩ V V V ms ms A A A A A A Test Conditions CNOTL ≤ 200 pF VNOTL from low = 10% to high = 90% VVB CNOTL ≤ 200 pF VNOTL from high = 90% to low = 10% V(VB) Pin 1 Symbol trNOTL Min. Typ. Max. 5 Unit µs Type* A 10.9 11 11.1 11.2 11.3 11.4 11.5 11.6 1 tfNOTL 5 µs A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 8 ATA6025 4716C–AUTO–09/05 ATA6025 8. Diagrams Figure 8-1. V(VCC) VCChon VCChoff VCCloff VCClon VCC Monitoring Diagram t low VCCH high VCCL Figure 8-2. Watchdog Timing Diagram no WD or TWD >ToWD TuWD < TWD < ToWD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TWD