ADNS-6090
Gaming Laser Mouse Sensor
Data Sheet
Description
Features
The Avago Technologies ADNS-6090 sensor along with
the ADNS-6120 or ADNS-6130-001 lens, ADNS-6230-001
clip and ADNV-6340 laser diode form a complete and
compact laser mouse tracking system. It is the laser illuminated gaming mouse system enabled for high performance navigation. Driven by Avago’s LaserStream
Technology, it can operate on many surfaces that prove
difficult for traditional LED-based optical navigation.
It’s high performance architecture is capable of sensing
high-speed mouse motion - with resolution up to
1600 counts per inch, velocities up to max of 65 inches
per second and acceleration up to 20g. This sensor is
powered for the high sensitive user.
x High speed motion detection – up to max of 65ips
and 20g
There is no moving part in the complete assembly for
ADNS-6090 laser mouse system, thus it is high reliability and less maintenance for the end user. In additional,
precision optical alignment is not required, facilitating
high volume assembly.
x LaserStream architecture for greatly improved optical
navigation technology
x Programmable frame rate over 7200 frames per
second
x SmartSpeed self-adjusting frame rate for optimum
performance
x Serial port burst mode for fast data transfer
x 800/1200/1600/2000/2400/3000cpi selectable
resolution
x Single 3.3 volts power supply
x Four-wire serial port along with Power Down and
Reset pins
x Laser fault detect circuitry on-chip
Applications
Theory of Operation
The ADNS-6090 is based on LaserStream technology, which measures changes in position by optically
acquiring sequential images (frames) and mathematically
determining the direction and magnitude of movement.
ADNS-6090 contains an Image Acquisition System (IAS), a
Digital Signal Processor (DSP), and a four wire serial port.
The IAS acquires microscopic surface images via the lens
and illumination system. These images are processed
by the DSP to determine the direction and distance of
motion. The DSP calculates the Δx and Δy relative displacement values.
An external microcontroller reads the Δx and Δy information from the sensor serial port. The microcontroller
then translates the data into PS2 or USB signals before
sending them to the host PC or game console.
x Laser mice for game consoles and computer games
x Laser mice for desktop PC’s, Workstations, and
portable PC’s
x Laser trackballs
x Integrated input devices
Pinout
Pin
Name
Description
1
NCS
Chip select (active low input)
2
MISO
Serial data output (Master In/Slave Out)
3
SCLK
Serial clock input
4
MOSI
Serial data input (Master Out/Slave In)
5
NC
No Connection
6
RESET
Reset input
7
NPD
Power down (active low input)
8
OSC_OUT
Oscillator output
9
GUARD
Oscillator GND for PCB guard (optional)
10
OSC_IN
Oscillator input
11
REFC
Reference capacitor
12
REFB
Reference capacitor
13
RBIN
Binning Resistor to set XY_LASER
current
14
XY_LASER
LASER current output
15
NC
No Connection
16
VDD3
Supply voltage
17
GND
Ground
18
VDD3
Supply voltage
19
GND
Ground
20
LASER_
NEN
Laser enable (active low)
2
Figure 1. Package outline drawing (top view)
Figure 2. Package outline drawing
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
3
Overview of Laser Mouse Sensor Assembly
Figure 3. Assembly drawing of ADNS-6090 (top, front and cross-sectional view)
4
2D Assembly Drawing of ADNS-6090, PCBs and Base Plate
Customer Supplied VCSEL PCB
ADNS-6090 (sensor)
ADNV-6340 (VCSEL)
Customer Supplied PCB
ADNS-6230-001 (clip)
ADNS-6120 (round lens)*
Customer Supplied Base Plate
With Recommended Features
Per IGES Drawing*
* or ADNS-6130-001 trim lens
Figure 4. Exploded view drawing
Shown with ADNS-6120 Laser Mouse Lens, ADNS-6230001 VCSEL Assembly Clip and ADNV-6340 VCSEL. The
components interlock as they are mounted onto defined
features on the base plate.
The ADNS-6090 laser mouse sensor is designed for
mounting on a through-hole PCB, looking down. There is
an aperture stop and features on the package that align
to the lens.
The ADNV-6340 VCSEL provides a laser diode with a
single longitudinal and a single transverse mode. It is particularly suited as lower power consumption and highly
coherent replacement of LEDs. It also provides wider
operation range while still remaining within single-mode,
reliable operating conditions.
The ADNS-6120 or ADNS-6130-001 Laser Mouse Lens
is designed for use with ADNS-6090 sensor and the illumination subsystem provided by the assembly clip and
the VCSEL. Together with the VCSEL, the ADNS-6120 or
5
ADNS-6130-001 lens provides the directed illumination
and optical imaging necessary for proper operation of
the Laser Mouse Sensor. ADNS-6120 and ADNS-6130001 are precision molded optical component and should
be handled with care to avoid scratching of the optical
surfaces. ADNS-6120 also has a large round flange to
provide a long creepage path for any ESD events that
occur at the opening of the base plate.
The ADNS-6230-001 VCSEL Assembly Clip is designed to
provide mechanical coupling of the ADNV-6340 VCSEL
to the ADNS-6120 or ADNS-6130-001lens. This coupling
is essential to achieve the proper illumination alignment
required for the sensor to operate on a wide variety of
surfaces.
Avago Technologies provides an IGES file drawing describing the base plate molding features for lens and PCB
alignment.
Figure 5. Recommended PCB mechanical cutouts and spacing
Assembly Recommendation
1. Insert the sensor and all other electrical components
into the application PCB (main PCB board and VCSEL
PCB board).
2. Wave Solder the entire assembly in a no-wash
solder process utilizing a solder fixture. The solder
fixture is needed to protect the sensor during the
solder process. It also sets the correct sensor-to -PCB
distance, as the lead shoulders do not normally rest
on the PCB surface. The fixture should be designed to
expose the sensor leads to solder while shielding the
optical aperture from direct solder contact.
3. Place the lens onto the base plate.
4. Remove the protective kapton tape from the optical
aperture of the sensor. Care must be taken to keep
contaminants from entering the aperture.
6
5. Insert the PCB assembly over the lens onto the base
plate. The sensor aperture ring should self-align to the
lens. The optical position reference for the PCB is set
by the base plate and lens. Note that the PCB motion
due to button presses must be minimized to maintain
optical alignment.
6. Remove the protective kapton tape from the VCSEL.
7. Insert the VCSEL assembly into the lens.
8. Slide the clip in place until it latches. This locks the
VCSEL and lens together.
9. Install the mouse top case. There must be a feature in
the top case (or other area) to press down onto the
sensor to ensure the sensor and lens are interlocked to
the correct vertical height.
Design considerations for improving ESD Performance
For improved electrostatic discharge performance,
typical creepage and clearance distance are shown in the
table below. Assumption: base plate construction as per
the Avago supplied IGES file for ADNS-6120 round lens.
Typical Distance
Millimeters
Creepage
12.0
Clearance
2.1
Figure 6. Cross section of PCB assembly
The lens flange can be sealed (i.e. glued) to the base
plate. Note that the lens material is polycarbonate
and therefore, cyanoacrylate based adhesives or other
adhesives that may damage the lens should NOT be
used.
25LC160A 16KBit EEPROM (optional)
3.3V Regulator
+3.3V
R7 100K
__
1
VCC
___
WP
____
HLD
CS
6
SCLK
5
SI
2
S0
Buttons
3
Vout
C7
4.7
C5
0.1
7
Vcc
LP2950ACZ-3.3
1
8
Vin
3
C4
0.1
Gnd
C6
4.7
2
4
GND
74VHC125 Level Shifter
SW2
middle
SW1
right
9
SW3
left
5
3
10
4
2
1
6
8
14
7
2
Vcc
1
3
C2
0.1
C1
0.1
20
P1.0
VDD3
P0.7* 21
USB Port
VBUS
1
GND
2
D+
D-
P0.6
P0.5*
P1.6
17
P1.7
16
3
15
4
R5
1.30K
22
2
Hi-Z Configuration
P1.3
USB Microcontroller
8
Vcc
D+/SCLK
D-/SDAT
4
24
P0.4*
R9
3
P0.2
P0.3
11
12
XTALOUT
RESET
REFC
P1.4
NPD
R2
20K
P1.5
VPP
LASER_NEN
1
QA
QB
N/C
SW4
ALPS
EC10E
Scroll wheel encoder
R4 20K
Figure 7. Schematic Diagram for 3-Button Scroll Wheel USB PS/2 Mouse - Regulator Bypass
Laser Bin Table
Bin Number
Rbin Resistor Value (kohm)
2A
18.7
3A
12.7
20
OSC_IN
8
X1
Murata
24 MHz CSALS24MOX53-B0
9
RBIN
GUARD
OSC_OUT
Rbin
Selected to
match laser
2
R3 20K
12
XY_LASER
15
13
Vcc
XTALIN/P2.1
GND
N/C
R1
20K
3
10
C9
0.1
C10 to be as close as
possible to VCSEL
D1
VCSEL
C10
470pF
14
5
Vcc
P0.1 2
R6
2.7K
11
C8
2.2
REFB
10 K
7
Q2
2N3906
19
7
R10
4
9
7
MOSI
10 K
P0.0 1
Vreg
6
17
MISO
23
18
13
GND
SCLK
GND
P1.2
C3
0.1
NCS
3
P1.1
6
19
C2
0.1
1
*Outputs configured
as open drain if NOT
using level shifter
ADNS-6090
5
18
VDD3
16
14
Vcc
10
Optional
Ground
Plane
Notes
x Caps for pins 11, 12, 16 and 18 MUST have trace lengths LESS than 5
mm on each side.
x Pins 16 and 18 caps MUST use pin 17 GND.
x Pin 9, if used, should not be connected to PCB GND to reduce
potential RF emissions.
x The 0.1 μF caps must be ceramic.
x Caps should have less than 5 nH of self inductance.
x Caps should have less than 0.2 Ω ESR.
x NC pins should not be connected to any traces.
x Surface mount parts are recommended.
x Care must be taken when interfacing a 5V microcontroller to the
ADNS-6090. Serial port inputs on the sensor should be connected
to open-drain outputs from the microcontroller or use an active
drive level shifter. NPD and RESET should be connected to 5V
microcontroller outputs through a resistor divider or other level
shifting technique.
x VDD3 and GND should have low impedance connections to the
power supply.
x Because the RBIN pin sets the XY_LASER current, the following PC
board layout practices should be followed to reduce the chance
of uncontrolled laser drive current caused from a leakage path
between RBIN and ground. One hypothetical source of such a
leakage path is PC board contamination due to a liquid, such as a
soft drink, being deposited on the printed circuit board.
x The RBIN resistor should be located close to the sensor pin 13. The
traces between the resistor and the sensor should be short.
x The pin 13 solder pad and all exposed conductors connected to pin
13 should be surrounded by a guard trace connected to VDD3 and
devoid of solder mask.
x The pin 13 solder pad, the traces connected to pin 13, and the RBIN
resistor should be covered with a conformal coating.
x The RBIN resistor should be a thru-hole style to increase the distance
between its terminals. This does not apply if a conformal coating is
used.
External PROM
The ADNS-6090 must operate from externally loaded
programming. This architecture enables immediate
adoption of new features and improved performance
algorithms. The external program is supplied by Avago
as a file, which may be burned into a programmable
device. The example application shown in this document
uses an EEPROM to store and load the external program
memory. A micro-controller with sufficient memory may
be used instead. On power-up and reset, the ADNS-6090
program is downloaded into volatile memory using the
burst-mode procedure described in the Synchronous
Serial Port section. The program size is 1986 x 8 bits.
OSC_IN
NCS
RESONATOR
OSCILLATOR
MISO
REFB
IMAGE
PROCESSOR
CTRL
RESET
RBIN
VOLTAGE REGULATOR
AND POWER CONTROL
MOSI
Serial Port
SCLK
OSC_OUT
LASER DRIVER
REFC
REFERENCE
VOLTAGE
FILTER NODE
NPD
V DD3
3.3 V POWER
GND
XY_LASER
LASER_NEN
Figure 8. Block diagram of ADNS-6090 optical mouse sensor
8
LASER Drive Mode
The LASER has 2 modes of operation: DC and Shutter. In
DC mode, the LASER is on at all times the chip is powered
except when in the power down mode via the NPD pin.
In shutter mode the LASER is on only during the portion
of the frame that light is required. The LASER mode is
set by the LASER_MODE bit in the Configuration_bits
register. For optimum product lifetime, Avago recommends the default Shutter mode setting (except for calibration and test).
LASER Output Power
The laser beam output power as measured at the navigation surface plane is specified below. The following conditions apply:
1. The system is adjusted according to the above
procedure.
Eye Safety
The ADNS-6090 and the associated components in the
schematic of Figure 7 are intended to comply with Class
1 Eye Safety Requirements of IEC 60825-1. Avago Technologies suggests that manufacturers perform testing to
verify eye safety on each mouse. It is also recommended
to review possible single fault mechanisms beyond those
described below in the section “Single Fault Detection”.
Under normal conditions, the ADNS-6090 generates the
drive current for the laser diode (ADNV-6340). In order to
stay below the Class 1 power requirements, resistor Rbin
must be set at least as high as the value in the bin table of
Figure 7, based on the bin number of the laser diode and
LP_CFG0 and LP_CFG1 must be programmed to appropriate values. Avago recommends using the exact Rbin value
specified in the bin table to ensure sufficient laser power
for navigation. The system comprised of the ADNS-6090
and ADNV-6340 is designed to maintain the output beam
power within Class 1 requirements over component manufacturing tolerances and the recommended temperature range when adjusted per the procedure below and
when implemented as shown in the recommended application circuit of Figure 7. For more information, please
refer to Application Note AN5088 on the eye safety calculation.
LASER Power Adjustment Procedure
1. The ambient temperature should be 25°C +/- 5°C.
2. Set VDD3 to its permanent value.
3. Ensure that the laser drive is at 100% duty cycle.
4. Program the LP_CFG0 and LP_CFG1 registers to
achieve an output power as close to 506uW as possible
without exceeding it.
Good engineering practices should be used to guarantee
performance, reliability and safety for the product design.
Avago has additional information and detail, such as
Parameter
Symbol
Laser output power
LOP
9
firmware practices, PCB layout suggestions, and manufacturing procedures and specifications that could be
provided.
Minimum
2. The system is operated within the recommended
operating temperature range.
3. The VDD3 value is no greater than 50mV above its value
at the time of adjustment.
4. No allowance for optical power meter accuracy is
assumed.
Disabling the LASER
LASER_NEN is connected to the base of a PNP transistor
which when ON connects VDD3 to the LASER. In normal
operation, LASER_NEN is low. In the case of a fault
condition (ground at XY_LASER or RBIN), LASER_NEN
goes high to turn the transistor off and disconnect VDD3
from the LASER.
Single Fault Detection
ADNS-6090 is able to detect a short circuit, or fault,
condition at the RBIN and XY_LASER pins, which could
lead to excessive laser power output. A low resistance
path to ground on either of these pins will trigger the
fault detection circuit, which will turn off the laser drive
current source and set the LASER_NEN output high.
When used in combination with external components
as shown in the block diagram below, the system will
prevent excess laser power for a single short to ground at
RBIN or XY_LASER by shutting off the laser. Refer to the PC
board layout notes for recommendations to reduce the
chance of high resistance paths to ground existing due to
PC board contamination.
In addition to the continuous fault detection described
above, an additional test is executed automatically
whenever the LP_CFG0 register is written to. This test
will check for a short to ground on the XY_LASER pin, a
short to VDD3 on the XY_LASER pin, and will test the fault
detection circuit on the XY_LASER pin.
Maximum
Units
Notes
716
μW
Per conditions above
VDD3
Microcontroller
ADNS-6090
LASER
DRIVER
LASER_NEN
VDD3
fault control
block
RESET
XY_LASER
voltage sense
NPD
current set
GND
R BIN
Figure 9. Single Fault Detection and Eye-safety Feature Block Diagram
Regulatory Requirements
x Passes FCC B and worldwide analogous emission limits when assembled into a mouse with shielded cable and
following Avago recommendations.
x Passes IEC-1000-4-3 radiated susceptibility level when assembled into a mouse with shielded cable and following
Avago recommendations.
x Passes EN61000-4-4/IEC801-4 EFT tests when assembled into a mouse with shielded cable and following Avago
recommendations.
x UL flammability level UL94 V-0.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Storage Temperature
TS
-40
85
°C
Operating Temperature
TA
-15
55
°C
260
°C
3.7
V
2
kV
All pins, human body model MIL 883
Method 3015
VDD3+0.5
V
NPD, NCS, MOSI, SCLK, RESET, OSC_IN,
OSC_OUT, REFC, RBIN
Lead Solder Temp
Supply Voltage
VDD3
-0.5
ESD
-0.5
Notes
For 10 seconds, 1.6mm below seating plane.
Input Voltage
VIN
Output current
IOUT
7
mA
MISO, LASER_NEN
Input Current
IIN
15
mA
XY_LASER current with RBIN 12.7KΩ
LP_CFG0=0x00; LP_CFG1=0xFF
10
Recommended Operating Conditions
Parameter
Symbol
Minimum
Operating Temperature
TA
0
Power supply voltage
VDD3
3.10
Power supply rise time
VRT
1
Supply noise
(Sinusoidal)
VNB
Oscillator Frequency
fCLK
Serial Port Clock Frequency
fSCLK
Typical
3.30
23
24
10kHz- 300KHZ
300KHz-50MHz
25
MHz
Set by ceramic resonator
2
500
MHz
kHz
Active drive, 50% duty cycle
Open drain drive with pull-ups
on, 50 pF load
65
in/sec
Max limit is based on these
surfaces : White Paper, Photo
Paper, White Formica, Black
Formice, Spruce/White Pine
20
g
7200
Frames/
second
See Frame_Period register
section
See Laser Bin Table in Figure 7
kΩ
Using ADNV-6340 VCSEL
0.7
V
A
Frame Rate
FR
2000
Resistor value for LASER Drive
Current set
Rbin
Voltage at XY_LASER
VXY_LASER
VDD3
VCSEL
11
0 to 3.0V
mV p-p
45
Acceleration
VCSEL Clip
Figure 10. Distance from lens reference plane to surface
μs
30
80
Results in +/- 0.22 mm
minimum DOF, see Figure 10
2.18
Surface
Volts
mm
S
Lens
3.60
Ω
Speed
2.40
0.094
Notes
2.62
Z
Sensor PCB
°C
55
XRES
Distance from lens reference
plane to surface
Sensor
Units
40
2.40
Resonator Impedance
VCSEL PCB
Maximum
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3V, fclk=24MHz.
Parameter
Symbol
Maximum Units
Notes
VDD to RESET
Data delay after RESET
tOP
tPU-RESET
250
180
μs
ms
Input delay after reset
tIN-RST
550
μs
Power Down
tPD
600
μs
Wake from NPD
tPUPD
Data delay after NPD
tCOMPUTE
From VDD = 3.0V to RESET sampled
From RESET falling edge to valid motion
data at 2000 fps and shutter bound 20k.
From RESET falling edge to inputs active
(NPD, MOSI, NCS, SCLK)
From NPD falling edge to initiate the power
down cycle at 2000fps (tPD = 1 frame period
+ 100μs)
From NPD rising edge to valid motion data
at 2000 fps and shutter bound 8610. Max
assumes surface change while NPD is low
From NPD rising edge to all registers contain
data from new images at 2000fps (See
Figure 11).
RESET pulse width
MISO rise time
MISO fall time
MISO delay after SCLK
tPW-RESET
tr-MISO
tf-MISO
tDLY-MISO
10
MISO hold time
MOSI hold time
thold-MISO
thold-MOSI
250
200
ns
ns
MOSI setup time
SPI time between
write commands
tsetup-MOSI
tSWW
120
50
ns
Ps
SPI time between
write and read commands
tSWR
50
Ps
SPI time between read
tSRW
and subsequent commands tSRR
250
ns
SPI read address-data delay tSRAD
50
Ps
SPI motion read
address-data delay
tSRAD-MOT
75
Ps
NCS to SCLK active
tNCS-SCLK
120
ns
SCLK to NCS inactive
tSCLK-NCS
120
ns
NCS to MISO high-Z
tNCS-MISO
PROM download and frame tLOAD
capture byte-to-byte delay
NCS to burst mode exit
tBEXIT
Transient Supply Current
IDDT
Input Capacitance
C IN
12
Minimum Typical
tCOMPUTE 75
ms
3.1
ms
200
200
120
μs
ns
ns
ns
40
40
10
250
ns
Ps
4
Ps
68
14-22
mA
pF
CL = 50pF
CL = 50pF
From SCLK falling edge to MISO data valid,
no load conditions
Data held until next falling SCLK edge
Amount of time data is valid after SCLK
rising edge
From data valid to SCLK rising edge
From rising SCLK for last bit of the first data
byte, to rising SCLK for last bit of the second
data byte.
From rising SCLK for last bit of the first data
byte, to rising SCLK for last bit of the second
address byte.
From rising SCLK for last bit of the first
data byte, to falling SCLK for first bit of the
second address byte.
From rising SCLK for last bit of the address
byte, to falling SCLK for first bit of data
being read. All registers except Motion &
Motion_Burst
From rising SCLK for last bit of the address
byte, to falling SCLK for first bit of data
being read. Applies to 0x02 Motion, and
0x50 Motion_Burst, registers
From NCS falling edge to first SCLK rising
edge
From last SCLK falling edge to NCS rising
edge, for valid MISO data transfer
From NCS rising edge to MISO high-Z state
(See Figure 24 and 25)
Time NCS must be held high to exit burst
mode
Max supply current during a VDD3 ramp
from 0 to 3.67 V
OSC_IN, OSC_OUT
DC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3 V.
Parameter
Symbol
DC Supply Current
IDD_AVG
Power Down Supply Current
IDDPD
Input Low Voltage
VIL
Input High Voltage
VIH
Input hysteresis
VI_HYS
200
Input current, pull-up disabled
IIH_DPU
0
Input current, CMOS inputs
IIH
Output current, pulled-up
inputs
IOH_PU
XY_LASER Current
ILAS
XY_LASER Current (fault mode)
ILAS
Output Low Voltage, MISO,
LASER_NEN
VOL
Output High Voltage, MISO,
LASER_NEN
VOH
XY_LASER Current (no Rbin)
ILAS_NRB
Minimum
Typical
5
Maximum
Units
Notes
53
mA
DC average at 7200 fps. No DC
load on XY_LASER, MISO.
9
μA
NPD=GND; SCLK, MOSI,
NCS=GND or VDD3;
RESET=VDD3
0.8
V
SCLK, MOSI, NPD, NCS, RESET
V
SCLK, MOSI, NPD, NCS, RESET
0.7 * VDD3
150
±10
mV
SCLK, MOSI, NPD, NCS, RESET
μA
Vin = 0.8*VDD3, SCLK, MOSI,
NCS
0
±10
μA
NPD, RESET, Vin=0.8*VDD3
300
600
μA
Vin = 0.2V, SCLK, MOSI, NCS;
See bit 2 in Extended_Config
register
A
VXY_LASER >= 0.7 V
LP_CFG0 = 0x00, LP_CFG1 =
0xFF
500
μA
Rbin < 50 Ohms, or VXY_LASER
− 50 μs
SCLK
Address
Data
Address
Write Operation
Data
Write Operation
Figure 20. Timing between two write commands
If the rising edge of the SCLK for the last data bit of the second write command occurs before the 50 microsecond
required delay, then the first write command may not complete correctly.
t SWR
50 s
SCLK
Address
Data
Address
Write Operation
Next Read
Operation
Figure 21. Timing between write and read commands
If the rising edge of SCLK for the last address bit of the read command occurs before the 50 microsecond required
delay, the write command may not complete correctly.
tSRAD − 1 frame
period
SCLK
t NCS -SCLK
>120ns
>− 40 μs
t LOAD
>− 10 μs
t LOAD
>− 10 μs
>− 10 μs
soonest to read SROM_ID
Figure 24. PROM Download Burst Mode
19
100 μs
Frame Capture
This is a fast way to download a full array of pixel values from a single frame. This mode disables navigation and
overwrites any downloaded firmware. A hardware reset is required to restore navigation, and the firmware must be
reloaded.
To trigger the capture, write to the Frame_Capture register. The next available complete 1 2/3 frames (1536 values) will
be stored to memory. The data are retrieved by reading the Pixel_Burst register once using the normal read method,
after which the remaining bytes are clocked out by driving SCLK at the normal rate. The byte time must be at least
tLOAD. If the Pixel_Burst register is read before the data is ready, it will return all zeros.
To read a single frame, read a total of 900 bytes. The next 636 bytes will be approximately 2/3 of the next frame. The
first pixel of the first frame (1st read) has bit 6 set to 1 as a start-of-frame marker. The first pixel of the second partial
frame (901st read) will also have bit 6 set to 1. All other bytes have bit 6 set to zero. The MSB of all bytes is set to 1. If
the Pixel_Burst register is read past the end of the data (1537 reads and on) , the data returned will be zeros. Pixel data
is in the lower six bits of each byte.
After the download is complete, the micro-controller must raise the NCS line for at least tBEXIT to terminate burst
mode. The read may be aborted at any time by raising NCS. Alternatively, the frame data can also be read one byte at a
time from the Frame_Capture register. See the register description for more information.
exit burst mode
t BEXIT >− 4 μs
NCS
frame capture reg write
MOSI
address
data
frame capture reg
address
pixel dump reg read
address
enter burst
mode
soonest to begin again
>− 10 μs
SCLK
t NCS -SCLK
>120ns
t CAPTURE
t SRAD >− 50 μs
MISO
t LOAD
>− 10 μs
P0
P0 bit 6 set to 1
t LOAD
>− 10 μs
P1
P899
all MSB = 1
see note 2
Notes:
1. MSB = 1 for all bytes. Bit 6 = 0 for all bytes except pixel 0 of both frames which has bit 6 = 1 for use as a frame marker.
2. Reading beyond pixel 899 will return the first pixel of the second partial frame.
3. tCAPTURE = 10 μs + 3 frame periods.
4. This figure illustrates reading a single complete frame of 900 pixels. An additional 636 pixels from the next frame are available.
Figure 25. Frame capture burst mode timing
20
The pixel output order as related to the surface is shown below.
Cable
Top V iew of Mouse
Positive Y
LB
RB
Positive X
1
A6090
10
11
Expanded view of the
surface as viewed
through the lens
last output
899 898 897 896 895 894 893 892 891 890 889 888 887 886 885 884 883 882 881 880 879 878 877 876 875 874 873 872 871 870
869 868 867 866 865 864 863 862 861 860 859 858 857 856 855 854 853 852 851 850 849 848 847 846 845 844 843 842 841 840
839 838
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
etc.
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
first output
Figure 26. Pixel address map of navigation surface image (Sensor looking at the navigation surface through the ADNS-6120/ADNS-6130-001 lens from the top
of mouse)
Error detection and recovery
1. The ADNS-6090 and the micro-controller might get
out of synchronization due to ESD events, power
supply droops or micro-controller firmware flaws. In
such a case, the micro-controller should pulse NCS
high for at least 1μs. The ADNS-6090 will reset the
serial port (but not the control registers) and will be
prepared for the beginning of a new transmission
after the normal transaction delay.
2. Invalid addresses: Writing to an invalid address will
have no effect. Reading from an invalid address will
return all zeros.
3. Termination of a transmission by the micro-controller
may sometimes be required (for example, due to a
USB suspend interrupt during a read operation). To
accomplish this, the micro-controller should raise NCS.
The ADNS-6090 will not write to any register and will
reset the serial port (but not the control registers) and
be prepared for the beginning of future transmissions
after NCS goes low. The normal delays between reads
or writes (tSWW, tswr, tSRAD, tSRAD-mot) are still required
after aborted transmissions.
21
4. The micro-controller can verify success of write
operations by issuing a read command to the same
address and comparing written data to read data.
5. The micro-controller can verify the synchronization of
the serial port by periodically reading the product ID
and inverse product ID registers.
6. The microcontroller can read the SROM_ID register
to verify that the sensor is running downloaded
PROM code. ESD or similar noise events may cause
the sensor to revert to native ROM execution. If this
should happen, pulse RESET and reload the SROM
code.
Notes on Power-up and the serial port
Power Down Circuit
Reset Circuit
The following table lists the pin states during power
down.
The ADNS-6090 does not perform an internal power up
self-reset; the reset pin must be raised and lowered to
reset the chip. This should be done every time power is
applied. During power-up there will be a period of time
after the power supply is high but before any clocks are
available. The table below shows the state of the various
pins during power-up and reset when the RESET pin is
driven high by a micro-controller.
State of Signal Pins After VDD is Valid
State of Signal Pins During Power Down
Pin
NPD low
After wake from PD
SPI pull-ups
off
pre-PD state
NCS
hi-Z control
functional
functional
MISO
low or hi-Z
(per NCS)
pre-PD state
or hi-Z
SCLK
ignored
functional
Pin
Before Reset
During Reset
After Reset
MOSI
ignored
functional
SPI pullups
undefined
off
on (default)
XY_LASER
high (off )
functional
RESET
functional
functional
NCS
hi-Z control
functional
hi-Z control
functional
functional
NPD
low (driven
externally)
functional
MISO
driven or hi-Z
(per NCS)
driven or hi-Z
(per NCS)
low or hi-Z
(per NCS)
REFC
VDD3
REFC
SCLK
undefined
ignored
functional
MOSI
undefined
ignored
functional
XY_LASER
undefined
hi-Z
functional
RESET
functional
high (externally driven)
functional
NPD
undefined
ignored
functional
LASER_
NEN
undefined
high (off )
functional
22
OSC_IN
low
OSC_IN
OSC_OUT
high
OSC_OUT
LASER_NEN
high (off )
functional
The chip is put into the power down (PD) mode by lowering
the NPD input. When in PD mode, the oscillator is stopped but
all register contents are retained. To achieve the lowest current
state, all inputs must be held externally within 200mV of a rail,
either ground or VDD3. The chip outputs are driven low or hi-Z
during PD to prevent current consumption by an external load.
Registers
The ADNS-6090 registers are accessible via the serial port. The registers are used to read motion data and status as
well as to set the device configuration.
Address
Register
Read/Write
Default Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17-0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
0x1f
0x20-0x2b
0x2c
0x2d
0x2e-0x3c
0x3d
0x3e
0x3f
0x40
0x50
0x60
Product_ID
Revision_ID
Motion
Delta_X
Delta_Y
SQUAL
Pixel_Sum
Maximum_Pixel
Reserved
Resolution
Configuration_bits
Extended_Config
Data_Out_Lower
Data_Out_Upper
Shutter_Lower
Shutter_Upper
Frame_Period_Lower
Frame_Period_Upper
Motion_Clear
Frame_Capture
SROM_Enable
Reserved
Configuration II
Reserved
Frame_Period_Max_Bound Lower
Frame_Period_Max_Bound_Upper
Frame_Period_Min_Bound_Lower
Frame_Period_Min_Bound_Upper
Shutter_Max_Bound_Lower
Shutter_Max_Bound_Upper
SROM_ID
Reserved
LP_CFG0
LP_CFG1
Reserved
Observation
Reserved
Inverse Product ID
Pixel_Burst
Motion_Burst
SROM_Load
R
R
R
R
R
R
R
R
0x1C
0x20
0x25
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R
R
R
R
R
R
W
R/W
W
0x04
0x5D
0x08
Any
Any
0x85
0x00
Any
Any
Any
0x00
0x00
R/W
0x34
R/W
R/W
R/W
R/W
R/W
R/W
R
0x90
0x65
0x7E
0x0E
0x20
0x4E
Version dependent
R/W
R/W
0x7F
0x80
R/W
0x80
R
R
R
W
0xE3
0x00
0x00
Any
23
Product_ID
Address: 0x00
Access: Read
Default Value: 0x1C
Bit
7
6
5
4
3
2
1
0
Field
PID7
PID6
PID5
PID4
PID3
PID2
PID1
PID0
Data Type:
8-Bit unsigned integer
Usage:
This register contains a unique identification assigned to the ADNS-6090. The value in this
register does not change; it can be used to verify that the serial communications link is functional.
Revision_ID
Address: 0x01
Access: Read
Default Value: 0x20
Bit
7
6
5
4
3
2
1
0
Field
RID7
RID6
RID5
RID4
RID3
RID2
RID1
RID0
Data Type:
8-Bit unsigned integer
Usage:
This register contains the IC revision. It is subjected to change when new IC versions are
released.
Note: The downloaded SROM firmware revision is a separate value and is available in the
SROM_ID register.
24
Motion
Address: 0x02
Access: Read
Default Value: 0x20
Bit
7
6
5
4
3
2
1
0
Field
MOT
Reserved
LP_Valid
OVF
Reserved
Reserved
Fault
Reserved
Data Type:
Bit field.
Usage:
Register 0x02 allows the user to determine if motion has occurred since the last time it was
read. If so, then the user should read registers 0x03 and 0x04 to get the accumulated motion.
It also tells if the motion buffers have overflowed, if fault is detected and the current resolution
setting.
Field Name
Description
MOT
Motion since last report
0 = No motion
1 = Motion occurred, data ready for reading in Delta_X and Delta_Y
registers
LP_Valid
This bit is an indicator of complementary value contained in registers
0x2C and 0X2D.
0 = register 0x2C and 0x2D do not have complementary values
1 = register 0x2C and 0x2D contain complementary values
OVF
Motion overflow, ΔY and/or ΔX buffer has overflowed since last report
0 = no overflow
1 = overflow has occurred
Fault
Indicates that the RBIN and/or XY_LASER pin is shorted to GND.
0 = no fault detected
1 = fault detected
Notes for Motion:
1. Reading this register freezes the Delta_X and Delta_Y register values. Read this register
before reading the Delta_X and Delta_Y registers. If Delta_X and Delta_Y are not read before
the motion register is read a second time, the data in Delta_X and Delta_Y will be lost.
2. Avago RECOMMENDS that registers 0x02, 0x03 and 0x04 to be read sequentially.
See Motion burst mode also.
3. Internal buffers can accumulate more than eight bits of motion for X or Y. If one of the
internal buffers overflows, then absolute path data is lost and the OVF bit is set. This bit is
cleared once some motion has been read from the Delta_X and Delta_Y registers, and if the
buffers are not at full scale. Since more data is present in the buffers, the cycle of reading
the Motion, Delta_X and Delta_Y registers should be repeated until the motion bit (MOT) is
cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either positive
or negative full scale. If the motion register has not been read for long time, at 800 cpi it
may take up to 32 read cycles to clear the buffers, at 1600 cpi, up to 64 cycles and so on. Alternatively, writing to the Motion_Clear register (register 0x12) will clear all stored motion at
once.
25
Delta_X
Address: 0x03
Access: Read
Default Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
X7
X6
X5
X4
X3
X2
X1
X0
Data Type:
Eight bit 2’s complement number.
Usage:
X movement is the counts since last report. Absolute value is determined by resolution.
Reading clears the register.
Motion
-128
-127
-2
-1
0
+1
+2
+126
+127
Delta_X
80
81
FE
FF
00
01
02
7E
7F
Delta_Y
Address: 0x04
Access: Read
Default Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data Type:
Eight bit 2’s complement number.
Usage:
Y movement is the counts since last report. Absolute value is determined by resolution.
Reading clears the register.
26
Motion
-128
-127
-2
-1
0
+1
+2
+126
+127
Delta_Y
80
81
FE
FF
00
01
02
7E
7F
SQUAL
Address: 0x05
Access: Read
Default Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SQ7
SQ6
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Data Type:
Upper 8 bits of a 10-bit unsigned integer.
Usage:
SQUAL (Surface Quality) is a measure of ¼ of the number of valid* features visible by the sensor
in the current frame. Use the following formula to find the total number of valid features.
Number of features = SQUAL register value x 4
The maximum SQUAL register value is 169. Since small changes in the current frame can result
in changes in SQUAL, variations in SQUAL when looking at a surface are expected. The graph
below shows 900 sequentially acquired SQUAL values, while a sensor was moved slowly over
white paper. SQUAL is nearly equal to zero if there is no surface below the sensor. SQUAL
remains fairly high throughout the Z-height range which allows illumination of most pixels in
the sensor.
SQUAL Values (White Paper)
At Z=0mm, Circle@7.5" diameter, Speed-6ips
SQUAL Value (Counts)
100
80
60
40
20
0
1
51
101 151 201 251 301 351
401 451 501 551 601 651 701 751 801 851
Count
Figure 27. SQUAL Values at 3000cpi (White Paper)
Mean SQUAL vs. Z (White Paper)
3000dpi, Circle@7.5" diameter, Speed-6ips
120
Avg-3sigma
SQUAL (Counts)
100
Avg
80
Avg+3sigma
60
40
20
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
Distance from Lens Reference Plane to Surface, Z (mm)
Figure 28. Mean SQUAL vs. Z (White Paper)
27
3.4
3.6
Pixel_Sum
Address: 0x06
Access: Read
Default Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
AP7
AP6
AP5
AP4
AP3
AP2
AP1
AP0
Data Type:
High 8 bits of an unsigned 16-bit integer.
Usage:
This register is used to find the average pixel value. It reports the upper byte of a 16-bit counter
which sums all 900 pixels in the current frame. It may be described as the full sum divided by
256. To find the average pixel value, use the following formula:
Average Pixel = Register Value x 256 / 900 = Register Value / 3.51
The maximum register value is 221 (63 * 900/256 truncated to an integer). The minimum is 0.
The pixel sum value can change on every frame.
Maximum_Pixel
Address: 0x07
Access: Read
Default Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
0
0
MP5
MP4
MP3
MP2
MP1
MP0
Data Type:
6-bit number.
Usage:
Maximum Pixel value in current frame. Minimum value = 0, maximum value = 63. The
maximum pixel value can vary with every frame.
Reserved
Address: 0x08
Resolution
Address: 0x09
Access: Read/Write
Default Value: 0x04
Bit
7
6
5
4
3
2
1
0
Field
0
0
0
0
0
RES2
RES1
RES0
Data Type:
3-bit number
Usage:
This register sets the resolution in unit of counts per inch. Resolution values are approximate.
The performance of setting is surface dependent.
28
Field Name
Description
RES 2-0
CPI
800
1200
1600
2000
2400
3000
RES2-0
010
011
100
101
110
111
Configuration_bits
Address: 0x0a
Access: Read/Write
Default Value: 0x5D
Bit
7
6
5
4
3
2
1
0
Field
0
LASER_MODE
Sys_Test
1
1
1
Reserved
Reserved
Data Type:
Bit field
Usage:
Register 0x0a allows the user to change the configuration of the sensor. Shown below are the
bits, their default values, and optional values.
Field Name
Description
BIT 7
Must always be zero
LASER_MODE
LASER Shutter Mode
0 = Shutter mode off (LASER always on)
1 = Shutter mode on (LASER only on when illumination is required)
Sys_Test
System Tests
0 = no tests
1 = perform all system tests, output 16 bit CRC via Data_Out_Upper and
Data_Out_Lower registers.
NOTE:
The test will fail if SROM is loaded. Perform a hardware reset before
executing this test. Reload SROM after the test is completed.
The test will fail if a laser fault condition exists.
Since part of the system test is a RAM test, the RAM and SROM will be overwritten with the default values when the test is done. If any configuration
changes from the default are needed for operation, make the changes AFTER
the system test is run. The system test takes 200ms (@24MHz) to complete.
Do not access the Synchronous Serial Port during system test.
29
Extended_Config
Address: 0x0b
Access: Read/Write
Default Value: 0x08
Bit
7
6
5
4
3
2
1
0
Field
Busy
Reserved
Reserved
Reserved
1
Serial_NPU
NAGC
Fixed_FR
Data Type:
Bit field
Usage:
Register 0x0b allows the user to change the configuration of the sensor. Shown below are the
bits, their default values, and optional values.
30
Field Name
Description
Busy
Read-only bit. Indicates if it is safe to write to one or more of the following
registers:
Frame_Period_Max_Bound_Upper and Frame_Period_Max_Bound_Lower
Frame_Period_Min_Bound_Upper and Frame_Period_Min_Bound_Lower
Shutter_Max_Bound_Upper and Shutter_Max_Bound_Lower
After writing to the Frame_Period_Maximum_Bound_Upper register, at least
two frames must pass before writing again to any of the above registers.
This bit may be used in lieu of a timer since the actual frame rate may not be
known when running in auto mode.
0 = writing to the registers is allowed
1 = do not write to the registers yet
Bit 3
Must always be one
Serial_NPU
Disable serial port pull-up current sources on SCLK, MOSI and NCS
0 = no, current sources are on
1 = yes, current sources are off
NAGC
Disable AGC. Shutter will be set to the value in the Shutter_Maximum_Bound
registers.
0 = no, AGC is active
1 = yes, AGC is disabled
Fixed_FR
Fixed frame rate (disable automatic frame rate control). When this bit is
set, the frame rate will be determined by the value in the Frame_Period_
Maximum_Bound registers.
0 = automatic frame rate
1 = fixed frame rate
Data_Out_Lower
Address: 0x0c
Access: Read
Default Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Data_Out_Upper
Address: 0x0d
Access: Read
Default Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
DO15
DO14
DO13
DO12
DO11
DO10
DO9
DO8
Data Type:
16-bit word.
USAGE:
Data in these registers come from the system self test or the SROM CRC test. The data can be
read out in either order.
Data_Out_Upper
Data_Out_Lower
System test results:
0xA9
0xD5
SROM CRC Test Result:
0xBE
0xEF
System Test: This test is initiated via the Configuration_Bits register. It performs several tests to
verify that the hardware is functioning correctly. Perform a hardware reset just prior to running
the test. SROM contents and register settings will be lost.
SROM Content: Performs a CRC on the SROM contents. The test is initiated by writing a particular
value to the SROM_Enable register.
31
Shutter_Lower
Address: 0x0e
Access: Read
Default Value: 0x85
Bit
7
6
5
4
3
2
1
0
Field
S7
S6
S5
S4
S3
S2
S1
S0
Shutter_Upper
Address: 0x0f
Access: Read
Default Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
S15
S14
S13
S12
S11
S10
S9
S8
Data Type:
16-bit unsigned integer.
Usage:
Units are clock cycles. Read Shutter_Upper first, then Shutter_Lower. They should be read
consecutively. The shutter is adjusted to keep the average and maximum pixel values within
normal operating ranges. The shutter value is checked and automatically adjusted to a new
value if needed on every frame when operating in default mode. When the shutter adjusts,
it changes by ± 1/16 of the current value. The shutter value can be set manually by setting
the AGC mode to Disable using the Extended_Config register and writing to the Shutter_Max_
Bound registers. Because the automatic frame rate feature is related to shutter value it may also
be appropriate to enable the Fixed Frame Rate mode using the Extended_Config register.
Shown below is a graph of 900 sequentially acquired shutter values, while the sensor was
moved slowly over white paper.
Shutter Values (White Paper)
At Z=0mm, Circle@7.5" diameter, Speed-6ips
160
Shutter value
140
120
100
80
60
40
20
0
1
51 101 151 201 251 301 351 401 451 501 551 601 651 701 751 801 851
Count
Figure 29. Shutter Values at 3000cpi (White Paper)
Mean Shutter vs Z (White paper)
3000cpi, Circle@7.5" diameter, Speed-6ips
Shutter value (Counts)
250
Avg-3sigma
200
Avg
150
Avg+3sigma
100
50
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Distance from Lens Reference Plane to Surface, Z (mm)
Figure 30. Mean Shutter vs. Z (White Paper)
The maximum value of the shutter is dependent upon the setting in the Shutter_Max_Bound_
Upper and Shutter_Max_Bound_Lower registers.
32
Frame_Period_Lower
Address: 0x10
Access: Read
Default Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
Frame_Period_Upper
Address: 0x11
Access: Read
Default Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
Data Type:
16-bit unsigned integer.
Usage:
Read these registers to determine the current frame period and to calculate the frame rate.
Units are clock cycles. The formula is:
Frame Rate = Clock Frequency / Register value
To read from the registers, read Frame_Period_Upper first followed by Frame_Period Lower.
To set the frame rate manually, disable automatic frame rate mode via the Extended_Config
register and write the desired count value to the Frame_Period_Max_Bound registers.
The following table lists some Frame_Period values for popular frame rates with a 24MHz clock.
Counts
Frame_Period
Frames/second
Decimal
Hex
Upper
Lower
7200
3,333
0D05
0D
05
5000
4,800
12C0
12
C0
3000
8,000
1F40
1F
40
2000
12,000
2EE0
2E
E0
Motion_Clear
Address: 0x12
Access: Write
Default Value: Undefined
Data Type:
Any.
Usage:
Writing any value to this register will cause the Delta_X, Delta_Y, and internal motion registers
to be cleared. Use this as a fast way to reset the motion counters to zero without resetting the
entire chip.
33
Frame_Capture
Address: 0x13
Access: Read/Write
Default Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
Data Type:
Bit field.
Usage:
Writing 0x83 to this register will cause the next available complete 1 2/3 frames of pixel values
to be stored to SROM RAM. Writing to this register is required before using the Frame Capture
burst mode to read the pixel values (see the Synchronous Serial Port section for more details).
Writing to this register will stop navigation and cause any firmware loaded in the SROM to
be overwritten. A hardware reset is required to restore navigation, and the firmware must be
reloaded using the PROM Download burst method.
This register can also be used to read the frame capture data. The same data available by
reading the Pixel_Burst register using burst mode is available by reading this register in the
normal fashion. The data pointer is automatically incremented after each read so all 1536 pixel
values (1 and 2/3 frames) may be obtained by reading this register 1536 times in a row. Both
methods share the same pointer such that reading pixel values from this register will increment
the pointer causing subsequent reads from the Pixel_Burst register (without initiating a new
frame dump) to start at the current pointer location. This register will return all zeros if read
before the frame capture data is ready. See the Frame Capture description in the Synchronous
Serial Port section for more information.
This register will not retain the last value written. Reads will return zero or frame capture data.
SROM_Enable
Address: 0x14
Access: Write
Default Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0
Data Type:
8-bit number.
Usage:
Write to this register to start either PROM download or SROM CRC test.
Write 0x1D to this register, wait at least 1 frame period, and write 0x18 to this register before
downloading PROM firmware to the SROM_Load register. The download will not be successful
unless this sequence is followed. See the Synchronous Serial port section for details.
Write 0xA1 to start the SROM CRC test. Wait 7ms plus one frame period, then read result
from the Data_Out_Lower and Data_Out_Upper registers. Navigation is halted and the SPI
port should not be used during this test. Avago recommends reading the Motion register to
determine the laser fault condition before performing the SROM CRC test. Executing the test
under a fault condition will cause all subsequent register reads to return zero until the sensor is
reset or the fault is corrected.
34
Reserved
Address: 0x15
Configuration II
Address: 0x16
Access: Read/Write
Default Value: 0x34
Bit
7
6
5
4
3
2
1
0
Field
Reserved
Reserved
Reserved
Reserved
Reserved
1
Force_
disable
Reserved
Data Type
: Bit field
Usage
: Write to this register
Field Name
Reserved
35
Description
Bit-2
Must be always one
Force_disable
0 = LASER_NEN functions as normal
1 = LASER_NEN output high. May be useful for product test.
Address: 0x17-0x18
Frame_Period_Max_Bound_Lower
Address: 0x19
Access: Read/Write
Default Value: 0x90
Bit
7
6
5
4
3
2
1
0
Field
FBM7
FBM6
FBM5
FBM4
FBM3
FBM2
FBM1
FBM0
Frame_Period_Max_Bound_Upper
Address: 0x1A
Access: Read/Write
Default Value: 0x65
Bit
7
6
5
4
3
2
1
0
Field
FBM15
FBM14
FBM13
FBM12
FBM11
FBM10
FBM9
FBM8
Data Type:
16-bit unsigned integer.
Usage:
This value sets the maximum frame period (the MINIMUM frame rate) which may be selected
by the automatic frame rate control, or sets the actual frame period when operating in manual
mode. Units are clock cycles. The formula is:
Frame Rate = Clock Frequency / Register value
To read from the registers, read Upper first followed by Lower. To write to the registers, write
Lower first, followed by Upper. To set the frame rate manually, disable automatic frame rate
mode via the Extended_Config register and write the desired count value to these registers.
Writing to the Frame_Period_Max_Bound_Upper and Lower registers also activates any new
values in the following registers:
x Frame_Period_Max_Bound_Upper and Lower
x Frame_Period_Min_Bound_Upper and Lower
x Shutter_Max_Bound_Upper and Lower
Any data written to these registers will be saved but will not take effect until the write to the
Frame_Period_Max_Bound_Upper and Lower is complete. After writing to this register, two
complete frame times are required to implement the new settings. Writing to any of the above
registers before the implementation is complete may put the chip into an undefined state
requiring a reset. The “Busy” bit in the Extended_Config register may be used in lieu of a timer
to determine when it is safe to write. See the Extended_Config register for more details.
The following table lists some Frame_Period values for popular frame rates (clock rate = 24MHz).
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
36
Counts
Frame_Period
Frames/
second
Decimal
Hex
Upper
Lower
7200
3,333
0D05
0D
05
5000
4,800
12C0
12
C0
3000
8,000
1F40
1F
40
2000
12,000
2EE0
2E
E0
Frame_Period_Min_Bound_Lower
Address: 0x1B
Access: Read/Write
Default Value: 0x7E
Bit
7
6
5
4
3
2
1
0
Field
FBm7
FBm6
FBm5
FBm4
FBm3
FBm2
FBm1
FBm0
Frame_Period_Min_Bound_Upper
Address: 0x1C
Access: Read/Write
Default Value: 0x0E
Bit
7
6
5
4
3
2
1
0
Field
FBm15
FBm14
FBm13
FBm12
FBm11
FBm10
FBm9
FBm8
Data Type:
16-bit unsigned integer.
Usage:
This value sets the minimum frame period (the MAXIMUM frame rate) which may be selected
by the automatic frame rate control. Units are clock cycles. The formula is:
Frame Rate = Clock Rate / Register value
To read from the registers, read Upper first followed by Lower. To write to the registers, write
Lower first, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper
and Lower registers. The minimum allowed write value is 0x0D05; the maximum is 0xFFFF.
Reading this register will return the most recent value that was written to it. However, the value
will take effect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers.
After writing to Frame_Period_Max_Bound_Upper, wait at least two frame times before writing
to Frame_Period_Min_Bound_Upper or Lower again. The “Busy” bit in the Extended_Config
register may be used in lieu of a timer to determine when it is safe to write. See the Extended_
Config register for more details.
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
37
Shutter_Max_Bound_Lower
Address: 0x1D
Access: Read/Write
Default Value: 0x20
Bit
7
6
5
4
3
2
1
0
Field
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
Shutter_Max_Bound_Upper
Address: 0x1E
Access: Read/Write
Default Value: 0x4E
Bit
7
6
5
4
3
2
1
0
Field
SB15
SB14
SB13
SB12
SB11
SB10
SB9
SB8
Data Type:
16-bit unsigned integer.
Usage:
This value sets the maximum allowable shutter value when operating in automatic mode. Units
are clock cycles. Since the automatic frame rate function is based on shutter value, the value
in these registers can limit the range of the frame rate control. To read from the registers, read
Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper,
then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. To set the
shutter manually, disable the AGC via the Extended_Config register and write the desired value
to these registers.
Reading this register will return the most recent value that was written to it. However, the value
will take effect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers.
After writing to Frame_Period_Max_Bound_Upper, wait at least two frame times before writing
to Shutter_Max_Bound_Upper or Lower again. The “Busy” bit in the Extended_Config register
may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config
register for more details.
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.
38
SROM_ID
Address: 0x1F
Access: Read
Default Value: Version dependent
Bit
7
6
5
4
3
2
1
0
Field
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
Data Type:
8-Bit unsigned integer.
Usage:
Contains the revision of the downloaded Shadow ROM firmware. If the firmware has been successfully downloaded and the chip is operating out of SROM, this register will contain the SROM
firmware revision; otherwise it will contain 0x00.
Note: The IC hardware revision is available by reading the Revision_ID register (register 0x01).
LP_CFG0
Address: 0x2C
Access: Read/Write
Default Value: 0x7F
Bit
7
6
5
4
3
2
1
0
Field
0
LP6
LP5
LP4
LP3
LP2
LP1
LP0
Data Type:
8-bit unsigned integer
Usage:
This register is used to set the laser current. It is to be used together with register 0X2D where
register 0X2D must contain the complement of register 0X2C in order for the laser current to be
programmed. Writing to this register causes a fault test to be performed on the XY_LASER pin.
The test checks for stuck low and stuck high conditions. During the test, LASER_NEN will be
driven high and XY_LASER will pulse high for 12us and pulse low for 12us (times are typical).
Both pins will return to normal operation if no fault is detected.
Field Name
Description
Bit-7
Must be always 0
LP6 – LP0
Controls the 7 bit DAC for adjusting laser current.
One step is equivalent to (1/192)*100% = 0.5208% drop of relative laser
current.
Refer to the table below for example of relative laser current settings.
LP6– LP3
39
LP2
LP1
LP0
Relative Laser Current
0000
0
0
0
100%
0000
0
0
1
99.48%
0000
0
1
0
98.96%
0000
0
1
1
98.43%
0000
1
0
0
97.92%
:
:
:
:
:
1111
1
0
1
34.90%
1111
1
1
0
34.38%
1111
1
1
1
33.85%
LP_CFG1
Address: 0x2D
Access: Read/Write
Default Value: 0x80
Bit
7
6
5
4
3
2
1
0
Field
LPC7
LPC6
LPC5
LPC4
LPC3
LPC2
LPC1
LPC0
Data Type:
8-bit unsigned integer
Usage:
The value in this register must be a complement of register 0x2C for laser current to be as programmed; otherwise the laser current is set to 33.85%. Registers 0x2C and 0x2D may be written
in any order after power ON reset or SROM download.
Reserved
Address: 0x2E-0x3C
Observation
Address: 0x3D
Access: Read/Write
Default Value: 0x80
Bit
7
6
5
4
3
2
1
0
Field
OB7
Reserved
OB5
Reserved
Reserved
Reserved
OB1
OB0
OB0
Data Type:
Bit field
Usage:
Each bit is set by some processes or actions at regular intervals, or when the event occurs. The
user must clear the register by writing 0x00, wait for at least a frame period delay, and read the
register. The active processes will have set their corresponding bit(s). This register may be used
as part of a recovery scheme to detect a problem caused by EFT/B or ESD.
Reserved
40
Field Name
Description
OB7
0 = Chip is not running SROM code ,- 1 = Chip is running
SROM code
OB5
0 = NPD pulse was not detected,- 1 = NPD pulse was detected
OB1
Set once per frame
OB0
Set once per frame
Address: 0x3E
Inverse_Product_ID
Address: 0x3F
Access: Read
Default Value: 0xE3
Bit
7
6
5
4
3
2
1
0
Field
NPID7
NPID6
NPID5
NPID4
NPID3
NPID2
NPID1
NPID0
Data Type:
Inverse 8-Bit unsigned integer
Usage:
This value is the inverse of the Product_ID, located at the inverse address. It can be used to test
the SPI port.
Pixel_Burst
Address: 0x40
Access: Read
Default Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Data Type:
Eight bit unsigned integer
Usage:
The Pixel_Burst register is used for high-speed access to all the pixel values from one and 2/3
complete frame. See the Synchronous Serial Port section for use details.
Motion_Burst
Address: 0x50
Access: Read
Default Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
Data Type:
Various, depending on data
Usage:
The Motion_Burst register is used for high-speed access to the Motion, Delta_X, Delta_Y, SQUAL,
Shutter_Upper, Shutter_Lower and Maximum_Pixel registers. See the Synchronous Serial Port
section for use details.
SROM_Load
Address: 0x 60
Access: Write
Default Value: N/A
Bit
7
6
5
4
3
2
1
0
Field
SL7
SL6
SL5
SL4
SL3
SL2
SL1
SL0
Data Type:
8-bit unsigned integer
Usage:
The SROM_Load register is used for high-speed programming of the ADNS-6090 from an
external PROM or microcontroller. See the Synchronous Serial Port section for use details.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved.
AV02-1362EN - June 17, 2010
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