QCPL-341H-500E

Avago Confidential Preliminary Datasheet 1.0 19 Feb 2013 QCPL-341H 2.5 Amp Output Current IGBT Gate Drive Optocoupler Preliminary Data Sheet Description Features The QCPL-341H contains an AlGaAs LED, which is optically coupled to an integrated circuit with a power output stage. This optocoupler is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and high peak output current supplied by this optocoupler make it ideally suited for direct driving IGBT with ratings up to 1200V/100A. For IGBTs with higher ratings, this optocoupler can be used to drive a discrete power stage which drives the IGBT gate. The QCPL-341H has the highest insulation voltage of VIORM= 630Vpeak in the IEC/ EN/DIN EN 60747-5-5. Functional Diagram 1 8 VCC ANODE 2 7 VOUT CATHODE 3 6 VOUT 5 VEE NC NC 4     2.5 A maximum peak output current 2.0 A minimum peak output current Rail-to-rail output voltage 300 ns maximum propagation delay  200 ns maximum propagation delay difference  LED current input with hysteresis  25 kV/µs minimum Common Mode Rejection (CMR) at VCM = 1500 V ICC = 5.0 mA maximum supply current Under Voltage Lock-Out protection (UVLO) with hysteresis Wide operating VCC Range: 15 to 30 V Industrial temperature range: -40 °C to 105 °C Safety Approval Pending UL Recognized 3750/5000 VRMS for 1min. CSA IEC/EN/DIN EN 60747-5-5 VIORM = 630 Vpeak      Applications      IGBT/MOSFET gate drive AC and Brushless DC motor drives Renewable energy inverters Industrial inverters Switching power supp Note: Design Note: A 1 μF bypass capacitor must be connected between pins VCC and VEE. ssss Truth Table VCC – VEE VCC – VEE “POSITIVE GOING” “NEGATIVE GOING” VO (i.e., TURN-ON) (i.e., TURN-OFF) OFF 0 - 30 V 0 – 30 V LOW ON 0 – 12.1V 0 – 11.1V LOW ON 12.1 - 13.5V 11.1 – 12.4V TRANSITION ON 13.5 – 30V 12.4 – 30V HIGH LED CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. Avago Confidential Preliminary Datasheet 1.0 19 Feb 2013 Ordering Information QCPL-341H is UL Recognized with 3750 VRMS for 1 minute per UL1577. QCPL-341H -000E -300E -500E -060E -360E -560E Package 300mil DIP-8 X X X X IEC/EN/DIN EN 60747-5-5 RoHS Compliant Tape& Reel Part number Surface Mount Gull Wing Option X X X X X Quantity 50 per tube 50 per tube 1000 per reel 50 per tube 50 per tube 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: QCPL-341H-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: QCPL-341H-000E to order product of 300 mil DIP package in Tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. Avago Confidential Preliminary Datasheet 1.0 Package Outline Drawings QCPL-341H Outline Drawing (Standard DIP Package) QCPL-341H Gull Wing Surface Mount Option 300 Outline Drawing This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. 19 Feb 2013 Avago Confidential Preliminary Datasheet 1.0 19 Feb 2013 Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non- Halide Flux should be used. Regulatory Information The QCPL-341H is pending approval by the following organizations: UL Recognized under UL 1577, component recognition program, category, File E55361 up to VISO = 3750 VRMS. CSA CSA Component Acceptance Notice #5, File CA 88324 IEC/EN/DIN EN 60747-5-5 (Option 060 Only) Maximum Working Insulation Voltage VIORM = 630Vpeak Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060 – Under Evaluation) Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage  150 Vrms for rated mains voltage  300 Vrms for rated mains voltage  450 Vrms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage tini = 60 sec) Safety-limiting values – maximum values allowed in the event of a failure Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V Symbol QCPL-341H Option 060 Unit VIORM I – IV I – IV I – III 55/105/21 2 630 Vpeak VPR 1181 Vpeak VPR 1008 Vpeak VIOTM 6000 Vpeak TS IS, INPUT PS, OUTPUT RS 175 230 600 >109 °C mA mW  * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Surface mount classification is Class A in accordance with CECC 00802. This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. Avago Confidential Preliminary Datasheet 1.0 19 Feb 2013 Table 2. Insulation and Safety Related Specifications Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Symbol QCPL-341H Units L(101) 7.1 mm L(102) 7.4 mm 0.08 mm Minimum Internal Plastic Gap (Internal Clearance) Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance CTI > 175 V DIN IEC 112/VDE 0303 Part 1 (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Notes: 1. All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered (the recommended Land Pattern does not necessarily meet the minimum creepage of the device). There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. Table 3. Absolute Maximum Ratings Parameter Storage Temperature Operating Temperature Output IC Junction Temperature Average Input Current Peak Transient Input Current ( 5 V IF = 10 mA IF = 10 mA V IR = 100 µA pF f = 1 MHz, VF = 0 V V 2, 16 1 5, 17 4, 5 6, 7, 8 13 VO > 5 V, IF = 10 mA 19 V This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. 9, 10 Avago Confidential Preliminary Datasheet 1.0 19 Feb 2013 Table 6. Switching Specifications (AC) Unless otherwise noted, all typical values are at TA = 25 °C, VCC - VEE = 30 V, VEE = Ground; all minimum and maximum specifications are at recommended operating conditions (TA = -40 to 105 °C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VEE = Ground, VCC = 15 to 30 V). Parameter Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Pulse Width Distortion Propagation Delay Difference Between Any Two Parts Rise Time Fall Time Symbol Min. Typ. Max. Units tPLH 50 98 300 ns tPHL 50 95 300 ns 22 150 ns 200 ns PWD PDD (tPHL - tPLH) tR tF Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity -100 |CMH| 43 40 25 |CML| ns ns 35 25 kV/s 35 kV/s Test Conditions Rg = 10 , Cg = 25 nF, f = 20 kHz , Duty Cycle = 50%, IF = 7 mA to 16 mA, VCC = 15 V to 30 V Fig. Note 8, 9, 10, 11, 12, 20 11 27, 28 Vcc = 30 V 12 20 TA = 25 °C, IF = 10 mA, VCM = 1500 V, VCC = 30 V, VCM = 1500 V TA = 25°C, VF = 0 V, VCM = 1500 V, VCC = 30 V, VCM = 1500 V 13, 14 21 13, 15 Table 7. Package Characteristics Unless otherwise noted, all typical values are at TA = 25 °C; all minimum/maximum specifications are at recommended operating conditions. Parameter Input-Output Momentary Withstand Voltage* Input-Output Resistance Input-Output Capacitance LED-to-Case Thermal Resistance LED-to-Detector Thermal Resistance Detector-to-Case Thermal Resistance Symbol VISO Device Min. QCPL-341H 3750 Typ. Max. Units VRMS RI-O CI-O 1012 θLC 467 θLD, 442 ΘDC 126 0.6  pF °C/W Test Conditions RH < 50%, t = 1 min., TA = 25 °C VI-O = 500 VDC f =1 MHz Fig. Note 16,17 17 25 18 * The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Avago Technologies Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.” This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. Avago Confidential Preliminary Datasheet 1.0 19 Feb 2013 Notes: 1. Derate linearly above 70 C free-air temperature at a rate of 0.3 mA/ C. 2. Maximum pulse width = 10 µs. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See applications section for additional details on limiting IOH peak. 3. Derate linearly above 70 C free-air temperature at a rate of 4.8 mW/ C. 4. Derate linearly above 70 C free-air temperature at a rate of 5.4 mW/ C . The maximum LED junction temperature should not exceed 125 C. 5. Maximum pulse width = 50 µs. 6. Output is sourced at -2.0 A with a maximum pulse width = 10 µs. VCC-VO is measured to ensure 15 V or below. 7. Output is sourced at 2.0 A with a maximum pulse width = 10 µs. VO-VEE is measured to ensure 15 V or below. 8. Output is sourced at -2.0 A/2.0 A with a maximum pulse width = 10 µs. 9. In this test VOH is measured with a dc load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero amps. 10. Maximum pulse width = 1 ms. 11. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device. 12. The difference between tPHL and tPLH between any two QCPL-341H parts under the same test condition. 13. Pin 1 and 4 need to be connected to LED common. 14. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15.0 V). 15. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V). 16. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 VRMS for 1 second (leakage detection current limit, II-O 5 µA). 17. Device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together. 18. The device was mounted on a high conductivity test board as per JEDEC 51-7. This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. Avago Confidential Preliminary Datasheet 1.0 This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. 19 Feb 2013 Avago Confidential Preliminary Datasheet 1.0 This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. 19 Feb 2013 Avago Confidential Preliminary Datasheet 1.0 This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. 19 Feb 2013 Avago Confidential Preliminary Datasheet 1.0 1 8 2 7 3 6 4 5 I F = 7 to 16 mA 19 Feb 2013 4 V Pulsed +_ 1 µF +_ I OH VCC = 15 to 30 V Figure 14. IOH test circuit. 1 8 2 7 3 6 4 5 1 µF I OL +_ +_ VCC = 15 to 30 V 2.5 V Pulsed Figure 15. IOL test circuit. 1 8 2 7 3 6 4 5 1 8 2 7 3 6 4 5 I F = 7 to 16 mA 1 µF VOH +_ VCC = 15 to 30 V 100 mA Figure 16. VOH test circuit. 100 mA 1 µF VOL +_ VCC = 15 to 30 V Figure 17. VOL test circuit. This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. Avago Confidential Preliminary Datasheet 1.0 IF 1 8 2 7 3 6 4 5 1 8 2 7 3 6 4 5 19 Feb 2013 1 µF VO > 5 V 10 Ω +_ VCC = 15 to 30 V 25 nF Figure 18. IFLH test circuit. I F = 7 to 16 mA 1 µF VO > 5 V +_ VCC Figure 19. UVLO test circuit. I F = 7 to 16 mA, 20kHz, 50% Duty Cycle 1 8 2 7 3 6 4 5 1 µF VO 10 Ω +_ VCC = 15 to 30 V 25 nF Figure 20. t PLH, t PHL, t r and t f test circuit and waveforms. +_ 8 2 7 3 6 4 5 1 µF VO +_ VCC = 30 V 10 mA +_ 5V 1 VCM = 1500V Figure 21. CMR test circuit and waveforms. This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. Avago Confidential Preliminary Datasheet 1.0 19 Feb 2013 Application Information Recommended Application Circuit The recommended application circuit shown in Figure 22 illustrates a typical gate drive implementation using the QCPL-341H. The following describes about driving IGBT. However, it is also applicable to MOSFET. Designers will need to adjust the VCC supply voltage, depending on the MOSFET or IGBT gate threshold requirements (Recommended VCC = 15 V for IGBT and 12 V for MOSFET). The supply bypass capacitors (1 µF) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, a low current (5.0 mA) power supply will be enough to power the device. The gate resistor RG serves to limit gate charge current and controls the IGBT collector voltage rise and fall times. In PC board design, care should be taken to avoid routing the IGBT collector or emitter traces close to the QCPL-341H’s inputs as this can result in unwanted coupling of transient signals into QCPL-341H and degrade performance. 1 8 2 7 3 6 R +_ VCC =15V 1µF RG VEE=-5V 4 +_ +_ + HVDC Q1 5 Q2 + VCE - + VCE - 3-PHASE AC - HVDC Figure 22. Recommended application circuit with split resistors LED drive. Selecting the Gate Resistor (Rg) Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT and Rg in Figure 22 can be analyzed as a simple RC circuit with a voltage supplied by QCPL-341H. Rg  VCC VEE I OLPEAK 15V  5V 2. 5 A  8  Step 1: Check the QCPL-341H power dissipation and increase Rg if necessary. The QCPL-341H total power dissipation (PT) is equal to the sum of the emitter power (PE) and the output power (PO). PT = PE + PO PE = IF • VF • Duty Cycle PO = PO(BIAS) + PO(SWITCHING) = ICC • (VCC-VEE) + ESW(Rg;Cg) • f Using IF(worst case) = 16 mA, Rg = 8 Ω, Max Duty Cycle = 80%, Cg = 25 nF, f = 25 kHz and TA max = 70 °C: PE = 16 mA • 1.95 V • 0.8 = 25 mW PO = 5 mA • 20 V + 4 µJ • 25 kHz = 100 mW + 100 mW = 200 mW < 250 mW (PO(MAX) @ 70 °C) The value of 5 mA for ICC in the previous equation is the maximum ICC over the entire operating temperature range. This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. Avago Confidential Preliminary Datasheet 1.0 19 Feb 2013 Since PO is less than PO(MAX), Rg = 8 Ω is alright for the power dissipation. 3.0E-05 ESW - Enery Per Switching Cycle - J Vcc=30V 2.5E-05 Vcc=20V Vcc=15V 2.0E-05 1.5E-05 1.0E-05 5.0E-06 0.0E+00 0 2 4 6 8 10 Rg - Gate Resistance - Ω Figure 23. Energy Dissipated in the QCPL-341H for each IGBT switching cycle. Dead Time and Propagation Delay Specifications The QCPL-341H includes a Propagation Delay Difference (PDD) specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 22) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worstcase conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 23. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 100 ns over the operating temperature range of -40 °C to 105 °C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 24. The maximum dead time for the QCPL-341H is 400 ns (= 200 ns - (-200 ns)) over an operating temperature range of -40 °C to 105 °C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. Avago Confidential Preliminary Datasheet 1.0 19 Feb 2013 Figure 23. Minimum LED skew for zero dead time. Figure 24. Waveforms for dead time. LED Current Input with Hysteresis The detector has optical receiver input stage with built in Schmitt trigger to provide logic compatible waveforms, eliminating the need for additional wave shaping. The hysteresis (Figure 6) provides differential mode noise immunity and minimizes the potential for output signal chatter. Under Voltage Lockout The QCPL-341HUnder Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the QCPL-341H output low during power-up. IGBTs typically require gate voltages of 15 V to achieve their rated VCE(ON) voltage. At gate voltages below 13 V typically, the VCE(ON) voltage increases dramatically, especially at higher currents. At very low gate voltages (below 10 V), the IGBT may operate in the linear region and quickly overheat. The UVLO function causes the output to be clamped whenever insufficient operating supply (VCC) is applied. Once VCC exceeds VUVLO+ (the positive-going UVLO threshold), the UVLO clamp is released to allow the device output to turn on in response to input signals. This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. Avago Confidential Preliminary Datasheet 1.0 Thermal Model for QCPL-341H Definitions: TJE: LED junction temperature TJD: Detector IC junction temperature TC: Case temperature measured at the center of the package bottom θLC : LED-to-case thermal resistance θLD: LED-to-detector thermal resistance θDC: Detector-to-case thermal resistance θCA: Case-to-ambient thermal resistance *θCA will depend on the board design and the placement of the part TA: Ambient temperature. Figure 25. Thermal model. Related Application Noted AN5336 – Gate Drive Optocoupler Basic Design for IGBT / MOSFET AN1043 – Common-Mode Noise: Sources and Solutions AV02-0310EN –Plastics Optocouplers Product ESD and Moisture Sensitivity This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. 19 Feb 2013