PI74ALVCH16721A

PI74ALVCH16721 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 3.3V 20-Bit Flip-Flop with 3-STATE Outputs Product Features Product Description • • • • Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. • • • • PI74ALVCH16721 is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors Industrial operation at –40°C to +85°C Packages available: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 300 mil wide plastic SSOP (V) The PI74ALVCH16721 is a 20-bit flip-flop with 3-state outputs designed specifically for 2.3V to 3.6V VCC operation. The PI74ALVCH16721 is designed with edge-triggered D-type flipflops with qualified clock storage. On the positive transition of clock (CLK) input, the device provides true data at the Q outputs, provided that the clock-enable (CLKEN) input is LOW. If CLKEN is HIGH, no data is stored. A buffered output-enable (OE) input can be used to place the 20 outputs in either a normal logic state (HIGH or LOW level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capacity to drive bus lines without the need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The PI74ALVCH16721 data has “Bus Hold” which retains the data input’s last state whenever the data input goes to highimpedance preventing “floating” inputs and eliminating the need for pullup/down resistors. Logic Block Diagram 1 56 29 2 55 1 PS8090C 02/07/00 PI74ALVCH16721 3.3V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Name OE CLKEN CLK Dx Qx GND VCC Truth Table(1) Description Output Enable Input (Active LOW) Clock Enable Input (Active LOW) Clock Input (Active HIGH) Data Inputs 3-State Outputs Ground Power Inputs Q4 VCC Q5 Q6 Q7 GND Q8 Q9 Q10 Q11 Q12 Q13 GND Q14 Q15 Q16 VCC Q17 Q18 GND Q19 Q20 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 56 55 54 53 52 51 50 49 48 47 46 45 44 14 43 56-Pin 15 A,V 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 25 26 27 28 OE CLKEN CLK Dx Qx L H X X Q0 L L ↑ H H L L ↑ L L L L L or H X Q0 H X X X Z Notes: 1. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance ↑ = LOW-to-HIGH Transition Product Pin Configuration OE Q1 Q2 GND Q3 Outputs 33 32 31 30 29 CLK D1 D2 GND D3 D4 VCC D5 D6 D7 GND D8 D9 D10 D11 D12 D13 GND D14 D15 D16 VCC D17 D18 GND D19 D20 CLKEN 2 PS8090C 02/07/00 PI74ALVCH16721 3.3V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........................................................... –65°C to +150°C Ambient Temperature with Power Applied ........................ –40°C to +85°C Input Voltage Range, VIN ...................................................... –0.5V to VCC +0.5V Output Voltage Range, VOUT ............................................... –0.5V to VCC +0.5V DC Input Voltage .................................................................... –0.5V to +5.0V DC Output Current ............................................................................ 100 mA Power Dissipation .................................................................................. 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ±10%) Te s t Conditions (1) D e s cription VCC Supply Voltage VIH(3) Input HIGH Voltage VIL(3) Input LO W Voltage VIN(3) Input Voltage 0 VCC VOUT(3) O utput Voltage 0 VCC VOH VOL IOH(3) IOL(3) O utput HIGH Voltage O utput LO W Voltage O utput HIGH Current O utput LO W Current M in. Typ.(2) Parame te rs 2.3 VCC = 2.3V to 2.7V 1.7 VCC = 2.7V to 3.6V 2.0 M ax. 3.6 VCC = 2.3V to 2.7V 0.7 VCC = 2.7V to 3.6V 0.8 IOH = - 100µA, VCC = Min. to Max. VCC - 0.2 VIH = 1.7V, IOH = - 6mA, VCC = 2.3V 2.0 VIH = 1.7V, IOH = - 12mA, VCC = 2.3V 1.7 VIH = 2.0V, IOH = - 12mA, VCC = 2.7V 2.2 VIH = 2.0V, IOH = - 12mA, VCC = 3.0V 2.4 VIH = 2.0V, IOH = - 24mA, VCC = 3.0V 2.0 V IOL = 100µA, VIL = Min. to Max. 0.2 VIL = 0.7V, IOL = 6mA, VCC = 2.3V 0.4 VIL = 0.7V, IOL = 12mA, VCC = 2.3V 0.7 VIL = 0.8V, IOL = 12mA, VCC = 2.7V 0.4 VIL = 0.8V, IOL = 24mA, VCC = 3.0V 0.55 VCC = 2.3V - 12 VCC = 2.7V - 12 VCC = 3.0V - 24 VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 3 Units mA PS8090C 02/07/00 PI74ALVCH16721 3.3V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics-Continued (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ±10%) Te s t Conditions (1) Parame te rs De s cription IIN IIN (HOLD) Input Current Input Hold Current M in. Typ.(2) VIN = VCC or GND, VCC = 3.6V M ax. ±5 VIN = 0.7V, VCC = 2.3V 45 VIN = 1.7V, VCC = 2.3V - 45 VIN = 0.8V, VCC = 3.0V 75 VIN = 2.0V, VCC = 3.0V - 75 VIN = 0 to 3.6V, VCC = 3.6V ±500 IOZ Output Current (3- STATE Outputs) VOUT = VCC or GND, VCC = 3.6V ±10 ICC Supply Current VCC = 3.6V, IOUT = 0µA, VIN = GND or VCC 40 ∆ICC Supply Current per Input @ TTL HIGH VCC = 3.0V to 3.6V One Input at VCC - 0.6V Other Inputs at VCC or GND 750 CI CO Control Inputs Data Inputs Outputs VIN = VCC or GND, VCC = 3.3V VO = VCC or GND, VCC = 3.3V Units µA 3 6 pF 7 Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading. 3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating. 4 PS8090C 02/07/00 PI74ALVCH16721 3.3V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics over Operating Range(1) Parame te rs De s cription fCLOCK Clock Frequency fMAX Maximum Frequency tPLH, tPHL Propogation Delay CLK to Qx tPZH, tPZL Output Enable Time OE to Qx tPHX Output Disable Time OE to Qx tSU Data Before CLK↑ Conditions (1) VCC = 2.5V ±0.2V M in.(2) 0 VCC = 2.7V M ax. M ax. M in.(2) M ax. 150 0 150 0 150 150 150 5.6 6.1 1.0 CL = 50pF RL = 500Ω VCC = 3.3V ±0.3V M in.(2) 150 5.1 1.0 5.5 5.8 4.7 4.4 4 3.6 3.1 3.4 3.1 2.7 tH Data After CLK↑ 0 0 0 tH CLKEN After CLK↑ 0 0 0 3.3 3.3 3.3 CLK HIGH or LOW ∆t/∆v(4) Input Transition RISE or FALL 0 10 4.8 1.0 CLKEN Before CLK↑ tW 0 10 MHz 4.3 tSU Pulse Width(3) Units ns 0 10 ns/V Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Recommended operating condition. Operating Characteristics, TA = 25ºC Parame te r CPD Power Dissipation Capacitance Te s t Conditions Outputs Enabled Outputs Disabled CL = 50pF, f = 10 MHz VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V Typ. 55 59 46 49 Units pF Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS8090C 02/07/00