PI74AVC+16721A

PI74AVC+16721 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 2.5V 20-Bit Flip-Flop with 3-State Outputs Product Features Product Description • PI74AVC+16721 is designed for low voltage operation, VCC = 1.65V to 3.6V Pericom Semiconductor’s PI74AVC+ series of logic circuits are produced using the Company’s advanced submicron CMOS technology, achieving industry leading speed. The PI74AVC+16721 is a 20-bit flip-flop with 3-state outputs designed specifically for 1.65V to 3.6V VCC operation. The device is designed with edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of clock (CLK) input, the device provides true data at the Q outputs, provided that the clock-enable (CLKEN) input is LOW. If CLKEN is HIGH, no data is stored. • True ±24mA Balanced Drive @ 3.3V • IOFF supports partial power-down operation • 3.6V I/O Tolerant inputs and outputs • All outputs contain noise reduction circuitry reducing noise without speed degradation • Industrial operation at –40°C to +85°C • Available Packages: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 173 mil wide plastic TVSOP (TSSOP) (K) A buffered output-enable (OE) input can be used to place the 20 outputs in either a normal logic state (HIGH or LOW level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capacity to drive bus lines without the need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the highimpedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Logic Block Diagram 1 56 29 2 55 1 PS8483 07/11/00 PI74AVC+16721 2.5V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Truth Table(1) Product Pin Description Pin Name D e s cription Inputs Outputs OE O utput Enable Input (Active LO W) OE CLKEN CLK Dx Qx CLKEN Clock Enable Input (Active LO W) L H X X Q0 Clock Input (Active HIGH) L L – H H Dx Data Inputs L L – L L Qx 3- State O utputs L L L or H X Q0 GND Ground H X X X Z VCC Power CLK Notes: 1. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance ↑ = LOW-to-HIGH Transition Product Pin Configuration OE Q1 Q2 GND Q3 Q4 VCC Q5 Q6 Q7 GND Q8 Q9 Q10 Q11 Q12 Q13 GND Q14 Q15 Q16 VCC Q17 Q18 GND Q19 Q20 NC 1 2 3 4 5 6 7 8 9 10 11 56 55 54 53 52 51 50 49 48 47 46 12 45 13 44 14 43 56-Pin 15 A,V 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 CLK D1 D2 GND D3 D4 VCC D5 D6 D7 GND D8 D9 D10 D11 D12 D13 GND D14 D15 D16 VCC D17 D18 GND D19 D20 CLKEN 2 PS8483 07/11/00 PI74AVC+16721 2.5V 20-Bit Flip-Flop 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings above which the useful life may be impaired. (For user guidelines, not tested.) Supply voltage range, VCC ............................................................................. –0.5V to +4.6V Input voltage range, VI .................................................................................... –0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ............................................... –0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ......................................................................... –0.5V to VCC +0.5V Input clamp current, IIK (VI