PI74AVC+16836A

PI74AVC+16836 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 2.5V 20-Bit Universal Bus Driver with 3-State Outputs Features Description • PI74AVC+16836 is designed for low-voltage operation, VCC = 1.65V to 3.6V Pericom Semiconductor’s 20-bit PI74AVC+16836 universal bus driver is designed for 1.65V to 3.6V VCC operation. Data flow from A to Y is controlled by the Output Enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is LOW. When LE is HIGH, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is HIGH, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is HIGH, the outputs are in the highimpedance state, but all the inputs are enabled and data is capable of being stored in the register. • True ±24mA Balanced Drive @ 3.3V • IOFF supports partial power-down operation • 3.6V I/O Tolerant inputs and outputs • Meets PC133 SDRAM Registered DIMM Specifications • All outputs contain a patented DDC (Dynamic Drive Control) circuit that reduces noise without degrading propagation delay To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. • Industrial operation: –40°C to +85°C • Packaging (Pb-free & Green available): – 56-pin 240-mil wide plastic TSSOP (A) Block Diagram OE CLK LE A1 1 56 29 55 1D C1 2 Y1 V CLK TO 19 OTHER CHANNELS 1 08-0291 PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Truth Table(1) Pin Description Pin Name Inputs De s cription OE Output Enable Input (Active LOW) OE LE CLK A Outputs Y LE Latch Enable (Active LOW) H X X X Z CLK Clock Input L L X L L A Data Input L L X H H Y Data Output L H ↑ L L GND Ground L H ↑ H H Vcc Power L H L or H X Yo(2) Notes: 1 H = High Signal Level L = Low Signal Level Z = High Impedance ↑ = Transition LOW-to-HIGH X = Irrelevant 2. Output level before the indicated steady-state input conditions were established. Pin Configuration OE Y1 1 2 56 55 CLK A1 Y2 GND Y3 3 4 5 54 53 52 A2 GND A3 Y4 VCC 51 50 49 A4 VCC Y5 6 7 8 A5 Y6 Y7 9 10 48 47 A6 A7 GND Y8 Y9 11 12 13 46 45 44 GND A8 A9 Y10 Y11 Y12 14 15 16 43 42 41 A10 A11 A12 Y13 GND 17 18 40 39 A13 GND Y14 Y15 Y16 19 20 21 38 37 36 A14 A15 A16 VCC 22 23 24 35 VCC Y17 Y18 34 33 A17 A18 GND Y19 25 26 32 31 GND A19 Y20 NC 27 28 30 29 A20 LE 2 08-0291 PS8511E 10/17/08 PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345 Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ............................................ –0.5V to +4.6V Input voltage range, VI .................................................. –0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ................... –0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ....................................... –0.5V to VCC +0.5V Input clamp current, IIK (VI