PI74AVC+16646A

PI74AVC+16646 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 2.5V 16-Bit Bus Transceiver and Register with 3-State Outputs Product Features Product Description • PI74AVC+16646 is designed for low voltage operation, VCC = 1.65V to 3.6V Pericom Semiconductor’s PI74AVC+ series of logic circuits are produced using the Company’s advanced sub-micron CMOS technology, achieving industry leading speed. • True ±24mA Balanced Drive @ 3.3V The PI74AVC+16646 is a 16-bit bus transceiver and register designed for 1.65V to 3.6V VCC operation. It can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate Clock (CLKAB or CLKBA) input. Four fundamental busmanagement functions can be performed. Output Enable (OE) and Direction Control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The Select Control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. Circuitry used for Select Control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is LOW. In the isolation mode (OE HIGH), A data may be stored in one register and/ or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. • IOFF supports partial power-down operation • 3.6V I/O Tolerant Inputs and Outputs • All outputs contain a patented DDC (Dynamic DriveControl) circuit that reduces noise without degrading propagation delay. • Industrial operation at –40°C to +85°C • Available Packages: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 173 mil wide plastic TVSOP (K) Logic Block Diagrams 1OE 56 1DIR 2OE 29 1 2DIR 28 1CLKBA 55 2CLKBA 30 1SBA 54 1CLKAB 2 1SAB 3 2SBA 31 2CLKAB 27 2SAB 26 One of Eight Channels 1D One of Eight Channels 1D C1 1A1 C1 5 52 1D 2A1 15 1B1 42 1D C1 2B1 C1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS 1 PS8506B 02/26/01 PI74AVC+16646 2.5V 16-Bit Bus Transceiver and Register with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Configuration 1DIR Pin Name 1 2 3 4 5 6 7 56 55 54 53 52 51 50 8 9 10 11 49 48 47 46 12 56-Pin 13 A,K 14 15 45 44 43 42 1B 6 16 17 18 19 41 40 39 38 2B 2 2A 6 20 21 37 36 VCC 2A 7 2A 8 GND 22 23 24 25 35 34 33 32 2SAB 26 27 31 30 2SBA 2CLKAB 2DIR 28 29 2OE 1CLKAB 1SAB GND 1A 1 1A 2 VCC 1A 3 1A 4 1A 5 GND 1A 6 1A 7 1A 8 2A 1 2A 2 2A 3 GND 2A 4 2A 5 1OE 1CLKBA 1SBA GND 1B 1 1B 2 VCC 1B 3 1B 4 D e s cription xO E O utput Enable Inputs (Active LO W) xDIR Direction Control xCLK AB, xCLK BA Clock Pulse Inputs xSAB, xSBA Select Control Inputs xAx Data Register A Inputs Data Register B O utputs xBx Data Register B Inputs Data Register A O utputs GND Ground VCC Power 1B 5 GND 1B 7 1B 8 2B 1 2B 3 GND 2B 4 2B 5 2B 6 VCC 2B 7 2B 8 GND 2CLKBA Truth Table Inputs Data I/O xOE xDIR xCLKAB xCLKBA xSAB xSBA xAx xBx Store A, B Unspecified(1) Store B, A Unspecified(1) X X X X ↑ X X ↑ X X X X Input Unspecified(1) Unspecified(1) Input Isolation, Hold Storage Store A and B Data H H X X H or L ↑ H or L ↑ X X X X Input Disable Input Input Disable Input Real Time A Data to B Bus Stored A Data to B Bus L L H H X H or L X X L H X X Input Input Output Output Real Time B Data to A Bus Stored B Data toA Bus L L L L X X X H or L X X L H Output Output Input Input Function Notes: 1. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 2. H = High Voltage Level X = Don’t Care L = Low Voltage Level ↑ = LOW-to-HIGH transition 2 PS8506B 02/26/01 PI74AVC+16646 2.5V 16-Bit Bus Transceiver and Register with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 REAL-TIME TRANSFER BUS A to B REAL-TIME TRANSFER BUS B to A xDIR L BUS BUS BUS BUS A B A B xOE L xCLKAB X xCLKBA X xSAB X xSBA L xDIR H xOE L xCLKAB X xOE X X H xSAB L BUS BUS BUS BUS A B A B xCLKAB ↑ X ↑ xCLKBA X ↑ ↑ xSBA X TRANSFER STORED DATA to A and/or B STORAGE FROM A,B, or A and B xDIR X X X xCLKBA X xSAB X X X xDIR L H xSBA X X X 3 xOE L L xCLKAB X H or L xCLKBA H or L X xSAB X H PS8506B xSBA H X 02/26/01 PI74AVC+16646 2.5V 16-Bit Bus Transceiver and Register with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ................................................................................ –0.5V to +4.6V Input voltage range, VI ......................................................................................... –0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ................................................... –0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ........................................................................... –0.5V to VCC +0.5V Input clamp current, IIK (VI