PI74ALVTC16373A

PI74ALVTC16373 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 16-Bit Transparent D-Type Latch with 3-STATE Outputs Product Features Product Description • PI74ALVTC family is designed for low voltage operation, VDD = 1.8V to 3.6V • Supports Live Insertion • 3.6V I/O Tolerant Inputs and Outputs • Bus Hold • High Drive, -32/64mA @ 3.3V • Uses patented noise reduction circuitry • Power-off high impedance inputs and outputs • Industrial operation at –40°C to +85°C • Packages available: – 48-pin 240 mil wide plastic TSSOP (A) – 48-pin 173 mil wide plastic TVSOP (K) – 48-pin 300 mil wide plastic SSOP (V) Pericom Semiconductor’s PI74ALVTC series of logic circuits are produced in the Company’s advanced 0.35 micron CMOS technology, achieving industry leading speed. The PI74ALVTC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the Latch Enable (LE) input is HIGH, the Q outputs follow the (D) inputs. When LE is taken LOW, the Q outputs are latched at the levels set up at the D inputs. A buffered Output Enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state in which the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without an interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the ouputs are in the high-impedance state. Logic Block Diagram 1OE 1LE To ensure the high-impedance state during power up or power down, OE should be tied to Vdd through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 1 48 The family offers both I/O Tolerant, which allows it to operate in mixed 1.8/3.6V systems, and “Bus Hold,” which retains the data input’s last state whenever the data input goes to high-impedance, preventing “floating” inputs and eliminating the need for pullup/ down resistors. C1 2 1D1 47 1Q1 1D To Seven Other Channels 2OE 2LE 24 25 C1 13 2D1 36 2Q1 1D To Seven Other Channels 1 PS8355A 11/23/98 PI74ALVTC16373 16-Bit Transparent D-Type Latch With 3-STATE Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Truth Table(1) Product Pin Description Pin Name OE LE Dx Qx GND V CC Description Output Enable Input (Active LOW) Latch Enable (Active HIGH) Data Inputs 3-State Outputs Ground Power Inputs (1) 1OE 1 48 1LE 1Q1 2 47 1D1 1Q2 3 46 1D2 GND 4 45 GND 1Q3 5 44 1D3 1Q4 6 43 1D4 VCC 7 42 VCC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 39 GND 1Q7 11 38 1D7 1Q8 12 37 1D8 2Q1 13 36 2D1 35 2D2 34 GND 33 2D3 2Q2 14 GND 15 2Q3 16 48-PIN A48 K48 V48 OE LE D Q L H H H L H L L L L X QO H X X Z Note: 1. H L X Z Product Pin Configuration 2Q4 17 32 2D4 VCC 18 31 VCC 2Q5 19 30 2D5 2Q6 20 29 2D6 GND 21 28 GND 2Q7 22 27 2D7 2Q8 23 26 2D8 2OE 24 25 2LE 2 Outputs (1) = High Signal Level = Low Signal Level = Don’t Care or Irrelevant = High Impedance PS8355A 11/23/98 PI74ALVTC16373 16-Bit Transparent D-Type Latch With 3-STATE Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage Range, VDD .......................................... –0.5V to 4.6V Input Voltage Range, VI ................................................. -0.5V to 4.6V Output Voltage Range, VO (3-Stated) ............................ -0.5V to 4.6V Output Voltage Range, VO(1) (Active) ................. –0.5V to VDD +0.5V DC Input Diode Current (IIK) VI