PI7C9X118SLFDEX

PI7C9X118SL PCI Express-to-PCI Bridge Datasheet January 2021 Revision 5 1545 Barber Lane Milpitas, CA 95035 Telephone: 408-232-9100 FAX: 408-434-1040 Internet: http://www.diodes.com Document Number DS40301 Rev 5-2 PI7C9X118SL PR IMPORTANT NOTICE 1. DIODES INCORPORATED AND ITS SUBSIDIARIES (“DIODES”) MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. 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Copyright © 2021 Diodes Incorporated www.diodes.com PI7C9X118SL Document Number DS40301 Rev 5-2 Page 2 of 79 www.diodes.com January 2021 © Diodes Incorporated PI7C9X118SL PR REVISION HISTORY Date Revision # 07/31/2011 09/05/2011 12/15/2011 0.1 0.2 1.0 05/28/2013 1.1 07/24/2014 04/21/2016 1.2 1.3 01/18/2017 1.4 09/27/2017 2 02/06/2020 3 04/09/2020 4 01/18/2021 5 Description Preliminary Datasheet Updated Section 2.7 Power and Ground Pins (1.1V power supply to 1.0V) PI7C9X118SL datasheet release Remove Figure 8-2 Topology of internal clock generator and internal clock buffering – external feedback mode Remove Figure 8-4 Topology of external clock generator and internal clock buffering – external feedback mode Remove NC and pin 22 from Section 2.6 and added pin 22 to Section 2.7 under pin name VSS Updated Section 2.5 JTAG Boundary Scan Signals Updated Logo Updated Section 2.7 Power and Ground Pins Updated Section 2.8 Pin Assignments Updated Section 14.1 Absolute Maximum Ratings Updated Section 14.2 DC Specifications Added Section 14.4 Operating Ambient Temperature Added Section 14 Power Sequencing Updated Section 17 Ordering Information Revision numbering system changed to whole number Updated Section 17 Ordering Information Updated Figure 1-1 PI7C9X118SL Topology Updated Figure 16-1 Package Outline Drawing Added Figure 16-2 Part Marking Updated Section 14 Power Sequencing Added Section 14.2 Power-Off Sequence Updated Section 14 Power Sequencing Updated Section 2.2 PCI Express Signals PREFACE The datasheet of PI7C9X118SL will be enhanced periodically when updated information is available. The technical information in this datasheet is subject to change without notice. This document describes the functionalities of PI7C9X118SL (PCI Express Bridge) and provides technical information for designers to design their hardware using PI7C9X118SL. PI7C9X118SL Document Number DS40301 Rev 5-2 Page 3 of 79 www.diodes.com January 2021 © Diodes Incorporated PI7C9X118SL PR TABLE OF CONTENTS 1 INTRODUCTION ........................................................................................................................ 10 1.1 1.2 1.3 1.4 2 PIN DEFINITIONS ...................................................................................................................... 12 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 TRANSPARENT MODE ....................................................................................................... 18 FORWARD BRDIGE ............................................................................................................. 18 PCI EXPRESS FUNCTIONAL OVERVIEW........................................................................... 20 5.1 5.2 6 FUNCTIONAL MODE SELECTION .................................................................................... 17 PIN STRAPPING ................................................................................................................... 17 TRANSPARENT AND FORWARD BRIDGING..................................................................... 18 4.1 4.2 5 SIGNAL TYPES ..................................................................................................................... 12 PCI EXPRESS SIGNALS ...................................................................................................... 12 PCI SIGNALS ........................................................................................................................ 12 MODE SELECT AND STRAPPING SIGNALS ................................................................... 14 JTAG BOUNDARY SCAN SIGNALS .................................................................................. 14 MISCELLANEOUS SIGNALS ............................................................................................. 14 POWER AND GROUND PINS ............................................................................................. 14 PIN ASSIGNMENTS ............................................................................................................. 16 MODE SELECTION AND PIN STRAPPING.......................................................................... 17 3.1 3.2 4 INDUSTRY SPECIFICATION COMPLIANCE ................................................................... 10 GENERAL FEATURES ......................................................................................................... 10 PCI EXPRESS FEATURES ................................................................................................... 11 PCI FEATURES ..................................................................................................................... 11 TLP STRUCTURE ................................................................................................................. 20 VIRTUAL ISOCHRONOUS OPERATION .......................................................................... 20 CONFIGURATION REGISTER ACCESS............................................................................... 21 6.1 6.2 6.3 CONFIGURATION REGISTER MAP .................................................................................. 21 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP ............................................ 22 PCI CONFIGURATION REGISTERS .................................................................................. 23 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12 6.3.13 6.3.14 VENDOR ID – OFFSET 00h ................................................................................................................ 23 DEVICE ID – OFFSET 00h .................................................................................................................. 23 COMMAND REGISTER – OFFSET 04h .............................................................................................. 24 PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................... 24 REVISION ID REGISTER – OFFSET 08h ........................................................................................... 25 CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 25 CACHE LINE SIZE REGISTER – OFFSET 0Ch .................................................................................. 25 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 26 HEADER TYPE REGISTER – OFFSET 0Ch ........................................................................................ 26 RESERVED REGISTERS – OFFSET 10h TO 17h ................................................................................ 26 PRIMARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 26 SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 26 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 26 SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 26 PI7C9X118SL Document Number DS40301 Rev 5-2 Page 4 of 79 www.diodes.com January 2021 © Diodes Incorporated PI7C9X118SL PR 6.3.15 6.3.16 6.3.17 6.3.18 6.3.19 6.3.20 6.3.21 6.3.22 6.3.23 6.3.24 6.3.25 6.3.26 6.3.27 6.3.28 6.3.29 6.3.30 6.3.31 6.3.32 6.3.33 6.3.34 6.3.35 6.3.36 6.3.37 6.3.38 6.3.39 6.3.40 6.3.41 6.3.42 6.3.43 6.3.44 6.3.45 6.3.46 6.3.47 6.3.48 6.3.49 6.3.50 6.3.51 6.3.52 6.3.53 6.3.54 6.3.55 6.3.56 6.3.57 6.3.58 6.3.59 6.3.60 6.3.61 6.3.62 6.3.63 6.3.64 6.3.65 6.3.66 6.3.67 6.3.68 I/O BASE REGISTER – OFFSET 1Ch .................................................................................................. 27 I/O LIMIT REGISTER – OFFSET 1Ch ................................................................................................. 27 SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 27 MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 28 MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 28 PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ......................................................... 28 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ........................................................ 28 PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 28 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch ............................................... 28 I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h ......................................................................... 29 I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 29 CAPABILITY POINTER – OFFSET 34h .............................................................................................. 29 EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 29 INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................... 29 INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 29 BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 29 PCI DATA PREFETCHING CONTROL REGISTER – OFFSET 40h .................................................. 30 CHIP CONTROL 0 REGISTER – OFFSET 40h ................................................................................... 32 RESERVED REGISTER – OFFSET 44h............................................................................................... 33 ARBITER ENABLE REGISTER – OFFSET 48h ................................................................................... 33 ARBITER MODE REGISTER – OFFSET 48h ...................................................................................... 33 ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 34 RESERVED REGISTERS – OFFSET 4Ch ............................................................................................ 34 MEMORY READSMART BASE LOWER 32-Bit REGISTER 1 – OFFSET 50h.................................... 34 MEMORY READSMART BASE UPPER 32-Bit REGISTER 1 – OFFSET 54h .................................... 35 MEMORY READSMART RANGE CONTROL REGISTER 1 – OFFSET 58h ...................................... 35 MEMORY READSMART BASE LOWER 32-Bit REGISTER 2 – OFFSET 5Ch ................................... 35 MEMORY READSMART BASE UPPER 32-Bit REGISTER 2 – OFFSET 60h .................................... 35 MEMORY READSMART RANGE SIZE REGISTER 2 – OFFSET 64h ................................................ 35 UPSTREAM MEMORY READ/WRITE CONTROL REGISTER – OFFSET 68h .................................. 35 PHY TRANSMIT/RECEIVE CONTROL REGISTER – OFFSET 6Ch .................................................. 36 EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h ........................................... 37 RESERVED REGISTER – OFFSET 74h............................................................................................... 38 GPIO DATA AND CONTROL REGISTER – OFFSET 78h .................................................................. 38 RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 38 PCI-X CAPABILITY ID REGISTER – OFFSET 80h ............................................................................ 38 NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 38 PCI-X SECONDARY STATUS REGISTER – OFFSET 80h .................................................................. 38 PCI-X BRIDGE STATUS REGISTER – OFFSET 84h .......................................................................... 39 UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 40 DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 40 POWER MANAGEMENT ID REGISTER – OFFSET 90h .................................................................... 40 NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 41 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 41 POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 41 PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 42 SUBTRACTIVE DECODING PCI-TO-PCI BRIDGE ENABLE – OFFSET 98h .................................. 42 RESERVED REGISTERS – OFFSET 9Ch ............................................................................................ 42 CAPABILITY ID REGISTER – OFFSET A0h ....................................................................................... 42 NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 43 SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 43 CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 43 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h ................................. 43 XPIP CONFIGURATION REGISTER 3 – OFFSET A4h ..................................................................... 44 PI7C9X118SL Document Number DS40301 Rev 5-2 Page 5 of 79 www.diodes.com January 2021 © Diodes Incorporated PI7C9X118SL PR 6.3.69 6.3.70 6.3.71 6.3.72 6.3.73 6.3.74 6.3.75 6.3.76 6.3.77 6.3.78 6.3.79 6.3.80 6.3.81 6.3.82 6.3.83 6.3.84 6.3.85 6.3.86 6.3.87 6.3.88 6.3.89 6.3.90 6.3.91 6.3.92 6.3.93 6.3.94 6.3.95 6.3.96 6.3.97 6.3.98 6.3.99 6.3.100 6.3.101 6.3.102 6.3.103 6.3.104 6.3.105 6.3.106 6.3.107 6.3.108 6.3.109 6.3.110 6.3.111 6.3.112 6.3.113 6.3.114 6.3.115 6.3.116 6.3.117 6.3.118 6.3.119 6.3.120 6.3.121 6.3.122 CAPABILITY ID REGISTER – OFFSET A8h ....................................................................................... 44 NEXT POINTER REGISTER – OFFSET A8h....................................................................................... 44 RESERVED REGISTER – OFFSET A8h .............................................................................................. 44 SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh ...................................................................... 44 SUBSYSTEM ID REGISTER – OFFSET ACh ...................................................................................... 45 PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................. 45 NEXT CAPABILITY POINTER REGISTER – OFFSET B0h ................................................................ 45 PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h.................................................................... 45 DEVICE CAPABILITY REGISTER – OFFSET B4h ............................................................................. 45 DEVICE CONTROL REGISTER – OFFSET B8h................................................................................. 46 DEVICE STATUS REGISTER – OFFSET B8h ..................................................................................... 47 LINK CAPABILITY REGISTER – OFFSET BCh.................................................................................. 47 LINK CONTROL REGISTER – OFFSET C0h ...................................................................................... 48 LINK STATUS REGISTER – OFFSET C0h .......................................................................................... 48 RESERVED REGISTER – OFFSET C4 – C8h ..................................................................................... 49 XPIP CONFIGURATION REGISTER 0 – OFFSET CCh ..................................................................... 49 XPIP CONFIGURATION REGISTER 1 – OFFSET D0h ..................................................................... 49 XPIP CONFIGURATION REGISTER 2 – OFFSET D4h ..................................................................... 49 CAPABILITY ID REGISTER – OFFSET D8h ...................................................................................... 50 NEXT POINTER REGISTER – OFFSET D8h ...................................................................................... 50 VPD REGISTER – OFFSET D8h ......................................................................................................... 50 VPD DATA REGISTER – OFFSET DCh .............................................................................................. 50 EXTENDED CONFIGURATION ACCESS ADDRESS REGISTER – OFFSET E0h ............................ 50 EXTENDED CONFIGURATION ACCESS DATA REGISTER – OFFSET E4h ................................... 51 RESERVED REGISTERS – OFFSET E8h – ECh ................................................................................. 51 MESSAGE SIGNALED INTERRUPTS ID REGISTER – F0h ............................................................... 51 NEXT CAPABILITIES POINTER REGISTER – F0h ............................................................................ 51 MESSAGE CONTROL REGISTER – OFFSET F0h ............................................................................. 51 MESSAGE ADDRESS REGISTER – OFFSET F4h .............................................................................. 51 MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h ................................................................. 52 MESSAGE DATA REGISTER – OFFSET FCh..................................................................................... 52 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h .............................. 52 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h .................. 52 NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h ................................................................ 52 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................... 52 UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h ...................................................... 52 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ............................................... 53 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h ......................................................... 53 CORRECTABLE ERROR MASK REGISTER – OFFSET 114h ............................................................ 53 ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h ........................ 54 HEADER LOG REGISTER 1 – OFFSET 11Ch .................................................................................... 54 HEADER LOG REGISTER 2 – OFFSET 120h ..................................................................................... 54 HEADER LOG REGISTER 3 – OFFSET 124h ..................................................................................... 54 HEADER LOG REGISTER 4 – OFFSET 128h ..................................................................................... 54 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch ........................... 54 SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h ............................... 55 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h ........................ 55 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h.......................... 56 SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h.................................................... 56 RESERVED REGISTER – OFFSET 14Ch ............................................................................................ 56 VC CAPABILITY ID REGISTER – OFFSET 150h ............................................................................... 57 VC CAPABILITY VERSION REGISTER – OFFSET 150h ................................................................... 57 NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h ................................................................ 57 PORT VC CAPABILITY REGISTER 1 – OFFSET 154h ...................................................................... 57 PI7C9X118SL Document Number DS40301 Rev 5-2 Page 6 of 79 www.diodes.com January 2021 © Diodes Incorporated PI7C9X118SL PR 6.3.123 6.3.124 6.3.125 6.3.126 6.3.127 6.3.128 6.3.129 6.3.130 6.3.131 6.3.132 6.3.133 6.3.134 PORT VC CAPABILITY REGISTER 2 – OFFSET 158h ...................................................................... 57 PORT VC CONTROL REGISTER – OFFSET 15Ch............................................................................. 57 PORT VC STATUS REGISTER – OFFSET 15Ch ................................................................................. 57 VC0 RESOURCE CAPABILITY REGISTER – OFFSET 160h ............................................................. 57 VC0 RESOURCE CONTROL REGISTER – OFFSET 164h ................................................................. 58 VC0 RESOURCE STATUS REGISTER – OFFSET 168h ..................................................................... 58 RESERVED REGISTERS – OFFSET 16Ch – 2FCh ............................................................................. 58 EXTENDED GPIO DATA AND CONTROL REGISTER – OFFSET 300h........................................... 58 EXTENDED GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h .................................... 58 RESERVED REGISTERS – OFFSET 308h – 30Ch .............................................................................. 59 REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h ............................................. 59 RESERVED REGISTERS – OFFSET 314h – FFCh ............................................................................. 59 7 GPIO PINS .................................................................................................................................... 60 8 CLOCK SCHEME ....................................................................................................................... 61 9 INTERRUPTS .............................................................................................................................. 65 10 EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS ................................. 66 10.1 10.2 EEPROM (I2C) INTERFACE ................................................................................................ 66 EEPROM AUTOLOAD CONFIGURATION ....................................................................... 66 11 RESET SCHEME......................................................................................................................... 68 12 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................. 69 12.1 12.2 12.3 12.4 12.5 INSTRUCTION REGISTER .................................................................................................. 69 BYPASS REGISTER ............................................................................................................. 69 DEVICE ID REGISTER ......................................................................................................... 69 BOUNDARY SCAN REGISTER .......................................................................................... 70 JTAG BOUNDARY SCAN REGISTER ORDER ................................................................. 70 13 POWER MANAGEMENT .......................................................................................................... 71 14 POWER SEQUENCING ............................................................................................................. 72 14.1 14.2 15 INITIAL POWER-UP (G3 TO L0) ......................................................................................... 73 POWER-OFF SEQUENCE .................................................................................................... 74 ELECTRICAL AND TIMING SPECIFICATIONS ................................................................ 75 15.1 15.2 15.3 15.4 ABSOLUTE MAXIMUM RATINGS .................................................................................... 75 DC SPECIFICATIONS .......................................................................................................... 75 AC SPECIFICATIONS .......................................................................................................... 76 OPERATING AMBIENT TEMPERATURE ...................................................................................... 77 16 PACKAGE INFORMATION ..................................................................................................... 78 17 ORDERING INFORMATION ................................................................................................... 79 PI7C9X118SL Document Number DS40301 Rev 5-2 Page 7 of 79 www.diodes.com January 2021 © Diodes Incorporated PI7C9X118SL PR TABLE OF FIGURES FIGURE 1-1 PI7C9X118SL TOPOLOGY................................................................................................... 10 FIGURE 4-1 FORWARD BRIDGE MODE ..................................................................................................... 19 FIGURE 8-1 TOPOLOGY OF INTERNAL CLOCK GENERATOR AND INTERNAL CLOCK BUFFERING – INTERNAL FEEDBACK MODE ........................................................................................................... 62 FIGURE 8-2 TOPOLOGY OF INTERNAL CLOCK GENERATOR AND INTERNAL CLOCK BUFFERING – EXTERNAL FEEDBACK MODE .......................................................................................................... 62 FIGURE 8-3 TOPOLOGY OF EXTERNAL CLOCK GENERATOR AND INTERNAL CLOCK BUFFERING – INTERNAL FEEDBACK MODE ........................................................................................................... 63 FIGURE 8-4 TOPOLOGY OF EXTERNAL CLOCK GENERATOR AND INTERNAL CLOCK BUFFERING – EXTERNAL FEEDBACK MODE .......................................................................................................... 63 FIGURE 8-5 TOPOLOGY OF EXTERNAL CLOCK GENERATOR AND EXTERNAL CLOCK BUFFERING ............ 64 FIGURE 14-1 TIMING SEQUENCE WITH UNDETERMINED I/O STATE ......................................................... 72 FIGURE 14-2 RECOMMENDED POWER SEQUENCE .................................................................................... 72 FIGURE 14-3 INITIAL POWER-UP .............................................................................................................. 73 FIGURE 15-1 PCI SIGNAL TIMING CONDITIONS ....................................................................................... 76 FIGURE 16-1 PACKAGE OUTLINE DRAWING ............................................................................................ 78 FIGURE 16-2 PART MARKING .................................................................................................................. 78 LIST OF TABLES TABLE 2-1 PIN ASSIGNMENTS.................................................................................................................. 16 TABLE 3-1 MODE SELECTION .................................................................................................................. 17 TABLE 3-2 PIN STRAPPING FOR CLOCK POWER MANAGEMENT ............................................................... 17 TABLE 5-1 TLP FORMAT ......................................................................................................................... 20 TABLE 6-1 CONFIGURATION REGISTER MAP (00H – FFH) ....................................................................... 21 TABLE 6-2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP (100H – FFFH) .................................. 23 TABLE 8-1 FREQUENCY OF PCI CLKOUT WITH INTERNAL CLOCK SOURCE: ........................................... 61 TABLE 9-1 PCI INTERRUPT TO PCIE INTERRUPT MESSAGE MAPPING IN FORWARD BRIDGE MODE ........ 65 TABLE 12-1 INSTRUCTION REGISTER CODES ........................................................................................... 69 TABLE 12-2 JTAG DEVICE ID REGISTER ................................................................................................ 69 TABLE 14-1 POWER SEQUENCING AND RESET SIGNAL TIMINGS .............................................................. 73 TABLE 15-1 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 75 TABLE 15-2 DC ELECTRICAL CHARACTERISTICS .................................................................................... 75 TABLE 15-3 PCI BUS TIMING PARAMETERS ............................................................................................ 76 TABLE 15-4 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT CHARACTERISTICS76 TABLE 15-5 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT CHARACTERISTICS ......... 77 TABLE 15-6 OPERATING AMBIENT TEMPERATURE .................................................................................. 77 PI7C9X118SL Document Number DS40301 Rev 5-2 Page 8 of 79 www.diodes.com January 2021 © Diodes Incorporated PI7C9X118SL PR This page intentionally left blank. PI7C9X118SL Document Number DS40301 Rev 5-2 Page 9 of 79 www.diodes.com January 2021 © Diodes Incorporated PI7C9X118SL PR 1 INTRODUCTION PI7C9X118SL is a PCIe-to-PCI/PCI-X bridge. PI7C9X118SL is compliant with the PCI Express Base Specification, Revision 1.1, the PCI Express Card Electromechanical Specification, Revision 1.1, the PCI Local Bus Specification, Revision 3.0 and PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. PI7C9X118SL supports transparent mode operation and forward bridging. PI7C9X118SL has an x1 PCI Express upstream port and a 32-bit PCI downstream port. The 32-bit PCI downstream port is 66MHz capable (see Figure 1-1). PI7C9X118SL configuration registers are backward compatible with existing PCI bridge software and firmware. No modification of PCI bridge software and firmware is needed for the original operation. Figure 1-1 PI7C9X118SL Topology 1.1          1.2      INDUSTRY SPECIFICATION COMPLIANCE Compliant with PCI Express Base Specification, Revision 1.1 Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 Compliant with PCI Express Card Electromechanical Specification, Revision 1.0a Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.2 Compliant with PCI Local Bus Specification, Revision 3.0 Compliant with PCI SHPC and Subsystem Specification, Revision 1.0 Compliant with PCI Mobile Design Guide, Version 1.1 Compliant with PCI Bus PM Interface Specification, Revision 1.2 Compliant with Advanced Configuration and Power Interface Specification (ACPI), Revision 2.0b GENERAL FEATURES Forward bridging (PCI Express as primary bus, PCI as secondary bus) x1 PCI Express interface (2.5Gb/s data rate) 32-bit PCI interface capable of 66MHz GPIO support (4 bi-directional pins). When external arbiter is used, 3 additional GPI (input) and GPO (output) pins Power Management (including ACPI, PCI_PM, CLKRUN_L and CLKREQ_L,) PI7C9X118SL Page 10 of 79 January 2021 Document Number DS40301 Rev 5-2 www.diodes.com © Diodes Incorporated PI7C9X118SL PR            1.3          1.4           Transparent mode support Subtractive Decoding PCI-to-PCI bridge to support legacy device Masquerade support (user-defined vendor, device, revision, subsystem device, and subsystem vendor ID) EEPROM (I2C) Interface 8k byte buffer: 2K byte buffer for downstream memory read, 2K bytes for upstream memory read, and 2K byte buffer for memory write in both directions Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support Power consumption less than 400mW in L0 mode and less than 180mW in L1 mode Commercial temperature range (0oC to 75oC) Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/ PCI EXPRESS FEATURES Physical Layer interface (x1 link with 2.5Gb/s data rate) Virtual Isochronous support (upstream TC1-7 generation, downstream TC1-7 mapping) CRC (16-bit), LCRC (32-bit) ECRC and advanced error reporting Lane polarity toggle ASPM support WAKE_L support Maximum payload size to 256 bytes CLKREQ_L support to disable Refclk at L1 and L2 state PCI FEATURES Provides two level arbitration support for four PCI Bus masters 3.3V PCI signaling with 5V I/O tolerance PME_L support LOCK support 16-bit address decode for VGA Subsystem Vendor and Subsystem Device IDs support PCI INT interrupt or MSI Function support Adaptive fragmentation support for memory write Internal clock generator for PCI bus CLKRUN_L support to stop the PCI clock Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain