ZVP4105ASTOA

NOT RECOMMENDED NOT RECOMMENDED P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET ZVP4105A ISSUE 2 – MARCH 94 FEATURES * 50 Volt VDS * RDS(on)=10Ω * Low threshold D G S E-Line TO92 Compatible ABSOLUTE MAXIMUM RATINGS. PARAMETER SYMBOL VALUE UNIT Drain-Source Voltage VDS -50 V Continuous Drain Current at Tamb=25°C ID -175 mA Pulsed Drain Current IDM -520 mA Gate Source Voltage VGS ± 20 V Power Dissipation at Tamb=25°C Ptot 625 mW Operating and Storage Temperature Range Tj:Tstg -55 to +150 °C ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated). PARAMETER SYMBOL MIN. Drain-Source Breakdown Voltage BVDSS -50 Gate-Source Threshold Voltage VGS(th) -0.8 MAX. UNIT CONDITIONS. V ID=-0.25mA, VGS=0V -2.0 V ID=-1mA, VDS= VGS Gate-Body Leakage IGSS 10 nA VGS=± 20V, VDS=0V Zero Gate Voltage Drain Current IDSS -15 -60 -100 µA µA nA VDS=-50V, VGS=0V VDS=-50V, VGS=0V, T=125°C(2) VDS=-25V, VGS=0V 10 Ω VGS=-5V,ID=-100mA mS VDS=-25V,ID=-100mA Static Drain-Source On-State RDS(on) Resistance (1) Forward Transconductance (1)(2) gfs 50 Input Capacitance (2)(4) Ciss 40 pF Common Source Output Capacitance (2)(4) Coss 15 pF Reverse Transfer Capacitance (2)(4) Crss 6 pF Turn-On Delay Time (2)(3)(4) td(on) 10 ns Rise Time (2)(3)(4) 10 ns Turn-Off Delay Time (2)(3)(4) td(off) 18 ns Fall Time (2)(3)(4) 25 ns tr tf VDS=-25V, VGS=0V, f=1MHz VDD ≈ -30V, ID=-270mA (1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test. (3) Switching times measured with 50Ω source impedance and