TPS3809J25-Q1, TPS3809L30-Q1, TPS3809K33-Q1, TPS3809I50-Q1
TPS3809J25-Q1, TPS3809L30-Q1,
TPS3809K33-Q1,
TPS3809I50-Q1
SGLS142C – DECEMBER
2002 – REVISED
DECEMBER 2020
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SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020
TPS3809xxx-Q1 3-Pin Supply Voltage Supervisors
1 Features
3 Description
•
•
The TPS3809 family of supervisory circuits provides
circuit initialization and timing supervision, primarily
for DSPs and processor-based systems. The newer
TLV809E device is an alternative with the same pins,
functions and electrical parameters.
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to +125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C5
3-Pin SOT-23 Package
Supply Current of 9 μA (Typical)
Precision-Supply Voltage Monitor 2.5 V, 3 V, 3.3 V,
5V
Power-On Reset Generator With Fixed Delay Time
of 200 ms
Pin-For-Pin Compatible With MAX 809
2 Applications
•
•
•
•
•
Automotive Camera Systems
Telematics
Automotive Cluster
Engine Controls
Surround View Systems
During power-on, RESET is asserted when the supply
voltage VDD becomes higher than 1.1 V. Thereafter,
the supervisory circuit monitors VDD and keeps
RESET active as long as VDD remains below the
threshold voltage VIT. An internal timer delays the
return of the output to the inactive state (high) to
ensure proper system reset. The delay time, td(typ) =
200 ms, starts after VDD has risen above the threshold
voltage VIT. When the supply voltage drops below the
threshold voltage VIT, the output becomes active (low)
again. No external components are required. All the
devices of this family have a fixed sense-threshold
voltage VIT set by an internal voltage divider.
The product spectrum is designed for supply voltages
of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available
in a 3-pin SOT-23. The TPS3809xxx-Q1 devices are
characterized for operation over a temperature range
of −40°C to 125°C, and are qualified in accordance
with AEC-Q100 stress test qualification for integrated
circuits.
Device Information (1)
PART NUMBER
TPS3809xxx-Q1
(1)
PACKAGE
SOT-23 (3)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
TPS76333
3.3 V
5V
IN
OUT
GND
V DD
V DD
TMS320LC54x
TPS3809K33-Q1
RESET
RESET
GND
GND
Typical Application
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2020 Texas Instruments
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SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................3
6.1 Pin Functions.............................................................. 3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Timing Requirements.................................................. 5
7.7 Switching Characteristics............................................5
7.8 Timing Diagrams ........................................................ 6
7.9 Typical Characteristics................................................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes............................................8
9 Application and Implementation.................................... 9
9.1 Application Information............................................... 9
9.2 Typical Application...................................................... 9
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Support Resources................................................. 13
12.2 Trademarks............................................................. 13
12.3 Electrostatic Discharge Caution..............................13
12.4 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2016) to Revision C (December 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added new sentence regarding the new TLV809E to the Description section................................................... 1
• Renamed Device Comparison modified device option table and added comparison table ...............................3
• Changed VDD from 7 to 6.5 in Absolute Maximum Ratings ..............................................................................4
• Changed VOL @ 500μA from 0.2 to 0.3 in Electrical Characteristics .................................................................5
• Changed tw pulse duration from 3 to 10μs in Timing Requirements ..................................................................5
• Changed tPHL from 1 to 10μs in Switching Characteristics ................................................................................ 5
• Deleted figure for Minimum Pulse Duration At VDD in Typical Characteristics....................................................7
Changes from Revision A (December 2002) to Revision B (February 2016)
Page
• Added AEC-Q100 Qualified information in bullets .............................................................................................1
• Changed Applications list items .........................................................................................................................1
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
• Changed device part numbers by adding -Q1 to them throughout document ................................................... 5
2
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SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020
5 Device Comparison
Table 5-1. Device Threshold Options
PRODUCT
THRESHOLD VOLTAGE
TPS3809J25QDBVRQ1
2.25 V
TPS3809L30QDBVRQ1
2.64 V
TPS3809K33QDBVRQ1
2.93 V
TPS3809I50QDBVRQ1
4.55 V
Table 5-2. Device Family Comparison
DEVICE
FUNCTION
TLV803
Open-Drain, RESET Output
TLV809
Push-Pull, RESET Output
TLV810
Push-Pull, RESET Output
6 Pin Configuration and Functions
GND
1
3
RESET_
V
DD
2
Figure 6-1. DBV Package
3-Pin SOT-23
Top View
6.1 Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
1
—
Ground
RESET
2
O
Reset output
VDD
3
I
Supply voltage and supervising input
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SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
6.5
V
Supply voltage, VDD (2)
All other
pins(2)
–0.3
6.5
V
5
mA
Maximum low output current, IOL
–5
mA
Input clamp current, IIK (VIVDD)
Maximum high output current, IOH
–20
20
mA
Output clamp current, IOK (VOVDD)
–20
20
mA
Operating free-air temperature range, TA
–40
125
°C
Storage temperature, Tstg
–65
150
°C
Continuous total power dissipation
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to GND. For reliable operation the device should not be operated at 6.5 V for more than t = 1000 h
continuously.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC
Electrostatic discharge
Q100-002(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply voltage
TA
Operating free-air temperature
NOM
MAX
UNIT
2
6
V
–40
125
°C
7.4 Thermal Information
TPS3809xxx-Q1
THERMAL METRIC(1)
DBV (SOT-23)
UNIT
3 PINS
RθJA
Junction-to-ambient thermal resistance
232.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
187.6
°C/W
RθJB
Junction-to-board thermal resistance
104.1
°C/W
ψJT
Junction-to-top characterization parameter
40.5
°C/W
ψJB
Junction-to-board characterization parameter
104.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
High-level output voltage
VDD – 0.2
VDD = 3.3 V, IOH = −2 μA
VDD – 0.4
VDD = 6 V, IOH = −4 mA
VOL
Low-level output voltage
Power-up reset voltage(1)
TA = −40°C to +25°C
VDD – 0.4
TA = 125°C
VDD – 0.5
VIT−
Negative-going input threshold
voltage(2)
Vhys
Hysteresis
0.3
0.4
VDD = 6 V, IOL = 4 mA
0.4
VDD ≥ 1.1 V, IOL = 50 μA
0.2
2.20
2.25
2.58
2.64
2.7
2.87
2.93
2.99
TA = −40°C to +85°C
4.45
4.55
4.65
TA = −40°C to +125°C
4.4
4.55
4.65
TA = −40°C to +125°C
Supply current
Ci
Input capacitance
(1)
(2)
UNIT
V
TPS3809J25-Q1
30
TPS3809L30-Q1
35
TPS3809K33-Q1
40
TPS3809I50-Q1
IDD
MAX
VDD = 3.3 V, IOL = 2 mA
TPS3809K33-Q1
TPS3809I50-Q1
TYP
VDD = 2 V to 6 V, IOL = 500 μA
TPS3809J25-Q1
TPS3809L30-Q1
MIN
VDD = 2.5 V to 6 V, IOH = −500 μA
V
V
2.30
V
mV
60
VDD = 2 V, Output unconnected
9
15
VDD = 6 V, Output unconnected
20
30
VI = 0 V to VDD
5
μA
pF
The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.
To ensure best stability of the threshold voltage, a bypass capacitor ( 0.1 µF, ceramic) should be placed near the supply terminals.
7.6 Timing Requirements
RL = 1 MΩ, CL = 50 pF, TA = 25°C
MIN
tw
Pulse width at VDD
VDD = VIT− + 0.2 V, VDD = VIT− − 0.2 V
NOM
MAX
10
UNIT
μs
7.7 Switching Characteristics
RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
VDD ≥ VIT− + 0.2 V, See
timing diagram, Section 7.8
td
Delay time
tPHL
Propagation (delay) time,
high-to-low-level output
VDD to RESET delay
Copyright © 2020 Texas Instruments Incorporated
MIN
TYP
MAX
UNIT
120
200
280
ms
VIL = VIT− − 0.2 V, VIH = VIT−
+0.2 V
10
μs
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SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020
7.8 Timing Diagrams
VDD
V(NOM)
VIT
1.1 V
t
RESET
aaaaa
aaaaa
aaaaa
aaaaa
aaaaa
1
aaaa
aaaa
aaaa
aaaa
aaaa
0
td
t
td
For VDD< 1.1 V Undefined
Behavior of RESET Output
Figure 7-1. Timing Diagram
6
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SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020
7.9 Typical Characteristics
50
2.75
VDD = 2.5 V
o
TA = 25 C
40
2.25
30
2.00
IDD – Supply Current – mA
VOL – Low-Level Output Voltage – V
2.50
o
TA = 25 C
1.75
1.50
o
TA = 85 C
1.25
o
TA = 0 C
1.00
0.75
o
TA = –40 C
0.50
20
10
TPS3809J25
0
–10
–20
–30
–40
0.25
–50
0
0
2.5
5.0
7.5
10.0
–2
12.5
0
2
4
VDD – Supply Voltage – V
IOL – Low-Level Output Current – mA
Figure 7-2. Low-Level Output Voltage vs Low-Level
Output Current
6.5
3.00
5.5
5.0
o
4.5
TA = –40 C
4.0
3.5
o
TA = 0 C
3.0
o
2.5
TA = 85 C
2.0
1.5
1.0
VDD = 2.5 V
2.75
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
Figure 7-3. Supply Current vs Supply Voltage
VDD = 6 V
6.0
o
TA = 25 C
6
2.50
2.25
2.00
o
TA = –40 C
1.75
1.50
o
TA = 0 C
1.25
1.00
o
TA = 85 C
0.75
o
0.50
TA = 25 C
0.25
0.5
0
0
0
–10
–20
–30
–40
IOH – High-Level Output Current – mA
–50
0
VDD = 6 V
–2
–4
–6
–8
IOH – High-Level Output Current – mA
–10
VDD = 2.5 V
Normalized Threshold Voltage VIT (TA), VIT (25oC)
Figure 7-4. High-Level Output Voltage vs HighLevel Output Current
Figure 7-5. High-Level Output Voltage vs HighLevel Output Current
1.001
VDD = 2.3 V
1.000
0.999
0.998
0.997
0.996
0.995
–40
–20
0
20
40
60
o
TA – Free-Air Temperature – C
85
VDD = 2.3 V
Figure 7-6. Normalized Input Threshold Voltage vs Free-Air Temperature at VDD
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SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020
8 Detailed Description
8.1 Overview
The TPS3809xxx-Q1 device is a low-current supervisory circuit for monitoring system voltages above 2 V. The
device asserts an active-low RESET signal when VDD drops below a preset threshold. The RESET output
remains low until VDD returns above its threshold. The device design is also to be relatively immune to short
negative transients on the VDD pin.
8.2 Functional Block Diagram
TPS3809xxx-Q1
R1
_
VDD
+
Reset
Logic
+
Timer
RESET
R2
GND
Oscillator
Reference
Voltage
of 1.137 V
8.3 Feature Description
8.3.1 VDD Monitoring
The VDD pin provides a terminal at which a system voltage can be monitored. If the voltage on this pin drops
below VIT, RESET is asserted low. The comparator has a built-in hysteresis to ensure smooth RESET assertions
and deassertions. Refer to Section 5 to determine the VDD voltage threshold for each device.
8.4 Device Functional Modes
TPS3809xxx-Q1 monitors one supply using the VDD pin. When VDD is above the VIT threshold for the device,
RESET will be high. When VDD is below the VIT threshold for the device, RESET will be low.
8
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SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS3809xxx-Q1 voltage supervisor device design asserts an active-low RESET signal when VDD drops
below a voltage threshold VIT. The RESET signal remains low until the voltage returns above its threshold. The
typical application is with a processor or microcontroller, which needs to be reset when the supply rail drops
below a specified tolerance.
9.2 Typical Application
TPS76333
3.3 V
5V
IN
OUT
GND
V DD
V DD
TMS320LC54x
TPS3809K33-Q1
RESET
RESET
GND
GND
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
Each device has a fixed=voltage monitoring threshold, and the device should be chosen based on the voltage
being monitored. Refer to Section 5 to determine the VDD voltage threshold for each device. In this example, a
3.3V supply rail to a microcontroller will be monitored.
9.2.2 Detailed Design Procedure
Because a 3.3-V supply rail needs to be monitored, TPS3809K33-Q1 should be used. This device has a 2.93-V
threshold for reset. Connect the 3.3-V supply to the VDD pin and the reset output of the supervisor to the reset
pin of the microcontroller.
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9.2.3 Application Curves
Normalized Threshold Voltage VIT (TA), VIT (25oC)
50
o
TA = 25 C
40
IDD – Supply Current – mA
30
20
10
TPS3809J25
0
–10
–20
–30
–40
–50
–2
0
2
4
VDD – Supply Voltage – V
6
Figure 9-2. Supply Current vs Supply Voltage
1.001
VDD = 2.3 V
1.000
0.999
0.998
0.997
0.996
0.995
–40
–20
0
20
40
60
o
TA – Free-Air Temperature – C
85
VDD = 2.3 V
Figure 9-3. Normalized Input Threshold Voltage vs
Free-Air Temperature at VDD
10
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SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020
10 Power Supply Recommendations
The TPS3809xxx-Q1 device design operates from an input supply from 2 V to 6 V. TI recommends placing a 0.1µF capacitor near the VDD pin.
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11 Layout
11.1 Layout Guidelines
TI recommends placing the 0.1-µF decoupling capacitor close to the VDD pin. The VDD and GND traces should
be able to carry 30 µA without a significant drop in voltage.
11.2 Layout Example
GND
CVDD
TPS3809xxx-Q1
VDD
RESET
Denotes GND Via
Figure 11-1. Layout Example
12
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12 Device and Documentation Support
12.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.2 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
2T09I50QDBVRG4Q
ACTIVE
SOT-23
DBV
3
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PDCQ
TPS3809I50QDBVRQ1
ACTIVE
SOT-23
DBV
3
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PDCQ
TPS3809K33QDBVRQ1
ACTIVE
SOT-23
DBV
3
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PDBQ
TPS3809L30QDBVRQ1
ACTIVE
SOT-23
DBV
3
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PDAQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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