2U3838L30QDBVRG4Q1

TPS3836E18-Q1 / J25-Q1 / H30-Q1 / L30-Q1 / K33-Q1 TPS3837E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1, TPS3838E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1 NANOPOWER SUPERVISORY CIRCUITS SGLS141A − DECEMBER 2002 − REVISED JANUARY 2007 D Qualified for Automotive Applications D Customer-Specific Configuration Control D D D D D D D D Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Supply Current of 220 nA (Typ) Precision Supply Voltage Supervision Range: 1.8 V, 2.5 V, 3.0 V, 3.3 V Power-On Reset Generator With Selectable Delay Time of 10 ms or 200 ms Push/Pull RESET Output (TPS3836), RESET Output (TPS3837), or Open-Drain RESET Output (TPS3838) Manual Reset 5-Pin SOT-23 Package Temperature Range: −40°C to 125°C D Applications Include − Applications Using Automotive Low-Power DSPs, Microcontrollers, or Microprocessors − Battery-Powered Equipment − Intelligent Instruments − Wireless Communication Systems − Automotive Systems TPS3836, TPS3838 DBV PACKAGE (TOP VIEW) CT 1 GND 2 MR 3 5 VDD 4 RESET TPS3837 DBV PACKAGE (TOP VIEW) description The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing supervision, primarily for DSP and processor-based systems. CT 1 GND 2 MR 3 5 VDD 4 RESET During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above the threshold voltage VIT. When CT is connected to GND a fixed delay time of typical 10 ms is asserted. When connected to VDD the delay time is typically 200 ms. When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. All the devices of this family have a fixed-sense threshold voltage VIT set by an internal voltage divider. The TPS3836 has an active-low push-pull RESET output. The TPS3837 has active-high push-pull RESET, and TPS3838 integrates an active-low open-drain RESET output. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2007, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS3836E18-Q1 / J25-Q1 / H30-Q1 / L30-Q1 / K33-Q1 TPS3837E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1, TPS3838E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1 NANOPOWER SUPERVISORY CIRCUITS
SGLS141A − DECEMBER 2002 − REVISED JANUARY 2007 description (continued) TPS3836K33 VDD MSP430 VCC CT Xin RESET RST MR T Xout Quartz 32 kHz VSS GND Lithium Battery 3.6 V TYPICAL OPERATING CIRCUIT The product spectrum is designed for supply voltages of 1.8 V, 2.5 V, 3 V, and 3.3 V. The circuits are available in a 5-pin SOT-23 package. The TPS3836-Q-Q1, TPS3837-Q-Q1, TPS3838-Q-Q1 families are characterized for operation over a temperature range of −40°C to 125°C. PACKAGE INFORMATION TA −40°C 125°C 40 C to 125 C † DEVICE NAME THRESHOLD VOLTAGE SYMBOL TPS3836E18QDBVRQ1† 1.71 V PDNQ TPS3836J25QDBVRQ1† 2.25 V PDSQ TPS3836H30QDBVRQ1† 2.79 V PHRQ TPS3836L30QDBVRQ1† 2.64 V PCAQ TPS3836K33QDBVRQ1† 2.93 V PDTQ TPS3837E18QDBVRQ1† 1.71 V PDOQ TPS3837J25QDBVRQ1† 2.25 V PDRQ TPS3837L30QDBVRQ1† 2.64 V PCBQ TPS3837K33QDBVRQ1† 2.93 V PDUQ TPS3838E18QDBVRQ1† 1.71 V PDQQ TPS3838J25QDBVRQ1† 2.25 V PDPQ TPS3838L30QDBVRQ1† 2.64 V PCCQ TPS3838K33QDBVRQ1† 2.93 V PDVQ DBVR indicates tape and reel of 3000 parts. ORDERING INFORMATION TPS383 6 E 18 Q DBV R Q1 Automotive Designator Reel Package Q-Temperature Designator Nominal Supply Voltage Typical Reset Threshold Voltage Functionality Family 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
TPS3836E18-Q1 / J25-Q1 / H30-Q1 / L30-Q1 / K33-Q1 TPS3837E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1, TPS3838E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1 NANOPOWER SUPERVISORY CIRCUITS SGLS141A − DECEMBER 2002 − REVISED JANUARY 2007 FUNCTION TABLE TPS3836, TPS3837, TPS3838 † ‡ MR VDD > VIT RESET† RESET‡ L 0 L H L 1 L H H 0 L H H 1 H L TPS3836 and TPS3838 TPS3837 functional block diagram VDD CT R3 MR C1 R1 + S1 Reset Logic and Timer − Reset (TPS3837-Push-Pull) Reset (TPS3836-Push-Pull TPS3838-Open-Drain) R2 C2 S2 Band-Gap Reference S3 C3 Refresh Timer GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS3836E18-Q1 / J25-Q1 / H30-Q1 / L30-Q1 / K33-Q1 TPS3837E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1, TPS3838E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1 NANOPOWER SUPERVISORY CIRCUITS SGLS141A − DECEMBER 2002 − REVISED JANUARY 2007 timing diagram A B C D E F G VDD VIT < 1.1 V t MR t RESET t Undefined Output 4 td POST OFFICE BOX 655303 td • DALLAS, TEXAS 75265 td Undefined Output

TPS3836E18-Q1 / J25-Q1 / H30-Q1 / L30-Q1 / K33-Q1 TPS3837E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1, TPS3838E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1 NANOPOWER SUPERVISORY CIRCUITS SGLS141A − DECEMBER 2002 − REVISED JANUARY 2007 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t=1000 h continuously DISSIPATION RATING TABLE PACKAGE TA VIT, VDD < 3 V 220 500 VDD > VIT, VDD > 3 V 250 550 10 25 −40 −60 −25 VI = 0 V to VDD −200 V mV MR (see Note 4) VDD = 6 V V 0.2 1.64 Internal pullup resistor at MR Input capacitance at MR, CT MAX TPS383xJ25 VDD < VIT CI TYP TPS383xE18 Hysteresis at VDD input High-level High level input current MIN IOH = −2 mA −100 µA 25 nA −340 µA 25 nA 25 nA nA µA 30 kΩ 5 pF NOTES: 2. The lowest voltage at which RESET output becomes active. tr, VDD ≥ 15 µs/V 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminal. 4. If manual reset is unused, MR should be connected to VDD to minimize current consumption. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
TPS3836E18-Q1 / J25-Q1 / H30-Q1 / L30-Q1 / K33-Q1 TPS3837E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1, TPS3838E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1 NANOPOWER SUPERVISORY CIRCUITS SGLS141A − DECEMBER 2002 − REVISED JANUARY 2007 timing requirements at RL = 1 MΩ, CL = 50 pF, TA = 25_C PARAMETER tw Pulse width TEST CONDITIONS MIN TYP MAX UNIT at VDD VIH = VIT + 0.2 V, VIL = VIT − 0.2 V 6 µs at MR VDD ≥ VIT + 0.2 V, VIH = 0.7 × VDD VIL = 0.3 × VDD, 1 µs switching characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25_C PARAMETER TEST CONDITIONS VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD, CT = GND, See timing diagram td tPHL tPLH Delay time VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD, CT = VDD , See timing diagram Propagation (delay) time, high high-to-low-level to low level output Propagation (delay) time, low to high level output low-to-high-level VDD to RESET delay (TPS3836 TPS3838) (TPS3836, VDD to RESET delay (TPS3837) MIN 5 TYP MAX 10 UNIT 15 ms 100 200 300 VIL = VIT − 0.2 V, VIH = VIT + 0.2 V 10 VIL = 1.6 V 50 VIL = VIT − 0.2 V, VIH = VIT + 0.2 V 10 VIL = 1.6 V 50 0.1 µs 0.1 µs tPHL Propagation (delay) time, high-to-low-level output MR to RESET delay (TPS3836, TPS3838) VDD ≥ VIT + 0.2 V, tPLH Propagation (delay) time, low-to-high-level output MR to RESET delay (TPS3837) VIL = 0.7 × VDD VIL = 0.3 × VDD, µs µs TYPICAL CHARACTERISTICS Table of Graphs FIGURE IDD Supply current vs Supply voltage 1 IMR Manual reset current vs Manual reset voltage 2 VOL Low-level output voltage vs Low-level output current 3 VOH High-level output voltage vs High-level output current 4 Normalized reset threshold voltage vs Free-air temperature 5 Minimum pulse duration at VDD vs VDD Threshold overdrive 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS3836E18-Q1 / J25-Q1 / H30-Q1 / L30-Q1 / K33-Q1 TPS3837E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1, TPS3838E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1 NANOPOWER SUPERVISORY CIRCUITS
SGLS141A − DECEMBER 2002 − REVISED JANUARY 2007 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE MANUAL RESET CURRENT vs MANUAL RESET VOLTAGE 10 100 MR = Open CT = GND VDD = 6 V CT = GND IMR − Manual Reset Current − µA TA = 85°C IDD − Supply Current − µA 8 TA = 25°C 6 TA = 0°C 4 TA = −40°C 2 0 0 2 4 0 TA = −40°C −100 TA = 0°C −200 TA = 25°C −300 TA = 85°C −400 −500 −2 6 0 VDD − Supply Voltage − V Figure 1 6 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.0 2.0 VDD = 2 V MR = OPEN CT = GND VOH − High-Level Output Voltage − V VOL − Low-Level Output Voltage − V 4 Figure 2 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 1.5 TA = 25°C 1.0 TA = 85°C TA = 0°C 0.5 TA = −40°C 0.0 VDD = 2 V MR = OPEN CT = GND 1.5 TA = 85°C TA = 25°C 1.0 TA = 0°C 0.5 TA = −40°C 0.0 0 1 2 3 4 5 6 7 IOL − Low-Level Output Current − mA Figure 3 8 2 VMR − Manual Reset Voltage − V POST OFFICE BOX 655303 0 1 2 3 4 IOH − High-Level Output Current − mA Figure 4 • DALLAS, TEXAS 75265 5 TPS3836E18-Q1 / J25-Q1 / H30-Q1 / L30-Q1 / K33-Q1 TPS3837E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1, TPS3838E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1 NANOPOWER SUPERVISORY CIRCUITS SGLS141A − DECEMBER 2002 − REVISED JANUARY 2007 TYPICAL CHARACTERISTICS NORMALIZED RESET THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE Normalized Reset Threshold Voltage − V 1.001 1 0.999 0.998 0.997 CT = GND, MR = Open 0.996 0.995 −40 −15 10 35 60 TA − Free-Air Temperature − °C 85 Figure 5 MINIMUM PULSE DURATION AT VDD vs VDD THRESHOLD OVERDRIVE 22 MR = Open CT = GND TA = 25°C 20 Minimum Pulse Duration at VDD − µs
18 16 14 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VDD − Threshold Overdrive − V Figure 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 2U3838K33QDBVRG4Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PDVQ TPS3836J25QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PDSQ TPS3836K33QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PDTQ TPS3836L30QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PCAQ TPS3838K33QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PDVQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of