54ACT11030, 74ACT11030
8-INPUT POSITIVE-NAND GATES
SCLS050 – MARCH 1987 – REVISED APRIL 1993
•
•
•
•
54ACT11030 . . . J PACKAGE
74ACT11030 . . . D OR N PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
C
B
A
GND
Y
NC
NC
1
14
2
13
3
12
4
11
5
10
6
9
7
8
D
E
F
VCC
NC
G
H
54ACT11030 . . . FK PACKAGE
(TOP VIEW)
E
F
NC
V CC
NC
•
•
description
These devices contain a single 8-input NAND gate
and perform the following Boolean functions in
positive logic:
D
NC
C
NC
B
Y = A • B • C • D • E • F • G • H or
Y=A+B+C+D+E+F+G+H
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
G
NC
H
NC
NC
A
GND
NC
Y
NC
The 54ACT11030 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The 74ACT11030 is characterized for
operation from – 40°C to 85°C.
4
NC – No internal connection
FUNCTION TABLE
INPUTS
A THRU H
OUTPUT
Y
All inputs H
L
One or more inputs L
H
logic symbol†
A
B
C
D
E
F
G
H
3
logic diagram (positive logic)
&
A
2
B
1
C
14
5
13
D
Y
12
E
F
9
G
8
H
3
2
1
14
13
5
Y
12
9
8
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
54ACT11030, 74ACT11030
8-INPUT POSITIVE-NAND GATES
SCLS050 – MARCH 1987 – REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions
54ACT11030
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t /∆v
Low-level output current
TA
Operating free-air temperature
2–2
High-level input voltage
74ACT11030
MIN
2
2
0.8
High-level output current
VCC
VCC
0
0
– 24
24
Input transition rise or fall rate
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
V
0.8
V
VCC
VCC
V
– 24
mA
V
24
mA
0
10
0
10
ns/ V
– 55
125
– 40
85
°C
54ACT11030, 74ACT11030
8-INPUT POSITIVE-NAND GATES
SCLS050 – MARCH 1987 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
4.5 V
IOH = – 50 µA
VOH
IOH = – 24 mA
IOH = – 50 mA†
IOH = – 75 mA†
TA = 25°C
TYP
MAX
54ACT11030
MIN
MAX
IOL = 50 mA†
IOL = 75 mA†
MIN
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
MAX
V
3.85
4.5 V
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
5.5 V
0.1
VI = VCC or GND
VI = VCC or GND,
∆ICC‡
One input at 3.4 V,
Other inputs at VCC or GND
IO = 0
V
1.65
5.5 V
II
ICC
UNIT
3.85
5.5 V
IOL = 24 mA
74ACT11030
4.4
5.5 V
IOL = 50 µA
VOL
MIN
1.65
5.5 V
± 0.1
±1
±1
µA
5.5 V
4
80
40
µA
5.5 V
0.9
1
1
mA
Ci
VI = VCC or GND
5V
3.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A thru H
Y
MIN
TA = 25°C
TYP
MAX
54ACT11030
74ACT11030
MIN
MAX
MIN
MAX
1.5
5.4
8.1
1.5
8.8
1.5
8.5
1.5
5.9
7.8
1.5
9.3
1.5
8.7
UNIT
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
POST OFFICE BOX 655303
CL = 50 pF,
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
UNIT
41
pF
2–3
54ACT11030, 74ACT11030
8-INPUT POSITIVE-NAND GATES
SCLS050 – MARCH 1987 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
3V
Input
(see Note B)
From Output
Under Test
CL = 50 pF
(see Note A)
1.5 V
1.5 V
0V
tPHL
500 Ω
tPLH
50% VCC
Output
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
74ACT11030DR
Package Package Pins
Type Drawing
SOIC
D
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
9.0
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74ACT11030DR
SOIC
D
14
2500
356.0
356.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
74ACT11030D
D
SOIC
14
50
506.6
8
3940
4.32
74ACT11030DE4
D
SOIC
14
50
506.6
8
3940
4.32
74ACT11030N
N
PDIP
14
25
506
13.97
11230
4.32
74ACT11030N
N
PDIP
14
25
506
13.97
11230
4.32
Pack Materials-Page 3
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