74ACT16373DLR

SN54ACT16373, 74ACT16373 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996 D Members of the Texas Instruments D D D D D D D D Widebust Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True Outputs Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Shrink Small-Outline (DL) 300-mil Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings SN54ACT16373 . . . WD PACKAGE 74ACT16373 . . . DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE description The SN54ACT16373 and 74ACT16373 are 16-bit D-type transparent latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data (D) inputs if enable C is taken high. When C is taken low, the Q outputs are latched at the levels set up at the D inputs. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1C 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2C A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74ACT16373 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ACT16373 is characterized for operation over the full military temperature range of −55°C to 125°C. The 74ACT16373 is characterized for operation from −40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright © 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ACT16373, 74ACT16373 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996 FUNCTION TABLE INPUTS OE C D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol† 1OE 1C 2OE 2C 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 † 2 1 1EN 48 24 25 47 C1 2EN C4 1D 46 2 1 2 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 3D 35 1 4 14 33 16 32 17 30 19 29 20 27 22 26 23 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 SN54ACT16373, 74ACT16373 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996 logic diagram (positive logic) 1OE 1C 1 2OE 48 2C C1 1D1 47 2 1D 24 25 C1 1Q1 2D1 36 13 1D 2Q1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils. recommended operating conditions (see Note 3) SN54ACT16373 74ACT16373 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC Supply voltage (see Note 4) VIH High-level input voltage VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V IOH High-level output current −24 −24 mA IOL Low-level output current 24 24 mA Dt/Dv Input transition rise or fall rate TA Operating free-air temperature 2 2 0.8 V V 0 10 0 10 ns/V −55 125 −40 85 °C NOTES: 3. Unused inputs should be tied to VCC through a pullup resistor of approximately 5 kW or greater to prevent them from floating. 4. All VCC and GND pins must be connected to the proper voltage supply. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ACT16373, 74ACT16373 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = −50 50 mA A VOH 24 mA IOH = −24 VOL † ‡ MIN MAX 74ACT16373 MIN 4.4 4.4 4.4 5.4 5.4 5.4 4.5 V 3.94 3.7 3.8 5.5 V 4.94 4.7 4.8 5.5 V 5.5 V IOL = 24 mA SN54ACT16373 MAX 5.5 V mA{ IOL = 50 mA A TYP 4.5 V IOH = −50 mA{ IOH = −75 TA = 25°C MIN MAX UNIT V 3.85 3.85 4.5 V 0.1 0.1 5.5 V 0.1 0.1 0.1 0.1 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 V IOL = 50 mA{ 5.5 V IOL = 75 mA{ 5.5 V II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 mA IOZ VO = VCC or GND 5.5 V ±0.5 ±10 ±5 mA ICC VI = VCC or GND, 5.5 V 8 160 80 mA DICC} One input at 3.4 V, Other inputs at GND or VCC 5.5 V 0.9 1 1 mA Ci VI = VCC or GND 5V 4.5 pF Co VI = VCC or GND 5V 12 pF IO = 0 1.65 1.65 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54ACT16373 MIN MAX 74ACT16373 MIN MAX UNIT tw Pulse duration, LE high 4 4 1 ns tsu Setup time, data before LE↓ 1 1 1 ns th Hold time, data after LE↓ 5 5 5 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ 4 FROM (INPUT) TO (OUTPUT) D Q LE Q OE Q OE Q POST OFFICE BOX 655303 TA = 25°C SN54ACT16373 74ACT16373 MIN TYP MAX MIN MAX MIN MAX 3.8 7.9 9.4 3.8 11.8 3.8 11.1 3.1 8.2 9.7 3.1 13 3.1 12.3 4.6 9.3 10.8 4.6 13.7 4.6 12.8 4.5 9.1 10.5 4.5 13 4.5 12.2 3.1 8 9.5 3.1 13 3.1 12.1 3.8 9.4 11.1 3.8 15.1 3.8 14.2 5.3 8.6 9.9 5.3 11 5.3 10.7 4.3 7.4 8.7 4.3 9.8 4.3 9.4 • DALLAS, TEXAS 75265 UNIT ns ns ns ns SN54ACT16373, 74ACT16373 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP Outputs enabled Cpd Power dissipation capacitance per latch UNIT 43 pF CL = 50 pF, Outputs disabled f = 1 MHz pF 4.5 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω LOAD CIRCUIT 3V 1.5 V Timing Input 0V tw tsu 3V Input 1.5 V 1.5 V th 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS 3V Input 1.5 V 1.5 V 0V tPHL tPLH VOH In-Phase Output 50% VCC 50% VCC VOL VOH 50% VCC 50% VCC VOL 3V Output Waveform 2 S1 at GND (see Note B) 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL Out-of-Phase Output Output Control (low-level enabling) 50% VCC 20% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS [ VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 27-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9202401MXA ACTIVE CFP WD 48 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9202401MX A SNJ54ACT16373W D 74ACT16373DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16373 Samples 74ACT16373DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16373 Samples 74ACT16373DLRG4 ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16373 Samples SNJ54ACT16373WD ACTIVE CFP WD 48 1 Non-RoHS & Green SNPB N / A for Pkg Type 5962-9202401MX A SNJ54ACT16373W D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of