74ACT16540DLR

54ACT16540, 74ACT16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS186A − OCTOBER 1991 − REVISED APRIL 1996 D Members of the Texas Instruments D D D D D D D D D 54ACT16540 . . . WD PACKAGE 74ACT16540 . . . DL PACKAGE (TOP VIEW) Widebus™ Family Inputs Are TTL-Voltage Compatible Provide Extra Data Width Necessary for Wider Address/Data Paths Provide Inverted Data 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC™ (Enhanced-Performance Implanted CMOS) 1-μm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Shrink Small-Outline 300-mil (DL) Package Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings 1OE1 1Y1 1Y2 GND 1Y3 1Y4 VCC 1Y5 1Y6 GND 1Y7 1Y8 2Y1 2Y2 GND 2Y3 2Y4 VCC 2Y5 2Y6 GND 2Y7 2Y8 2OE1 description These 16-bit buffers/bus drivers provide a high-performance bus interface for wide data paths. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE2 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE2 The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The 74ACT16540 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16540 is characterized for operation over the full military temperature range of −55°C to 125°C. The 74ACT16540 is characterized for operation from −40°C to 85°C. FUNCTION TABLE (each 8-bit section) INPUTS A OUTPUT Y L L H L H L H X X Z X H X Z OE1 OE2 L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright © 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 54ACT16540, 74ACT16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS186A − OCTOBER 1991 − REVISED APRIL 1996 logic symbol† 1OE1 1 logic diagram (positive logic) 1OE1 & 48 1OE2 2OE1 2OE2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 † 24 EN1 1OE2 EN2 1A1 & 25 2 47 46 1 1 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 35 1 2 14 33 16 32 17 30 19 29 20 27 22 26 23 1 48 47 2 1Y1 1Y1 1Y2 To Seven Other Channels 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 2OE1 2OE2 2A1 24 25 36 13 2Y1 2Y1 2Y2 2Y3 2Y4 To Seven Other Channels 2Y5 2Y6 2Y7 2Y8 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum power package dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54ACT16540, 74ACT16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS186A − OCTOBER 1991 − REVISED APRIL 1996 recommended operating conditions (see Note 3) 54ACT16540 74ACT16540 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V IOH High-level output current −24 −24 mA IOL Low-level output current 24 24 mA Δt /Δv Input transition rise or fall rate TA Operating free-air temperature 2 2 V V 0.8 0 10 0 10 ns/ V −55 125 −40 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = − 50 μA A VOH IOH = − 24 mA IOH = − 75 mA† † ‡ TA = 25°C MIN TYP 54ACT16540 MAX IOL = 24 mA MIN MAX 74ACT16540 MIN 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.8 3.8 5.5 V 4.94 4.8 4.8 5.5 V IOL = 50 μA A VOL VCC 3.85 MAX UNIT V 3.85 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.44 0.44 5.5 V 0.36 0.44 0.44 1.65 1.65 V IOL = 75 mA† 5.5 V II VI = VCC or GND 5.5 V ± 0.1 ±1 ±1 μA IOZ VO = VCC or GND 5.5 V ± 0.5 ±5 ±5 μA ICC VI = VCC or GND, 5.5 V 8 80 80 μA ΔICC‡ One input at 3.4 V, Other inputs at VCC or GND 5.5 V 0.9 1 1 mA Ci VI = VCC or GND 5V 4 pF Co VO = VCC or GND 5V 13 pF IO = 0 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 54ACT16540, 74ACT16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS186A − OCTOBER 1991 − REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) A Y OE Y OE Y TA = 25°C 54ACT16540 74ACT16540 MIN TYP MAX MIN MAX MIN MAX 2.1 5.1 6.8 2.1 7.5 2.1 7.5 3.9 6.8 8.5 3.9 9.5 3.9 9.5 2.7 6.2 8 2.7 8.9 2.7 8.9 3.6 7.5 9.5 3.6 10.5 3.6 10.5 5.4 9.2 10.9 5.4 11.9 5.4 11.9 5.4 8.6 10.3 5.4 11.1 5.4 11.1 UNIT ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Outputs enabled Power dissipation capacitance per buffer Outputs disabled pF CL = 50 pF, TYP 42 f = 1 MHz 8.5 UNIT pF PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω LOAD CIRCUIT 3V 1.5 V Input 1.5 V 0V tPHL tPLH VOH In-Phase Output 50% VCC 50% VCC VOL VOH 50% VCC 50% VCC VOL 3V Output Waveform 2 S1 at GND (see Note B) 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL Out-of-Phase Output Output Control (low-level enabling) 50% VCC 20% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS [ VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 7-Jun-2010 PACKAGING INFORMATION Orderable Device 74ACT16540DL Status (1) OBSOLETE Package Type Package Drawing SSOP DL Pins Package Qty Eco Plan 48 TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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