74ALVCH16831DBBRG4

www.ti.com FEATURES • • • • Member of the Texas Instruments Widebus™ Family Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This 1-bit to 4-bit address register/driver is designed for 1.65-V to 3.6-V VCC operation. The device is ideal for use in applications in which a single address bus is driving four separate memory locations. The SN74ALVCH16831 can be used as a buffer or a register, depending on the logic level of the select (SEL) input. When SEL is logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by the two output-enable (OE) controls. Each OE controls two groups of nine outputs. When SEL is logic low, the device is in the register mode. The register is an edge-triggered D-type flip-flop. On the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers. OE controls operate the same as in buffer mode. When OE is logic low, the outputs are in a normal logic state (high or low logic level). When OE is logic high, the outputs are in the high-impedance state. SEL and OE do not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES083F – AUGUST 1996 – REVISED SEPTEMBER 2004 DBB PACKAGE (TOP VIEW) 4Y1 3Y1 GND 2Y1 1Y1 VCC NC A1 GND NC A2 GND NC A3 VCC NC A4 GND CLK OE1 OE2 SEL GND A5 A6 VCC A7 NC GND A8 NC GND A9 NC VCC 4Y9 3Y9 GND 2Y9 1Y9 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 33 48 34 47 35 46 36 45 37 44 38 43 39 42 40 41 1Y2 2Y2 GND 3Y2 4Y2 VCC 1Y3 2Y3 GND 3Y3 4Y3 GND 1Y4 2Y4 VCC 3Y4 4Y4 GND 1Y5 2Y5 3Y5 4Y5 GND 1Y6 2Y6 VCC 3Y6 4Y6 GND 1Y7 2Y7 GND 3Y7 4Y7 VCC 1Y8 2Y8 GND 3Y8 4Y8 NC − No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996–2004, Texas Instruments Incorporated SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES083F – AUGUST 1996 – REVISED SEPTEMBER 2004 ORDERING INFORMATION PACKAGE (1) TA -40°C to 85°C (1) TVSOP - DBB ORDERABLE PART NUMBER Tape and reel SN74ALVCH16831DBBR TOP-SIDE MARKING ALVCH16831 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OE OUTPUT SEL CLK A Y H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H LOGIC DIAGRAM (POSITIVE LOGIC) OE1 OE2 20 5 4 CLK 19 A1 D 3Y1 Q 1 22 To Eight Other Channels 2 2Y1 CLK 2 8 SEL 1Y1 21 4Y1 SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES083F – AUGUST 1996 – REVISED SEPTEMBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 4.6 V VO Output voltage range (2) (3) -0.5 VCC + 0.5 IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 IO Continuous output current Continuous current through each VCC or GND θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) impedance (4) -65 V -50 mA -50 mA ±50 mA ±100 mA 64 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V, maximum. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 UNIT V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 × VCC VCC = 1.65 V to 1.95 V VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2.7 V to 3.6 V IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) V 0.8 VCC = 1.65 V -4 VCC = 2.3 V -12 VCC = 2.7 V -12 VCC = 3 V -24 VCC = 1.65 V 4 VCC = 2.3 V 12 VCC = 2.7 V 12 VCC = 3 V 24 -40 mA mA 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES083F – AUGUST 1996 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -100 µA 1.65 V to 3.6 V 1.65 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA IOH = -12 mA V 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 V ±5 VI = VCC or GND 3.6 V VI = 0.58 V 1.65 V 25 VI = 1.07 V 1.65 V -25 VI = 0.7 V 2.3 V 45 VI = 1.7 V 2.3 V -45 VI = 0.8 V 3V 75 3V -75 VI = 2 V UNIT 1.2 1.65 V to 3.6 V IOL = 24 mA II(hold) MAX IOL = 4 mA IOL = 12 mA II TYP (1) VCC - 0.2 IOH = -4 mA VOH VOL MIN µA µA 3.6 V ±500 IOZ VO = VCC or GND 3.6 V ±10 µA ICC VI = VCC or GND, IO = 0 3.6 V 40 µA ∆ICC One input at VCC - 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA VI = 0 to 3.6 Control inputs Ci Data Inputs Co (1) (2) Outputs V (2) VI = VCC or GND 3.3 V VO = VCC or GND 3.3 V 4.5 pF 5 7.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V MIN fclock MAX VCC = 2.5 V ± 0.2 V MIN (1) Clock frequency MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 UNIT MAX 150 MHz tw Pulse duration, CLK high or low (1) 3.3 3.3 3.3 ns tsu Setup time, A data before CLK↑ (1) 2 2 1.6 ns th Hold time, A data after CLK↑ (1) 0.7 0.5 1.1 ns (1) 4 This information was not available at the time of publication. SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES083F – AUGUST 1996 – REVISED SEPTEMBER 2004 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) MIN CLK (1) OE MIN 150 MAX 150 MIN UNIT MAX 150 MHz 4 4.1 1.6 3.6 (1) 1.1 4.5 4.4 1.5 3.9 (1) 1.3 5.2 5.2 1.7 4.4 Y (1) 1.1 5.1 5 1.2 4.3 ns Y (1) 1.4 5.5 4.7 1.6 4.5 ns SEL tdis MAX 1.2 Y OE MIN VCC = 3.3 V ± 0.3 V VCC = 2.7 V (1) A ten TYP (1) fmax tpd VCC = 2.5 V ± 0.2 V VCC = 1.8 V ns This information was not available at the time of publication. OPERATING CHARACTERISTICS TA = 25°C PARAMETER Power dissipation Cpd capacitance per bit (four outputs switching) (1) TEST CONDITIONS All outputs enabled All outputs disabled CL = 0, f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) 119 132 (1) 22 25 UNIT pF This information was not available at the time of publication. 5 SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES083F – AUGUST 1996 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V tw VI Timing Input VM VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VM VM 0V tPLH Output Control (low-level enabling) tPLZ VLOAD/2 VM tPZH VOH VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPHL VM VI VM tPZL VI Input VOLTAGE WAVEFORMS PULSE DURATION th VI Data Input VM 0V 0V tsu Output VI VM Input Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VOH VM VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 MECHANICAL DATA MTSS005D – JANUARY 1995 – REVISED MARCH 2002 DBB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 80 PINS SHOWN 0,23 0,13 0,40 80 0,07 M 41 6,20 6,00 8,30 7,90 0,20 0,09 1 Gage Plane 40 A 0,25 0°–ā8° 0,75 0,45 Seating Plane 1,20 MAX 0,15 0,05 PINS** 0,08 80 100 A MAX 17,10 20,90 A MIN 16,90 20,70 DIM 4040212 / E 03/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC : 80 Pin – MO-153 Variation FF 100 Pin – MO-194 Variation BB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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