74CBTLV3857DGVRG4

       

     

 
SCDS085E − OCTOBER 1998 − REVISED OCTOBER 2003 D Enable Signal Is SSTL_2 Compatible D Flow-Through Architecture Optimizes PCB DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) Layout VREF A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND D Designed for Use With 200 Mbit/s Double D D D D D D Data-Rate (DDR) SDRAM Applications Switch On-State Resistance Is Designed to Eliminate Series Resistor to DDR SDRAM Internal 10-kΩ Pulldown Resistors to Ground on B Port Internal 50-kΩ Pullup Resistor on Output-Enable Input Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 description/ordering information This 10-bit FET bus switch is designed for 3-V to 3.6-V VCC operation and SSTL_2 output-enable (OE) input levels. When OE is low, the 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. There are 10-kΩ pulldown resistors to ground on the B port. The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data path. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. ORDERING INFORMATION QSOP − DBQ −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA Tape and reel SN74CBTLV3857DBQR Tube SN74CBTLV3857DW Tape and reel SN74CBTLV3857DWR TSSOP − PW Tape and reel SN74CBTLV3857PWR TVSOP − DGV Tape and reel SN74CBTLV3857DGVR SOIC − DW TOP-SIDE MARKING CL857 CBTLV3857 CL857 CL857 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUT OE FUNCTION L A port = B port H Disconnect Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated     !"#$ % &'!!($ #%  )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
       

     

 
SCDS085E − OCTOBER 1998 − REVISED OCTOBER 2003 logic diagram (positive logic) 22 2 A1 B1 SW RINT 13 11 A10 B10 SW RINT VCC OE VREF 23 1 simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range (OE only), VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input voltage range (except OE), VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
       

     

 
SCDS085E − OCTOBER 1998 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) MIN VCC VREF Supply voltage VIH VIL AC high-level control input voltage VIH VIL DC high-level control input voltage Reference voltage (0.38 × VCC) NOM MAX UNIT 3 3.3 3.6 V 1.15 1.25 1.35 V VREF + 350 mV V AC low-level control input voltage VREF − 350 mV VREF + 180 mV V V DC low-level control input voltage VREF − 180 mV V TA Operating free-air temperature −40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II TEST CONDITIONS VCC = 3 V, MIN TYP† II = −18 mA UNIT −1.2 V OE ±1 A port ±5 µA ±1 mA B port VCC = 3.6 V, VI = VCC or GND VCC = 3.6 V, VI = 3 V or 0 IO = 0, VO = 3 V or 0, OE = VCC VREF ICC Ci MAX Control inputs Cio(OFF) ron‡ VI = VCC or GND µA mA pF 5 pF VI = 0, VI = 0.9 V, II = 24 mA II = 24 mA 5 6 11 VI = 1.25 V, II = 24 mA 7 13 VI = 1.6 V, II = 24 mA 9 40 VCC = 0 roff‡ ±5 25 3.5 VCC = 3 V mA 8 Ω 1 MΩ VCC = 3 V to 3.6 V, VI = 1.65 V, OE = VCC 1 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. Resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd§ A or B B or A ten OE A or B OE A or B PARAMETER tdis VCC = 3.3 V ± 0.3 V MIN UNIT MAX 0.25 ns 1.4 4.2 ns 1.4 4.8 ns § The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
       

     

 
SCDS085E − OCTOBER 1998 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V AND VDDQ = 2.5 ± 0.2 V 500 Ω From Output Under Test VDDQ × 2 Open S1 GND CL = 50 pF (see Note A) 500 Ω Output Control LOAD CIRCUIT TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VDDQ × 2 GND VREF† Input VDDQ/2 VDDQ/2 0V tPLH Output Output Waveform 1 S1 at 2 × VDDQ (see Note B) VOH VDDQ/2 VOL VDDQ/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VDDQ VDDQ/2 tPZH tPHL VIH (AC)‡ VIL (AC)§ tPZL VDDQ VREF† Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VDDQ/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES † VREF = 0.38 × VCC ‡ VIH(AC) = VREF + 350 mV § VIL(AC) = VREF − 350 mV NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) 74CBTLV3857DBQRE4 ACTIVE SSOP/QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 74CBTLV3857DBQRG4 ACTIVE SSOP/QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 74CBTLV3857DGVRE4 ACTIVE TVSOP DGV 24 TBD Call TI Call TI 74CBTLV3857DGVRG4 ACTIVE TVSOP DGV 24 TBD Call TI Call TI 74CBTLV3857DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CBTLV3857DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CBTLV3857PWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CBTLV3857PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV3857DBQR ACTIVE SSOP/QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74CBTLV3857DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV3857DWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV3857DWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV3857DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV3857PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2011 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74CBTLV3857DBQR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP/ QSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74CBTLV3857DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74CBTLV3857PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CBTLV3857DBQR SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0 SN74CBTLV3857DWR SOIC DW 24 2000 346.0 346.0 41.0 SN74CBTLV3857PWR TSSOP PW 24 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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