74GTLPH1627DGGRE4

SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356C – JUNE 2001 – REVISED FERUARY 2003 D D D D D D D D D D D D D D DGG PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels GTLP Buffered SYSCLK Signal (SSCLK) for Source-Synchronous Applications LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Outputs (100 mA) LVTTL Outputs (–24 mA/24 mA) GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DIR OE A1 A2 GND A3 VCC A4 A5 CMS A6 GND A7 A8 A9 VCC A10 GND A11 A12 GND A13 A14 GND A15 VCC A16 GND A17 A18 CLKOUT CKOE description/ordering information 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 FSTA BIAS VCC B1 B2 GND B3 ERC B4 B5 VREF B6 GND B7 B8 B9 VCC B10 GND B11 B12 GND B13 B14 GND B15 VCC B16 GND B17 B18 SSCLK SYSCLK ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 85°C TSSOP – DGG Tape and reel SN74GTLPH1627DGGR GTLPH1627 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC, TI-OPC, and Widebus are trademarks of Texas Instruments. Copyright  2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356C – JUNE 2001 – REVISED FERUARY 2003 description (continued) The SN74GTLPH1627 is a high-drive, 18-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent and latched modes of data transfer. Additionally, with the use of the clock-mode select (CMS) input, the device can be used in source-synchronous and clock-synchronous applications. Source-synchronous applications require the skew between the clock output and data output to be minimized for optimum maximum-frequency system performance. In order to reduce this skew, a flexible setup time adjustment (FSTA) feature is incorporated into the device that sets a predetermined delay between the clock and data. The CMS and direction (DIR) inputs control the mode of the device. The system clock (SYSCLK) and CLKOUT pins are LVTTL compatible, while the source synchronous I/O is GTLP compatible. The benefits include compensation for output-to-output skew coming from the driver itself, and compensation for process skew if more than one driver is used. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP’s reduced output swing ( VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356C – JUNE 2001 – REVISED FERUARY 2003 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High level input voltage High-level VIL Low level input voltage Low-level IIK IOH Input clamp current High-level output current IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 VCC VTT 5.5 B port and SSCLK Except B port and SSCLK B port and SSCLK Except B port and SSCLK VREF+0.05 2 B port and SSCLK V V V V VREF–0.05 0.8 V –18 mA A port and CLKOUT –24 mA A port and CLKOUT 24 Except B port and SSCLK B port and SSCLK 100 Outputs enabled 10 –40 ns/V µs/V 20 Operating free-air temperature mA 85 °C NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but generally, GND is connected first. 6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. 7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356C – JUNE 2001 – REVISED FERUARY 2003 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A portt and d CLKOUT A portt and d CLKOUT VOL B port and SSCLK TEST CONDITIONS MIN VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3 3.15 15 V IOH = –12 mA IOH = –24 mA TYP† MAX UNIT –1.2 V VCC–0.2 2.4 V 2 IOL = 100 µA IOL = 12 mA 0.2 0.5 VCC = 3.15 V to 3.45 V, IOL = 24 mA IOL = 100 µA 0.2 VCC = 3.15 V IOL = 10 mA IOL = 64 mA IOL = 100 mA 0.55 VCC = 3.15 V to 3.45 V, VCC = 3 3.15 15 V 0.4 0.2 V 0.4 SYSCLK and control inputs VCC = 3.45 V, VI = 0 to 5.5 V ±10 B port and SSCLK VCC = 3.45 V, VREF within 0.6 V of VTT, VO = 0 to 2.3 V ±10 CLKOUT VCC = 3.45 V, VO = 0 to 5.5 V ±10 IOZH‡ IOZL‡ A port VCC = 3.45 V, VO = VCC 10 µA A port VCC = 3.45 V, VO = GND –10 µA IBHL§ IBHH¶ A port VCC = 3.15 V, VCC = 3.15 V, VI = 0.8 V VI = 2 V IBHLO# IBHHO|| A port VCC = 3.45 V, VCC = 3.45 V, VI = 0 to VCC VI = 0 to VCC VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND, VI (B port) = VTT or GND Outputs high 50 Outputs low 50 Outputs disabled 50 II IOZ‡ ICC A port A port t B port, t or A port, SSCLK Ci Ciio SYSCLK inputs Control inputs A port B port or SSCLK VI = 3.15 V or 0 VI = 3.15 V or 0 VO = 3.15 V or 0 VO = 1.5 V or 0 µA 75 µA –75 µA 500 µA µA –500 VCC = 3.45 V, One A-port or control input at VCC – 0.6 V, Other A-port or control inputs at VCC or GND ∆ICCk µA 1.5 4 5 3.5 5.5 7.5 9.5 9.5 12 mA mA pF pF Co CLKOUT VO = 3.15 V or 0 6 7.5 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For I/O ports, the parameter II includes the off-state output leakage current. § The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. ¶ The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. # An external driver must source at least IBHLO to switch this node from low to high. || An external driver must sink at least IBHHO to switch this node from high to low. k This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356C – JUNE 2001 – REVISED FERUARY 2003 hot-insertion specifications for A port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT 10 µA VO = 0.5 V to 3 V, VI or VO = 0 to 5.5 V OE = 0 ±30 µA VO = 0.5 V to 3 V, OE = 0 ±30 µA Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, IOZPD VCC = 1.5 V to 0, live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS µA ±30 µA BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA 5 mA 10 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V VO IO VCC = 0, UNIT BIAS VCC = 0, BIAS VCC = 0, VCC = 3.15 V to 3.45 V VCC = 0, MAX 10 VCC = 0, VCC = 0 to 1.5 V, ICC (BIAS VCC) MIN VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 Ioff IOZPU BIAS VCC = 3 3.15 15 V to 3 3.45 45 V V, VO (B port) = 0 to 1.5 15V BIAS VCC = 3.3 V, IO = 0 VO (B port) = 0.6 V BIAS VCC = 3.15 V to 3.45 V, 0.95 1.05 V µA –1 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time SYSCLK (A to B) or (B to A) high or low 2.5 SYSCLK to CLKOUT high or low 2.8 SYSCLK to SSCLK (FSTA GND) high or low 2.8 SYSCLK to SSCLK (FSTA VCC) high or low 2.3 SSCLK (B to A) high or low 2.8 SSCLK to CLKOUT high or low 2.8 CKOE (A to B) or (B to A) high 2.5 A before SYSCLK↑ 1.1 B before SYSCLK↑ 2.2 B before SSCLK↑ 1.6 A before CKOE↓ 1.4 B before CKOE↓ 0.8 A after SYSCLK↑ 0.3 B after SYSCLK↑ 0.7 B after SSCLK↑ 1.1 A after CKOE↓ 0 B after CKOE↓ 0.7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 175 MHz ns ns ns 9 SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356C – JUNE 2001 – REVISED FERUARY 2003 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER CLOCK SYSCLK fmax SSCLK – – tpd d FROM (INPUT) – – EDGE RATE† FSTA MIN A or B B or A – – 175 SYSCLK CLKOUT – – 175 SYSCLK SSCLK – GND 175 SYSCLK SSCLK – 150 B A – VCC – SSCLK CLKOUT A B CKOE B SYSCLK B – – TO (OUTPUT) 175 – 2.3 6.2 Slow – 3 7.3 Fast – 2.6 6 Slow – 3.1 7.6 Fast – 2.6 6 Slow – B Fast – ten tdis – OE B Slow – tr – Rise time,, B and SSCLK outputs (20% to 80%) tf – Fall time,, B and SSCLK outputs (80% to 20%) Fast Slow Fast Slow 3 7.1 2.3 5.1 2.7 5.5 2.9 6 3.6 6.6 1.1 – 1.8 – – – 1.5 4.6 – CKOE A – – 2.1 6 – SYSCLK A – – 1.9 6 – SSCLK A – – 2.3 6.6 – SYSCLK CLKOUT – – 3.3 8.3 – SSCLK CLKOUT – – 3.7 9 1.6 5 2.1 6.4 2 5.2 2.4 6.1 – OE A – – ten tdis – CKOE CLKOUT – – POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns 2.4 A ten tdis ns ns 2.1 B † Slow (ERC = H) and Fast (ERC = L) ‡ All typical values are at VCC = 3.3 V, TA = 25°C. 10 175 – OE UNIT MHz – – tpd d MAX Fast ten tdis – TYP‡ ns ns ns SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356C – JUNE 2001 – REVISED FERUARY 2003 skew characteristics over recommended ranges of supply voltage and operating free-air temperature, VREF = 1 V (unless otherwise noted); standard lumped loads, CL = 30 pF for B port (see Figure 1)† PARAMETER tsk(LH)§ tsk(HL)§ tsk(LH)§ tsk(HL)§ tsk(LH)§ tsk(HL)§ tsk(LH)§ tsk(HL)§ tsk(LH)§ tsk(HL)§ tsk(LH)§ tsk(HL)§ FROM (INPUT) TO (OUTPUT) EDGE RATE‡ FSTA SYSCLK B F t Fast – SYSCLK B Sl Slow – SYSCLK SSCLK + ∆B (see Figure 2) SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK tsk(t)§ SYSCLK tsk(prLH)¶ tsk(prHL)¶ SYSCLK TEST CONDITIONS MIN MAX 0.5 0.5 0.5 SSCLK + ∆B (see Figure 2) SSCLK + ∆B (see Figure 2) SSCLK + ∆B (see Figure 2) SSCLK + ∆B (see Figure 2) SSCLK + ∆B (see Figure 2) SSCLK + ∆B (see Figure 2) SSCLK + ∆B (see Figure 2) B Fast Fast GND GND 0.5 VCC = 3.15 V, T = 85°C 3.2 4.6 VCC = 3.3 V, T = 25°C 2.9 4.3 VCC = 3.45 V, T = –40°C 2.8 4.1 VCC = 3.15 V, T = 85°C 3.6 5 VCC = 3.3 V, T = 25°C 3.4 4.8 VCC = 3.45 V, T = –40°C 3.3 4.6 VCC = 3.15 V, T = 85°C Slow Slow Fast GND GND VCC 3 4.6 VCC = 3.3 V, T = 25°C 2.6 4.3 VCC = 3.45 V, T = –40°C 2.4 4 VCC = 3.15 V, T = 85°C 3.7 5.2 VCC = 3.3 V, T = 25°C 3.6 5.1 VCC = 3.45 V, T = –40°C 3.5 5 VCC = 3.15 V, T = 85°C 6.5 8.3 VCC = 3.3 V, T = 25°C 6.3 8.2 VCC = 3.45 V, T = –40°C 5.6 7.4 7 8.7 VCC = 3.3 V, T = 25°C 6.5 8.3 VCC = 3.45 V, T = –40°C 6.2 8 VCC = 3.15 V, T = 85°C 6.4 8.3 VCC = 3.3 V, T = 25°C 5.9 7.7 VCC = 3.45 V, T = –40°C 5.5 7.4 VCC = 3.15 V, T = 85°C 7.2 8.9 VCC = 3.3 V, T = 25°C 6.8 8.6 VCC = 3.45 V, T = –40°C 6.6 8.3 VCC = 3.15 V, T = 85°C Fast Slow Slow VCC VCC VCC Fast – 1.4 Slow – 2 – – 1.8 B 2.8 UNIT ns ns ns ns ns ns ns ns ns ns ns ns † Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. ‡ Slow (ERC = H) and Fast (ERC = L) § tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature. The specifications apply to any outputs switching in the same direction, either high to low [tsk(HL)], low to high [tsk(LH)] or in opposite directions, both low to high and high to low [tsk(t)]. ¶ tsk(prLH) or tsk(prHL) – Part-to-part skew is designed as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst-case VCC and temperature. Furthermore, these values are provided by SPICE simulations. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356C – JUNE 2001 – REVISED FERUARY 2003 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION tsu th VOH Data Input VM VM 0V 3V Input 1.5 V 1.5 V 0V tPLH tPHL VOLTAGE WAVEFORMS SETUP AND HOLD TIMES (VM = 1.5 V for A port and 1 V for B port) (VOH = 3 V for A port and 1.5 V for B port) VOH Output 1V 1V 3V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1V 1V 0V tPLH 1.5 V 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ tPZH tPHL VOH Output 1.5 V tPZL 1.5 V Input Output Control 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) 1.5 V VOH VOH – 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. Load circuit for A outputs also is used for CLKOUT; load circuit for B outputs also is used for SSCLK. Figure 1. Load Circuits and Voltage Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356C – JUNE 2001 – REVISED FERUARY 2003 1.5 V 12.5 Ω From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS A SYSCLK SYSCLK to B tPLH SYSCLK to B tPHL B1 ∆B ∆B B18 SYSCLK to SSCLK FSTA (Fast) SYSCLK to SSCLK FSTA (Fast) SYSCLK to SSCLK FSTA (Slow) SYSCLK to SSCLK FSTA (Slow) SSCLK NOTES: A. B. C. D. tsk(LH) FSTA (Fast) tsk(HL) FSTA (Fast) tsk(LH) FSTA (Slow) tsk(HL) FSTA (Slow) CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. The outputs are measured one at a time with one transition per measurement. Load circuit for B outputs also is used for SSCLK. Figure 2. Load Circuit and SYSCLK to SSCLK + ∆B Skew Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN74GTLPH1627 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS SCES356C – JUNE 2001 – REVISED FERUARY 2003 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application is probably a distributed load. The physical representation is shown in Figure 3. This backplane, or distributed load, can be closely approximated to a resistor inductance capacitance (RLC) circuit, as shown in Figure 4. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer to better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 1.5 V ZO = 50 Ω .25” 1” 1” .25” 1.5 V 22 Ω 22 Ω 1.5 V 11 Ω Conn. 1” Conn. 1” Conn. 1” Conn. From Output Under Test 1” Rcvr Rcvr Rcvr Slot 2 Slot 19 Slot 20 LL = 14 nH Test Point CL = 18 pF Drvr Slot 1 Figure 4. High-Drive RLC Network Figure 3. High-Drive Test Backplane switching characteristics over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 4) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL FROM (INPUT) A SYSCLK TO (OUTPUT) EDGE RATE† FSTA Fast – B 4.2 5.6 – Fast – Slow – Fast – 0.9 B 4.9 4.5 5.5 ns 5.2 Rise time,, B and SSCLK outputs (20% to 80%) Slow – 1.3 tf Fall time,, B and SSCLK outputs (80% to 20%) Fast – 2.3 Slow – 2.7 • DALLAS, TEXAS 75265 ns 5.2 tr POST OFFICE BOX 655303 UNIT 4.8 Slow † Slow (ERC = H) and Fast (ERC = L) ‡ All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. 14 TYP‡ ns ns MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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