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SN74LVC1G139
SCES602D – AUGUST 2004 – REVISED AUGUST 2015
SN74LVC1G139 2-to-4 Line Decoder
1 Features
3 Description
•
This 2-to-4 line decoder is designed for 1.65-V to
5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to VCC
Maximum tpd of 4.9 ns at 3.3 V and 15 pF
Low Power Consumption, 10-µA Maximum ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
AV Receivers
Solid State Drives (SSDs): Client and Enterprise
TVs: LCD/Digital and High-Definition (HDTVs)
Tablets: Enterprise
Video Analytics: Server
The LVC1G139 2-line to 4-line decoder is designed
to be used in high-performance memory-decoding or
data-routing applications requiring very short
propagation delay times. In high-performance
memory systems, this decoder can be used to
minimize the effects of system decoding. When used
with high-speed memories using a fast enable circuit,
the delay times of these decoders and the enable
time of the memory usually are less than the typical
access time of the memory. This means that the
effective system delay introduced by the decoder is
negligible.
NanoStar and NanoFree package technology is a
major breakthrough in IC packaging concepts, using
the die as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G139DC
T
SM8 (8)
2.95 mm × 2.80 mm
SN74LVC1G139DC
U
VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC1G139YZ
P
DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
A
1
3
Y3
Select
Inputs
B
2
5
Y2
Data
Outputs
6
7
Y1
Y0
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G139
SCES602D – AUGUST 2004 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specification...........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
3
4
4
5
5
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2005) to Revision D
•
Page
Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical
Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision B (December 2005) to Revision C
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Updated Features. .................................................................................................................................................................. 1
•
Removed Ordering Information table. .................................................................................................................................... 1
2
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SCES602D – AUGUST 2004 – REVISED AUGUST 2015
5 Pin Configuration and Functions
DCT Package
8-Pin SM8
Top View
DCU Package
8-Pin VSSOP
Top View
A
1
8
VCC
B
2
7
Y0
Y3
3
6
Y1
GND
4
5
Y2
A
B
Y3
GND
1
2
3
8
7
6
4
5
VCC
Y0
Y1
Y2
YZP Package
8-Pin DSBGA
Bottom View
GND
Y3
B
A
4 5
3 6
2 7
1 8
Y2
Y1
Y0
VCC
See mechanical drawings for dimensions.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A
1
I
Adress input, bit 0
B
2
I
Adress input, bit 1
Y3
3
O
Output 3, low when B is high and A is high
GND
4
—
Ground
Y2
5
O
Output 2, low when B is high and A is low
Y1
6
O
Output 1, low when B is low and A is high
Y0
7
O
Output 0, low when B is low and A is low
VCC
8
—
Power pin
6 Specification
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
6.5
V
VI
Input voltage
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
V
(2)
VO
Voltage applied to any output in the high-impedance or power-off state
VO
Voltage applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
ICC
Continuous current through VCC or GND
±100
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
-65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
Machine model
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
Operating
Data retention only
High-level input voltage
MAX
5.5
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
1.65
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 3 V to 3.6 V
V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VIL
Low-level input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 4.5 V to 5.5 V
0.3 × VCC
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
Low-level output current
Δt/Δv
TA
(1)
4
Input transition rise or fall rate
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
15
VCC = 5 V ± 0.5 V
10
Operating free-air temperature
mA
–24
VCC = 4.5 V
IOL
V
–40
85
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74LVC1G139
THERMAL METRIC (1)
DCT (SM8)
DCU (VSSOP)
YZP (DSBGA)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
194
195
106
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
124
74
1.6
°C/W
RθJB
Junction-to-board thermal resistance
106
74
11
°C/W
ψJT
Junction-to-top characterization parameter
48
6.7
3.1
°C/W
ψJB
Junction-to-board characterization parameter
105
73
11
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
IOL = 100 µA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC
Ci
VI = VCC or GND
IO = 0
V
0.4
0.55
4.5 V
VI = 5.5 V or GND
Ioff
(1)
3.8
3V
IOL = 32 mA
A or B inputs
2.3
4.5 V
IOL = 24 mA
II
V
IOH = –32 mA
IOL = 16 mA
UNIT
2.4
3V
IOH = –24 mA
MAX
VCC – 0.1
IOH = –4 mA
IOH = –16 mA
VOL
MIN TYP (1)
VCC
0.55
0 to 5.5 V
±1
µA
0
±5
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
Other inputs at VCC or
– 0.6 V,
GND
3.3 V
4
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
TEST
CONDITIONS
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN MAX
VCC = 3.3 V
± 0.3 V
MIN MAX
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN MAX
See Figure 2
2.7
15.3
1.5
7.5
0.9
4.9
0.8
3.6
See Figure 3
3
16.7
1.6
8.2
1.2
5.9
1.1
4.2
ns
6.7 Operating Characteristics
TA = 25°C
PARAMETER
Cpd (1)
(1)
Power dissipation capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
31
34
36
39
UNIT
pF
Two outputs switching.
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6.8 Typical Characteristics
8
Long tpLH
Propagation Delay (nS)
7
Long tpHL
6
Short tpHL
5
Short tpLH
4
3
2
1
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VCC (V)
5.0
C001
Short is 2 inverter path; Long is 3 inverter path.
Figure 1. Propagation Delay vs. VCC
6
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The LVC1G139 decodes the 2-bit input to one of the four outputs. The B input is the most significant bit and the
Y outputs are active low. The propagation delays are very short and well matched (see Figure 1). Supply voltage
from 1.65-V to 5.5-V is supported.
8.2 Functional Block Diagram
A
1
3
Y3
Select
Inputs
B
2
5
Y2
Data
Outputs
6
7
Y1
Y0
8.3 Feature Description
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as
the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC1G139.
Table 1. Function Table
INPUTS
OUTPUTS
B
A
Y0
Y1
Y2
Y3
L
L
L
H
H
H
L
H
H
L
H
H
H
L
H
H
L
H
H
H
H
H
H
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G139 device is a 2-of-4 decoder and demultiplexer. This device decodes the 2-bit address on
inputs A (bit 0) and B (bit 1) then provides a logic low on the matching address output. It can produce 24 mA of
drive current at 3.3 V, making it ideal for driving multiple outputs.
9.2 Typical Application
This is an address line decoder using a 16-bit bus example; address bus lines 14 and 15 are decoded and drive
four active low chip selects. Each output covers 16k address space mapped by the address bus lines 0 through
13.
GND
SN74LVC1G139
PF
VCC
Address line 14
1 A
VCC 8
Address line 15
2 B
Y0 7
Chip Select 0
Chip Select 3
3 Y3
Y1 6
Chip Select 1
GND Plane
4 GND
Y2 5
Chip Select 2
Figure 4. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the
high drive will also create faster edges into light loads so routing and load conditions should be considered to
prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
10
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Typical Application (continued)
9.2.3 Application Curve
9
VCC=5V
8
VCC=3.3V
7
VCC=2.5V
ICC (mA)
6
VCC=1.8V
5
4
3
2
1
0
0
5
10
15
20
25
30
Frequency (MHz)
35
40
C001
Figure 5. ICC vs Frequency
Load is 15 pF
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC terminals then 0.01-μF or 0.022-μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G139
11
SN74LVC1G139
SCES602D – AUGUST 2004 – REVISED AUGUST 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoStar, NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
Submit Documentation Feedback
Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G139
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74LVC1G139DCTRE4
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
C39
Z
74LVC1G139DCTTE4
ACTIVE
SM8
DCT
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
C39
Z
74LVC1G139DCURE4
ACTIVE
VSSOP
DCU
8
TBD
Call TI
Call TI
-40 to 85
74LVC1G139DCUTG4
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
C39R
SN74LVC1G139DCTR
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
C39
Z
SN74LVC1G139DCTT
ACTIVE
SM8
DCT
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
C39
Z
SN74LVC1G139DCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(C39Q ~ C39R)
SN74LVC1G139DCUT
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(C39Q ~ C39R)
SN74LVC1G139YZPR
ACTIVE
DSBGA
YZP
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
DFN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
12-Sep-2016
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
74LVC1G139DCUTG4
VSSOP
DCU
8
250
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC1G139DCTR
SM8
DCT
8
3000
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74LVC1G139DCTT
SM8
DCT
8
250
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74LVC1G139DCUR
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC1G139DCUR
VSSOP
DCU
8
3000
178.0
9.5
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC1G139DCUT
VSSOP
DCU
8
250
178.0
9.5
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC1G139YZPR
DSBGA
YZP
8
3000
178.0
9.2
1.02
2.02
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74LVC1G139DCUTG4
VSSOP
DCU
SN74LVC1G139DCTR
SM8
DCT
8
250
202.0
201.0
28.0
8
3000
182.0
182.0
20.0
SN74LVC1G139DCTT
SM8
DCT
8
250
182.0
182.0
20.0
SN74LVC1G139DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74LVC1G139DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74LVC1G139DCUT
VSSOP
DCU
8
250
202.0
201.0
28.0
SN74LVC1G139YZPR
DSBGA
YZP
8
3000
220.0
220.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
D: Max = 1.918 mm, Min =1.858 mm
E: Max = 0.918 mm, Min =0.858 mm
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