Not Recommended For New Designs
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
www.ti.com
SCES145C – OCTOBER 1998 – REVISED JUNE 2005
FEATURES
•
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•
•
•
•
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•
•
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Member of the Texas Instruments Widebus+™
Family
UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, or Clocked Modes
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.4 ns at 3.3 V
Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) > 2 V at
VCC = 3.3 V, TA = 25°C
Simultaneously Generates and Checks Parity
Option to Select Generate Parity and Check or
Feedthrough Data/Parity in A-to-B or B-to-A
Direction
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC)
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class I
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DGG PACKAGE
(TOP VIEW)
1CLKENAB
LEAB
CLKAB
1ERRA
1APAR
GND
1A1
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
2A5
VCC
2A6
2A7
2A8
GND
2APAR
2ERRA
OEAB
SEL
2CLKENAB
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
1CLKENBA
LEBA
CLKBA
1ERRB
1BPAR
GND
1B1
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
2B5
VCC
2B6
2B7
2B8
GND
2BPAR
2ERRB
OEBA
ODD/EVEN
2CLKENBA
DESCRIPTION/ORDERING INFORMATION
This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a
feed-through transceiver, or it can generate/check parity from the two 8-bit data buses in either direction.
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
PACKAGE (1)
TSSOP – DGG
Tape and reel
ORDERABLE PART NUMBER
SN74LVCH16901DGGR
TOP-SIDE MARKING
LVCH16901
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, UBT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2005, Texas Instruments Incorporated
Not Recommended For New Designs
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
www.ti.com
SCES145C – OCTOBER 1998 – REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74LVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual
9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direction of data
flow is controlled by output-enable (OEAB and OEBA) inputs. When SEL is low, the parity functions are enabled.
When SEL is high, the parity functions are disabled, and the device acts as an 18-bit registered transceiver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLES
ABC
FUNCTION (1)
INPUTS
LEAB
CLKAB
A
OUTPUT
B
H
X
X
X
Z
L
H
X
L
L
CLKENAB
OEAB
X
X
(1)
(2)
(3)
X
L
H
X
H
H
H
L
L
X
X
B0 (2)
L
L
L
↑
L
L
L
L
L
↑
H
H
L
L
L
L
X
B0 (2)
L
L
L
H
X
B0 (3)
A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA,
LEBA, and CLKENBA.
Output level before the indicated steady-state input conditions were
established
Output level before the indicated steady-state input conditions were
established, provided that CLKAB was low before LEAB went low
PARITY ENABLE
INPUTS
2
OEAB
OPERATION OR FUNCTION
SEL
OEBA
L
H
L
Parity is checked on port A and is generated on port B.
L
L
H
Parity is checked on port B and is generated on port A.
L
H
H
Parity is checked on port B and port A.
L
L
L
Parity is generated on port A and B if device is in FF mode.
H
L
L
H
L
H
H
H
L
H
H
H
QA data to B, QB data to A
Parity functions are disabled; device Q data to A
B
acts as a standard 18-bit registered
QA data to B
transceiver.
Isolation
Not Recommended For New Designs
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
www.ti.com
SCES145C – OCTOBER 1998 – REVISED JUNE 2005
FUNCTION TABLES (CONTINUED)
ABC
PARITY
INPUTS
OUTPUTS
SEL
OEBA
OEAB
ODD/EVEN
Σ OF INPUTS
A1–A8 = H
Σ OF INPUTS
B1–B8 = H
APAR
BPAR
APAR
ERRA
L
H
L
L
0, 2, 4, 6, 8
N/A
L
N/A
N/A
L
H
L
L
1, 3, 5, 7
N/A
L
N/A
N/A
L
H
L
L
0, 2, 4, 6, 8
N/A
H
N/A
N/A
L
L
Z
L
H
L
L
1, 3, 5, 7
N/A
H
N/A
N/A
H
H
Z
L
L
H
L
N/A
0, 2, 4, 6, 8
N/A
L
L
Z
N/A
H
L
L
H
L
N/A
1, 3, 5, 7
N/A
L
H
Z
N/A
L
L
L
H
L
N/A
0, 2, 4, 6, 8
N/A
H
L
Z
N/A
L
L
L
H
L
N/A
1, 3, 5, 7
N/A
H
H
Z
N/A
H
L
H
L
H
0, 2, 4, 6, 8
N/A
L
N/A
N/A
L
H
Z
L
H
L
H
1, 3, 5, 7
N/A
L
N/A
N/A
H
L
Z
L
H
L
H
0, 2, 4, 6, 8
N/A
H
N/A
N/A
H
H
Z
L
H
L
H
1, 3, 5, 7
N/A
H
N/A
N/A
L
L
Z
L
L
H
H
N/A
0, 2, 4, 6, 8
N/A
L
H
Z
N/A
L
L
L
H
H
N/A
1, 3, 5, 7
N/A
L
L
Z
N/A
H
L
L
H
H
N/A
0, 2, 4, 6, 8
N/A
H
H
Z
N/A
H
(1)
(2)
BPAR
ERRB
H
L
Z
L
H
Z
L
L
H
H
N/A
1, 3, 5, 7
N/A
H
L
Z
N/A
L
L
H
H
L
0, 2, 4, 6, 8
0, 2, 4, 6, 8
L
L
Z
H
Z
H
L
H
H
L
1, 3, 5, 7
1, 3, 5, 7
L
L
Z
L
Z
L
L
H
H
L
0, 2, 4, 6, 8
0, 2, 4, 6, 8
H
H
Z
L
Z
L
L
H
H
L
1, 3, 5, 7
1, 3, 5, 7
H
H
Z
H
Z
H
L
H
H
H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
L
L
Z
L
Z
L
L
H
H
H
1, 3, 5, 7
1, 3, 5, 7
L
L
Z
H
Z
H
L
H
H
H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
H
H
Z
H
Z
H
L
H
H
H
1, 3, 5, 7
1, 3, 5, 7
H
H
Z
L
Z
L
L
L
L
L
N/A
N/A
N/A
N/A
PE (1)
Z
PE (1)
Z
L
L
L
H
N/A
N/A
N/A
N/A
PO (2)
Z
PO (2)
Z
Parity output is set to the level so that the specific bus side is set to even parity.
Parity output is set to the level so that the specific bus side is set to odd parity.
3
Not Recommended For New Designs
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
www.ti.com
SCES145C – OCTOBER 1998 – REVISED JUNE 2005
FUNCTIONAL BLOCK DIAGRAM
LEAB
2
1CLKENAB
2CLKENAB
CLKAB
OEAB
OEBA
1A1-1A8
18-Bit
Storage
18
1APAR
A-Port
Parity
Generate
and
Check
B Data
1ERRB
2A1-2A8
2APAR
18
QB
2ERRB
18-Bit
Storage
1B1-1B8
18
QA
18
1BPAR
B-Port
Parity
Generate
and
Check
A Data
1ERRA
2B1-2B8
2BPAR
2ERRA
ODD/EVEN
SEL
CLKBA
2
1CLKENBA
2CLKENBA
LEBA
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
range (2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
4
–65
V
±50
mA
±100
mA
55
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
Not Recommended For New Designs
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
www.ti.com
SCES145C – OCTOBER 1998 – REVISED JUNE 2005
Recommended Operating Conditions
VCC
Supply voltage
(1)
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
1.5
Low-level input voltage
VI
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
VO
Output voltage
IOH
High-level output current
0.35 × VCC
0.7
VCC = 2.7 V to 3.6 V
0.8
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 1.65 V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
VCC = 2.3 V to 2.7 V
Input voltage
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
V
V
V
mA
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
5
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
Not Recommended For New Designs
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
www.ti.com
SCES145C – OCTOBER 1998 – REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
1.65 V to 3.6 V
Control
inputs
II
TYP (1)
MAX
1.2
IOH = –8 mA
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
VI = 0 to 5.5 V
1.65 V
VI = 0.7 V
2.3 V
A or B ports VI = 1.7 V
VI = 0.8 V
3V
VI = 2 V
VI = 0 to 3.6
V
3.6 V
VI = 0.58 V
V (2)
UNIT
VCC – 0.2
1.65 V
VI = 1.07 V
II(hold)
MIN
IOH = –4 mA
IOH = –12 mA
VOL
VCC
±5
V
µA
25
–25
45
µA
–45
75
–75
3.6 V
±600
Ioff
VI or VO = 5.5 V
0
±10
µA
IOZ (3)
VO = 0 to 5.5 V
3.6 V
±10
µA
VI = VCC or GND
ICC
3.6 V ≤ VI ≤ 5.5 V (4)
∆ICC
One input at VCC – 0.6 V,
Ci
Control
inputs
Cio
A or B ports VO = VCC or GND
(1)
(2)
(3)
(4)
6
VI = VCC or GND
IO = 0
Other inputs at VCC or GND
20
3.6 V
20
2.7 V to 3.6 V
500
µA
µA
3.3 V
7
pF
3.3 V
9.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current, but not II(hold).
This applies in the disabled state only.
Not Recommended For New Designs
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
www.ti.com
SCES145C – OCTOBER 1998 – REVISED JUNE 2005
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 1.8 V (1)
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time
th
(1)
MAX
Hold time
MIN
MAX
125
VCC = 2.7 V
MIN MAX
125
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX
125
125
CLK↑
4
3
3
3
LE high
3
3
3
3
A, APAR or B, BPAR before CLK↑
4.7
2.7
2.8
2.5
CLKEN before CLK↑
4.5
2.9
2.9
2.5
A, APAR or B, BPAR before LE↓
0
2.2
2.1
2
A, APAR or B, BPAR after CLK↑
0
1.2
1.2
1.3
CLKEN after CLK↑
0
1.3
1.3
1.5
A, APAR or B, BPAR after LE↓
1
1.7
1.9
1.7
MHz
ns
ns
ns
Texas Instruments SPICE simulation data
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
MIN
TYP
125
A or B
APAR or BPAR
ODD/EVEN
SEL
tpd
CLKAB or CLKBA
LEAB or LEBA
(1)
VCC = 1.8 V (1)
VCC = 2.5 V
± 0.2 V
MIN
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
125
MIN
MAX
125
MIN
UNIT
MAX
125
MHz
B or A
5.9
1
6.2
5.8
1
5.4
BPAR or APAR
12.7
2
9.9
8.6
2
7.7
BPAR or APAR
7
1
6.7
6.2
1
5.7
ERRA or ERRB
13
2
10.7
9.7
2
8.5
ERRA or ERRB
9.9
1.5
9.7
8.9
1.5
7.8
BPAR or APAR
10.4
1.5
9.3
8.6
1.5
7.5
BPAR or APAR
6.9
1
7.1
6.9
1
6.1
A or B
6.9
1
7.4
6.8
1
6.1
BPAR or APAR
parity feedthrough
8.5
1.5
8.1
7.3
1.5
6.6
BPAR or APAR
parity generated
14.1
2.5
11.2
9.7
2
8.7
ERRA or ERRB
14.3
2.5
11.5
9.9
2
8.9
A or B
6.8
1
7
6.5
1
5.8
BPAR or APAR
parity feedthrough
7.9
1.5
7.7
7
1.5
6.3
BPAR or APAR
parity generated
13.6
2.5
10.8
9.3
2
8.4
ns
ERRA or ERRB
13.5
2.5
10.9
9.5
2
8.5
ten
OEAB or OEBA
B, BPAR or A, APAR
6.8
1.4
7.3
7.1
1
6.3
ns
tdis
OEAB or OEBA
B, BPAR or A, APAR
6.9
1.3
7.1
6.2
1.5
5.9
ns
ten
OEAB or OEBA
ERRA or ERRB
7.4
1.4
7.2
6.5
1
5.9
ns
tdis
OEAB or OEBA
ERRA or ERRB
9.3
1.3
8.3
7.5
1
6.7
ns
ten
SEL
ERRA or ERRB
7.6
1.4
7.7
7.5
1
6.5
ns
tdis
SEL
ERRA or ERRB
7.8
1.3
7.4
6.4
1.5
5.9
ns
Texas Instruments SPICE simulation data
7
Not Recommended For New Designs
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
www.ti.com
SCES145C – OCTOBER 1998 – REVISED JUNE 2005
Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
8
Power dissipation capacitance
per transceiver
Outputs enabled
Outputs disabled
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
37
52
68
16
22
28
UNIT
pF
Not Recommended For New Designs
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
www.ti.com
SCES145C – OCTOBER 1998 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74LVCH16901DGGRE4
NRND
TSSOP
DGG
64
TBD
Call TI
Call TI
-40 to 85
74LVCH16901DGGRG4
NRND
TSSOP
DGG
64
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
Addendum-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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湘ICP备2023018690号
