ADC08D1000CIYB

National Semiconductor is now part of Texas Instruments. Search http://www.ti.com/ for the latest technical information and details on our current products and services. ADC08D1000 High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter General Description Features The ADC08D1000 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.3 GSPS. Consuming a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.4 ENOB with a 500 MHz input signal and a 1 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 2 GSPS ADC. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range. ■ ■ ■ ■ ■ ■ ■ ■ ■ Internal Sample-and-Hold Single +1.9V ±0.1V Operation Choice of SDR or DDR output clocking Interleave Mode for 2x Sampling Rate Multiple ADC Synchronization Capability Guaranteed No Missing Codes Serial Interface for Extended Control Fine Adjustment of Input Full-Scale Range and Offset Duty Cycle Corrected Sample Clock Key Specifications ■ ■ ■ ■ ■ ■ ■ Resolution Max Conversion Rate Bit Error Rate ENOB @ 500 MHz Input DNL Power Consumption — Operating — Power Down Mode 8 Bits 1 GSPS (min) 10-18 (typ) 7.4 Bits (typ) ±0.15 LSB (typ) 1.6 W (typ) 3.5 mW (typ) Applications ■ ■ ■ ■ ■ Direct RF Down Conversion Digital Oscilloscopes Satellite Set-top boxes Communications Systems Test Instrumentation Block Diagram 20097453 © 2009 National Semiconductor Corporation 200974 www.national.com ADC08D1000 High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter April 16, 2009 ADC08D1000 Ordering Information Industrial Temperature Range (-40°C < TA < +85°C) NS Package ADC08D1000CIYB 128-Pin Exposed Pad LQFP ADC08D1000DEV Development Board Pin Configuration 20097401 * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. www.national.com 2 ADC08D1000 Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description OutV / SCLK Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See1.1.6 The LVDS Outputs. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See 1.2 NORMAL/EXTENDED CONTROL for details on the extended control mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. 4 OutEdge / DDR / SDATA DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. (See 1.1.5.2 OutEdge Setting). When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the extended control mode is enabled, this pin functions as the SDATA input. See 1.2 NORMAL/EXTENDED CONTROL for details on the extended control mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. 15 DCLK_RST/ DCLK_RST-   26   PD Power Down Pins. A logic high on the PD pin puts the entire device into the Power Down Mode. 30 CAL Calibration Cycle Initiate. A minimum tCAL_L input clock cycles logic low followed by a minimum of tCAL_H input clock cycles high on this pin initiates the self calibration sequence. See 2.4.2 Self Calibration for an overview of self-calibration and 2.4.2.2 OnCommand Calibration for a description of on-command calibration. 29   PDQ A logic high on the PDQ pin puts only the "Q" ADC into the Power Down mode. FSR/ECE Full Scale Range Select and Extended Control Enable. In nonextended control mode, a logic low on this pin sets the full-scale differential input range to a reduced VIN input level . A logic high on this pin sets the full-scale differential input range to a higher VIN input level. See Converter Electrical Characteristics. To enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See 1.2 NORMAL/EXTENDED CONTROL for information on the extended control mode. 3 14 DCLK Reset. A positive pulse on this pin is used to reset and synchronize the DCLK outs of multiple converters. See 1.5 MULTIPLE ADC SYNCHRONIZATION for detailed description. 3 www.national.com ADC08D1000 Pin Functions Pin No. Symbol Equivalent Circuit Description CalDly / DES / SCS Calibration Delay, Dual Edge Sampling and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of input clock cycles after power up before calibration begins (See 1.1.1 Self-Calibration). With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay). When this pin is floating or connected to a voltage equal to VA/2, DES (Dual Edge Sampling) mode is selected where the "I" input is sampled at twice the input clock rate and the "Q" input is ignored. See 1.1.5.1 DualEdge Sampling. 18 19 CLK+ CLK- LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See 1.1.2 Acquiring the Input for a description of acquiring the input and Section 2.3 for an overview of the clock inputs. 11 10   22 23 VINI+ VINI− 127   VINQ+ VINQ− 7 VCMO   31   VBG 126 CalRun www.national.com Analog signal inputs to the ADC. The differential full-scale input range of this input is programmable using the FSR pin 14 in normal mode and the Input Full-Scale Voltage Adjust register in the extended control mode. Refer to the VIN specification in the Converter Electrical Characteristics for the full-scale input range in the normal mode. Refer to 1.4 REGISTER DESCRIPTION for the full-scale input range in the extended control mode. Common Mode Voltage. The voltage output at this pin is required to be the common mode input voltage at VIN+ and VIN− when d.c. coupling is used. This pin should be grounded when a.c. coupling is used at the analog inputs. This pin is capable of sourcing or sinking 100μA. See 2.2 THE ANALOG INPUT. Bandgap output voltage capable of 100 μA source/sink. Calibration Running indication. This pin is at a logic high when calibration is running. 4 ADC08D1000 Pin Functions Pin No. Symbol 32 REXT External bias resistor connection. Nominal value is 3.3k-Ohms (±0.1%) to ground. See Section 1.1.1. Tdiode_P Tdiode_N Temperature Diode Positive (Anode) and Negative (Cathode). These pins may be used for die temperature measurements, however no specified accuracy is implied or guaranteed. Noise coupling from adjacent output data signals has been shown to affect temperature measurements using this feature. See 2.6.2 Thermal Management. 34 35 Equivalent Circuit Description 5 www.national.com ADC08D1000 Pin Functions Pin No. Symbol 83 / 78 84 / 77 85 / 76 86 / 75 89 / 72 90 / 71 91 / 70 92 / 69 93 / 68 94 / 67 95 / 66 96 / 65 100 / 61 101 / 60 102 / 59 103 / 58 DI7− / DQ7− DI7+ / DQ7+ DI6− / DQ6− DI6+ / DQ6+ DI5− / DQ5− DI5+ / DQ5+ DI4− / DQ4− DI4+ / DQ4+ DI3− / DQ3− DI3+ / DQ3+ DI2− / DQ2− DI2+ / DQ2+ DI1− / DQ1− DI1+ / DQ1+ DI0− / DQ0− DI0+ / DQ0+ 104 / 57 105 / 56 106 / 55 107 / 54 111 / 50 112 / 49 113 / 48 114 / 47 115 / 46 116 / 45 117 / 44 118 / 43 122 / 39 123 / 38 124 / 37 125 / 36 DId7− / DQd7− DId7+ / DQd7+ DId6− / DQd6− DId6+ / DQd6+ DId5− / DQd5− DId5+ / DQd5+ DId4− / DQd4− DId4+ / DQd4+ DId3− / DQd3− DId3+ / DQd3+ DId2− / DQd2− DId2+ / DQd2+ DId1− / DQd1− DId1+ / DQd1+ DId0− / DQd0− DId0+ / DQd0+ I and Q channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI/DQ outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100Ω differential resistor. OR+ OR- Out Of Range output. A differential high at these pins indicates that the differential input is out of range (outside the range ±VIN/2 as programmed by the FSR pin in non-extended control mode or the Input Full-Scale Voltage Adjust register setting in the extended control mode). 82 81 DCLK+ DCLK- Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. This signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. The DCLK outputs are not active during a calibration cycle, therefore this is not recommended as a system clock. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 VA Analog power supply pins. Bypass these pins to ground. 40, 51 ,62, 73, 88, 99, 110, 121 VDR Output Driver power supply pins. Bypass these pins to DR GND. 1, 6, 9, 12, 21, 24, 27, 41 GND Ground return for VA. 79 80 www.national.com Equivalent Circuit Description I and Q channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor. 6 ADC08D1000 Pin Functions Pin No. Symbol 42, 53, 64, 74, 87, 97, 108, 119 DR GND 52, 63, 98, 109, 120 NC Equivalent Circuit Description Ground return for VDR. No Connection. Make no connection to these pins. 7 www.national.com ADC08D1000 Operating Ratings Absolute Maximum Ratings (Notes 1, 2) −40°C ≤ TA ≤ +85°C (Notes 1, 2) Ambient Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA) Driver Supply Voltage (VDR) Analog Input Common Mode Voltage VIN+, VIN- Voltage Range (Maintaining Common Mode) Supply Voltage (VA, VDR) Supply Difference VDR - VA Voltage on Any Input Pin (Except VIN+, VIN- ) Voltage on VIN+, VIN(Maintaining Common Mode) Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) 2.2V +1.8V to +2.0V +1.8V to VA VCMO ±50mV 0V to 2.15V (100% duty cycle) 0V to 2.5V (10% duty cycle) 0V to 100 mV Ground Difference (|GND - DR GND|) CLK Pins Voltage Range Differential CLK Amplitude −0.15V to (VA +0.15V) -0.15V to 2.5V 0V to 100 mV ±25 mA ±50 mA Power Dissipation at TA ≤ 85°C ESD Susceptibility (Note 4) Human Body Model Machine Model Soldering Temperature, Infrared, 10 seconds, (Note 5), (Applies to standard plated package only) Storage Temperature 0V 0V to VA 0.4VP-P to 2.0VP-P Package Thermal Resistance Package 2.0 W 128-Lead Exposed Pad LQFP   2500V 250V θJA 25°C / W θJC(Top of θJ-PAD Package) (Thermal Pad) 10°C / W 2.8°C / W Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. 235°C −65°C to +150°C Converter Electrical Characteristics The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Notes 6, 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) STATIC CONVERTER CHARACTERISTICS INL Integral Non-Linearity (Best fit) DC Coupled, 1MHz Sine Wave Over ranged ±0.3 ±0.9 LSB (max) DNL Differential Non-Linearity DC Coupled, 1MHz Sine Wave Over ranged ±0.15 ±0.6 LSB (max) 8 Bits −1.5 0.5 LSB (min) LSB (max) Resolution with No Missing Codes VOFF Offset Error VOFF_ADJ Input Offset Adjustment Range PFSE Positive Full-Scale Error (Note 9) −0.6 ±25 mV (max) NFSE Negative Full-Scale Error (Note 9) −1.31 ±25 mV (max) FS_ADJ Full-Scale Adjustment Range ±20 ±15 %FS -0.45 Extended Control Mode Extended Control Mode ±45 mV NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS FPBW B.E.R. Full Power Bandwidth 1.7 GHz 10-18 Error/Sample d.c. to 500 MHz ±0.5 dBFS d.c. to 1 GHz ±1.0 dBFS fIN = 100 MHz, VIN = FSR − 0.5 dB 7.5 fIN = 248 MHz, VIN = FSR − 0.5 dB 7.4 7.0 Bits (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 7.4 7.0 Bits (min) Bit Error Rate Gain Flatness ENOB Normal Mode (non DES) Effective Number of Bits www.national.com 8 Bits SINAD SNR THD 2nd Harm 3rd Harm SFDR IMD Parameter Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious-Free dynamic Range Intermodulation Distortion Out of Range Output Code (In addition to OR Output high) Conditions Typical (Note 8) Limits (Note 8) Units (Limits) fIN = 100 MHz, VIN = FSR − 0.5 dB 47 fIN = 248 MHz, VIN = FSR − 0.5 dB 46.3 43.9 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 46.3 43.9 dB (min) dB fIN = 100 MHz, VIN = FSR − 0.5 dB 48 fIN = 248 MHz, VIN = FSR − 0.5 dB 47.1 44.0 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 47.1 44.0 dB (min) fIN = 100 MHz, VIN = FSR − 0.5 dB -55 fIN = 248 MHz, VIN = FSR − 0.5 dB -55 -47.5 dB (max) fIN = 498 MHz, VIN = FSR − 0.5 dB -55 -47.5 dB (max) fIN = 100 MHz, VIN = FSR − 0.5 dB −60 dB fIN = 248 MHz, VIN = FSR − 0.5 dB −60 dB fIN = 498 MHz, VIN = FSR − 0.5 dB −60 dB fIN = 100 MHz, VIN = FSR − 0.5 dB −65 dB fIN = 248 MHz, VIN = FSR − 0.5 dB −65 dB fIN = 498 MHz, VIN = FSR − 0.5 dB −65 dB fIN = 100 MHz, VIN = FSR − 0.5 dB 55 fIN = 248 MHz, VIN = FSR − 0.5 dB 55 47.5 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 55 47.5 dB (min) fIN1 = 321 MHz, VIN = FSR − 7 dB fIN2 = 326 MHz, VIN = FSR − 7 dB -50 dB dB dB dB (VIN+) − (VIN−) > + Full Scale 255 (VIN+) − (VIN−) < − Full Scale 0 INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS FPBW (DES) Full Power Bandwidth ENOB Effective Number of Bits SINAD Signal to Noise Plus Distortion Ratio SNR Signal to Noise Ratio THD 2nd Harm Total Harmonic Distortion Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious Free Dynamic Range Dual Edge Sampling Mode 900 MHz fIN = 248 MHz, VIN = FSR − 0.5 dB 7.3 6.8 Bits (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 7.3 6.8 Bits (min) fIN = 248 MHz, VIN = FSR − 0.5 dB 46 42.5 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 46 42.5 dB (min) fIN = 248 MHz, VIN = FSR − 0.5 dB 46.4 43 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 46.4 43 dB (min) fIN = 248 MHz, VIN = FSR − 0.5 dB -58 -49 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB -58 -49 dB (min) fIN = 248 MHz, VIN = FSR − 0.5 dB -64 dB fIN = 498 MHz, VIN = FSR − 0.5 dB -64 dB fIN = 248 MHz, VIN = FSR − 0.5 dB -69 dB fIN = 498 MHz, VIN = FSR − 0.5 dB -69 dB fIN = 248 MHz, VIN = FSR − 0.5 dB 57 47 dB (min) fIN = 498 MHz, VIN = FSR − 0.5 dB 57 47 dB (min) ANALOG INPUT AND REFERENCE CHARACTERISTICS VIN VCMI FSR pin 14 Low 650 FSR pin 14 High 870 Full Scale Analog Differential Input Range Analog Input Common Mode Voltage VCMO 9 570 mVP-P (min) 730 mVP-P (max) 790 mVP-P (min) 950 mVP-P (max) VCMO − 50 VCMO + 50 mV (min) mV (max) www.national.com ADC08D1000 Symbol ADC08D1000 Symbol CIN RIN Parameter Conditions Differential Analog Input Capacitance, Normal operation (Notes 10, 11) Each input pin to ground Analog Input Capacitance, DES Mode (Notes 10, 11) Typical (Note 8) Limits (Note 8) Units (Limits) 0.02 pF 1.6 pF Differential 0.08 pF Each input pin to ground 2.2 pF Differential Input Resistance 100 94 Ω (min) 106 Ω (max) 0.95 1.45 V (min) V (max) ANALOG OUTPUT CHARACTERISTICS VCMO Common Mode Output Voltage ICMO = ±100 µA 1.26 VCMO_LVL VCMO input threshold to set DC Coupling mode VA = 1.8V 0.60 V VA = 2.0V 0.66 V TC VCMO Common Mode Output Voltage Temperature Coefficient TA = −40°C to +85°C 118 ppm/°C CLOAD VCMO Maximum VCMO load Capacitance VBG Bandgap Reference Output Voltage IBG = ±100 µA TC VBG Bandgap Reference Voltage Temperature Coefficient TA = −40°C to +85°C, IBG = ±100 µA CLOAD VBG Maximum Bandgap Reference load Capacitance 1.26 80 pF 1.20 1.33 V (min) V (max) 28 ppm/°C 80 pF TEMPERATURE DIODE CHARACTERISTICS ΔVBE Temperature Diode Voltage 192 µA vs. 12 µA, TJ = 25°C 71.23 mV 192 µA vs. 12 µA, TJ = 85°C 85.54 mV 1 LSB 1 LSB CHANNEL-TO-CHANNEL CHARACTERISTICS Offset Match Positive Full-Scale Match Zero offset selected in Control Register Negative Full-Scale Match Zero offset selected in Control Register Phase Matching (I, Q) FIN = 1.0 GHz 1 LSB