ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
ADC10DV200 Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS
Outputs
Check for Samples: ADC10DV200
FEATURES
DESCRIPTION
•
•
•
•
•
•
The ADC10DV200 is a monolithic analog-to-digital
converter capable of converting two analog input
signals into 10-bit digital words at rates up to 200
Mega Samples Per Second (MSPS). The digital
output mode is selectable and can be either
differential LVDS or CMOS signals. This converter
uses a differential, pipelined architecture with digital
error correction and an on-chip sample-and-hold
circuit to minimize die size and power consumption
while providing excellent dynamic performance. A
unique sample-and-hold stage yields a full-power
bandwidth of 900MHz. Fabricated in core CMOS
process, the ADC10DV200 may be operated from a
single 1.8V power supply. The ADC10DV200
achieves approximately 9.6 effective bits at Nyquist
and consumes just 280mW at 170MSPS in CMOS
mode and 450mW at 200MSPS in LVDS mode. The
power consumption can be scaled down further by
reducing sampling rates.
1
2
•
•
•
•
Single 1.8V Power Supply Operation.
Power Scaling with Clock Frequency.
Internal Sample-and-Hold.
Internal or External Reference.
Power Down Mode.
Offset Binary or 2's Complement Output Data
Format.
LVDS or CMOS Output Signals.
60-pin WQFN Package, (9x9x0.8mm, 0.5mm
Pin-Pitch)
Clock Duty Cycle Stabilizer.
IF Sampling Bandwidth > 900MHz.
KEY SPECIFICATIONS
•
•
•
•
•
•
•
•
•
Resolution 10 Bits
Conversion Rate 200 MSPS
ENOB 9.6 bits (typ) @Fin=70 MHz
SNR 59.9 dBFS (typ) @Fin=70 MHz
SINAD 59.9 dBFS (typ) @Fin=70 MHz
SFDR 82 dBFS (typ) @Fin=70 MHz
LVDS Power 450mW (typ) @Fs=200 MSPS
CMOS Power 280mW (typ) @Fs=170 MSPS
Operating Temp. Range −40°C to +85°C.
APPLICATIONS
•
•
•
•
Communications
Medical Imaging
Portable Instrumentation
Digital Video
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
Block Diagram
VIN A+
S/H
VIN A-
CLK+
CLK-
10 Bit 200 MSPS
Pipeline Converter
Timing
Control
10
DCS
Digital Error
Correction
VRPA
VRMA
VRNA
Output
Clock
Reference
VREF
Output
Formatter
Output Buffer
(CMOS/LVDS)
Data Out
DRDY
OR
VRPB
VRMB
VRNB
Digital Error
Correction
10
10 Bit 200 MSPS
Pipeline Converter
VIN B+
VIN B-
S/H
AGND
VIN BVIN B+
AGND
VRM B
VRP B
DRGND
DB6/D8 +
46
DB7/D8 47
DB8/D9 +
48
49
DB9/D9 -
ORA/OR +
50
ORB/OR 51
PDB
52
53
VD
AGND
54
55
CLK -
CLK +
56
AGND
57
VA
58
59
60
VA
Connection Diagram
1
45
2
44
3
43
4
42
5
41
7
DB1/D5 DB0/D5 +
9
37
10
36
11
35
DRDYB/DRDY -
PDA
12
* Exposed pad must be soldered to ground
34
plane to ensure rated performance.
33
13
VIN A-
38
DRDYA/DRDY +
AGND
VIN A+
DA9/D4 DA8/D4 +
DA7/D3 -
14
32
15
31
DA6/D3 +
VDR
Submit Documentation Feedback
DRGND
30
29
DA5/D2 -
28
DA3/D1-
DA4/D2 +
27
26
DA2/D1 +
25
DA1/D0 -
24
DA0/D0 +
23
AGND
OUTSEL
21
22
VD
19
20
DF/DCS
REXT
18
VA
VREF
17
VA
16
AGND
2
DB3/D6 -
39
VA
VRP A
DB4/D7 +
40
ADC10DV200
60 LEAD WQFN
(TOP VIEW)
8
VRM A
DB5/D7 -
DB2/D6 +
6
VRN B
VRN A
VDR
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
13
3
VINA+
VINB+
14
2
VINAVINB-
10
6
VRPA
VRPB
11
5
VRMA
VRMB
VA
Differential analog input pins. The differential full-scale input
signal level is 1.5VP-P with each input pin signal centered on a
common mode voltage, VCM.
AGND
VA
VA
VA
9
7
VRNA
VRNB
VA
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very
close to the pin to minimize stray inductance. An 0201 size 0.1
µF capacitor should be placed between VRP and VRN as close
to the pins as possible.
VRP and VRN should not be loaded. VRM may be loaded to 1mA
for use as a temperature stable 0.9V reference.
It is recommended to use VRM to provide the common mode
voltage, VCM for the differential analog inputs.
AGND
AGND
Reference Voltage select pin and external reference input. The
relationship between the voltage on the pin and the reference
voltage is as follows:
VA
17
1.4V ≤ VREF ≤ VA
The internal 0.75V reference is
used.
0.2V ≤ VREF ≤ 1.4V
The external reference voltage is
used.
Note: When using an external
reference, be sure to bypass with
a 0.1µF capacitor to AGND as
close to the pin as possible.
AGND ≤ VREF ≤ 0.2V
The internal 0.5V reference is
used.
VREF
AGND
VA
19
Ibias
Programming resistor for analog bias current. Nominally a
3.3kΩ to AGND for 200MSPS, or tie to VA to use the internal
frequency scaling current.
REXT
AGND
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
3
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
Pin Descriptions and Equivalent Circuits (continued)
Pin No.
Symbol
Equivalent Circuit
Description
VA
20
Data Format/Duty Cycle Correction selection pin.
(see Table 1)
DF/DCS
AGND
DIGITAL I/O
Clock input pins signal. The analog inputs are sampled on the
rising edge of this signal. The clock can be configured for
single-ended mode by shorting the CLK- pin to AGND. When in
differential mode, the common mode voltage for the clock is
internally set to 1.2V.
VA
57
56
CLK +
CLK -
AGND
36
53
PD_A
PD_B
Two-state input controlling Power Down.
PD = VA, Power Down is enabled and power dissipation is
reduced.
PD = AGND, Normal operation.
VA
Two-state input controlling Output Mode.
OUTSEL = VD, LVDS Output Mode.
OUTSEL = AGND, CMOS Output Mode.
23
OUTSEL
AGND
LVDS Output Mode
24, 25
26, 27
28, 29
32, 33
34, 35
39, 40
41, 42
43, 44
47, 48
49, 50
D0+,D0D1+, D1D2+, D2D3+, D3D4+, D4D5+, D5D6+, D6D7+, D7D8+, D8D9+, D9-
37
38
DRDY+
DRDY-
51
52
OR+
OR-
LVDS Output pairs for bits 0 through 9. A-channel and Bchannel digital LVDS outputs are interleaved. A channel is
ready at rising edge of DRDY and B channel is ready at the
falling edge of DRDY.
VDR
-
+
+
-
4
+
-
DRGND
Data Ready Strobe. This signal is a LVDS DDR clock used to
capture the output data. A-channel data is valid on the rising
edge of this signal and B-channel data is valid on the falling
edge.
ADC over-range Signal. This signals timing is formatted
similarly to the data output signals. A channel is valid on DRDY
rising and B channel is valid on DRDY falling. This signal will go
high when the respective channel exceeds the allowable range
of the ADC. Nominally this signal will be low.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Pin Descriptions and Equivalent Circuits (continued)
Pin No.
Symbol
Equivalent Circuit
Description
CMOS Output Mode
24-29,
32-35
Digital data output pins that make up the 10-bit conversion
result for Channel A. DA0 (pin 24) is the LSB, while DA9 (pin
35) is the MSB of the output word. Output levels are CMOS
compatible.
DA0-DA9
VDR
VA
39-44,
47-50
DB0-DB9
Digital data output pins that make up the 10-bit conversion
result for Channel B. DB0 (pin 39) is the LSB, while DB9 (pin
50) is the MSB of the output word. Output levels are CMOS
compatible.
37
DRDYA
Data Ready Strobe for channel A. This signal is used to clock
the A-Channel output data. DRDYA is a SDR clock with same
frequency as CLK rate and data is valid on the rising edges.
38
DRDYB
Data Ready Strobe for channel B. This signal is used to clock
the B-Channel output data. DRDYB is a SDR clock with same
frequency as CLK rate and data is valid on the rising edges.
51
ORA
52
ORB
DRGND
DRGND
Overrange indicator for channel A. A high on this pin indicates
that the input exceeded the allowable range for the converter.
Overrange indicator for channel B. A high on this pin indicates
that the input exceeded the allowable range for the converter.
ANALOG POWER
Positive analog supply pins. These pins should be connected to
a quiet source and be bypassed to AGND with 0.1 µF
capacitors located close to the power pins.
8, 16, 18, 59,
60
VA
1, 4, 12, 15,
22, 55, 58, EP
AGND
The ground return for the analog supply.
Exposed pad must be soldered to AGND to ensure rated
performance.
DIGITAL POWER
21, 54
VD
Positive digital supply pins. These pins should be connected to
a quiet source and be bypassed to AGND with 0.1 µF
capacitors located close to the power pins.
31, 45
VDR
Positive driver supply pin for the output drivers. This pin should
be connected to a quiet voltage source and be bypassed to
DRGND with a 0.1 µF capacitor located close to the power pin.
30, 46
DRGND
The ground return for the digital output driver supply. This pin
should be connected to the system digital ground.
Table 1. Voltage on DF/DCS Pin and Corresponding Chip Response
Voltage on DF/DCS
Min
Results
Max
DF
DCS
Suggestions
0 mV
200mV
1
1
2's complement data, duty cycle correction on
Tie to AGND
250 mV
600 mV
0
0
Offset binary data, duty cycle correction off
Leave floating
750 mV
1250 mV
1
0
2's complement data, duty cycle correction off
1400mV
VA
0
1
Offset binary data, duty cycle correction on
Tie to VA
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
5
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Absolute Maximum Ratings
www.ti.com
(1) (2) (3)
−0.3V to 2.2V
Supply Voltage (VA, VD VDR)
−0.3V to (VA +0.3V)
Voltage on Any Pin
(Not to exceed 2.2V)
Input Current at Any Pin other than Supply Pins
Package Input Current
(4)
±25 mA
(4)
±50 mA
Max Junction Temp (TJ)
+150°C
Thermal Resistance (θJA)
30°C/W
ESD Rating
(5)
Human Body Model
2500V
Machine Model
250V
Human Body Model
750V
−65°C to +150°C
Storage Temperature
Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. (6)
(1)
(2)
(3)
(4)
(5)
(6)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the
maximum Operating Ratings is not recommended.
All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of ±5 mA to 10.
Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0Ω resistor. Charged
device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then
rapidly being discharged.
Reflow temperature profiles are different for lead-free and non-lead-free packages.
Operating Ratings
(1) (2)
−40°C ≤ TA ≤ +85°C
Operating Temperature
Supply Voltage (VA, VD, VDR)
Clock Duty Cycle
+1.7V to +1.9V
(DCS Enabled)
(DCS disabled)
VCM
(1)
(2)
6
30/70 %
48/52 %
0.8V to 1.0V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the
maximum Operating Ratings is not recommended.
All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface
limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C (1) (2)
Symbol
Parameter
Conditions
Typical
(3)
Limits
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
10
Bits (min)
INL
Resolution with No Missing Codes
Integral Non Linearity
±300
±920
mLSB (max)
DNL
Differential Non Linearity
±170
±430
mLSB (max)
PGE
Positive Gain Error
0.57
3.11
%FS (max)
NGE
Negative Gain Error
0.60
2.72
%FS (max)
TC PGE
Positive Gain Error Tempco
−40°C ≤ TA ≤ +85°C
13
ppm/°C
TC NGE
Negative Gain Error Tempco
−40°C ≤ TA ≤ +85°C
15
ppm/°C
VOFF
TC VOFF
Offset Error
Offset Error Tempco
0.1
−40°C ≤ TA ≤ +85°C
+0.75
-0.75
4
%FS (max)
ppm/°C
Under Range Output Code
0
0
Over Range Output Code
1023
1023
0.9
1
0.85
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VRM
Common Mode Output Voltage
VCM
Analog Input Common Mode Voltage
0.9
V
1
pF
CIN
VIN Input Capacitance (each pin to
AGND) (4)
2.5
pF
VRP
Internal Reference Top
1.33
V
VRN
Internal Reference Bottom
0.55
V
Internal Reference Accuracy
EXT
VREF
(1)
VIN
V
= 0.75 Vdc ± 0.5 (CLK LOW)
(CLK HIGH)
V (min)
V (max)
(VRP-VRN)
0.78
V
0.5
1.0
External Reference Voltage
V (Min)
V (max)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 3 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above VA or below AGND.
VA
I/O
To Internal Circuitry
AGND
(2)
(3)
(4)
With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
7
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
Dynamic Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface
limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C (1) (2)
Symbol
Parameter
Typical
Conditions
(3)
Limits
Units
(Limits)
(4)
DYNAMIC CONVERTER CHARACTERISTICS, AIN= -1dBFS
FPBW
Full Power Bandwidth
(5)
(6)
SNR
Signal-to-Noise Ratio
SFDR
Spurious Free Dynamic Range
ENOB
Effective Number of Bits
(7)
H2
Second Harmonic Distortion
H3
Third Harmonic Distortion
SINAD
Signal-to-Noise and Distortion Ratio
IMD
Intermodulation Distortion
Cross Talk
(1)
(5)
(5)
(8)
-1 dBFS Input, −3 dB Corner
900
MHz
fIN = 10 MHz
59.9
dBFS
fIN = 70 MHz
59.9
fIN = 10 MHz
82
fIN = 70 MHz
82
fIN = 10 MHz
9.65
fIN = 70 MHz
9.65
fIN = 10 MHz
-94
fIN = 70 MHz
-94
fIN = 10 MHz
-85
fIN = 70 MHz
-84
fIN = 10 MHz
59.8
fIN = 70 MHz
59.8
fIN1 = 69 MHz AIN1 = -7 dBFS
fIN2 = 70 MHz AIN2 = -7 dBFS
fIN1 = 69 MHz AIN1 = -1 dBFS
fIN2 = 70MHz AIN2 = -1 dBFS
59
dBFS (min)
70
dBFS (min)
dBFS
Bits
9.48
Bits (min)
-70
dBFS (min)
-70
dBFS (min)
58.9
dBFS (min)
dBFS
dBFS
dBFS
93
dBFS
97
dBFS
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above VA or below AGND.
VA
I/O
To Internal Circuitry
AGND
(2)
(3)
(4)
(5)
(6)
(7)
(8)
8
With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
Units of dBFS indicates the value that would be attained with a full-scale input signal.
This parameter is specified by design and/or characterization and is not tested in production.
SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dBFS lower.
SFDR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 2dBFS lower.
SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.1dBFS lower.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface
limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2)
Symbol
Parameter
Conditions
Typical
(3)
Limits
Units
(Limits)
LVDS OUTPUT MODE
IA
Analog Supply Current
ID
Digital Supply Current
IDR
Output Driver Supply Current
Power Consumption
Power Down Power Consumption
CMOS OUTPUT MODE
160
Full Operation, External 3.3kΩ Bias
148
184
mA (max)
Full Operation
36
43
mA (max)
64
80
mA (max)
524
mW (max)
Internal Bias
473
External 3.3kΩ Bias
450
PDA=PDB=VA
57
Full Operation, Internal Bias
138
Full Operation, External 3.3kΩ Bias
124
mA
mW
mW
(4)
IA
Analog Supply Current
ID
Digital Supply Current
Power Consumption
Power Down Power Consumption
(1)
Full Operation, Internal Bias
Full Operation
31
Internal Bias
310
External 3.3kΩ Bias
280
PDA=PDB=VA
60
mA
mA
mW
mW
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above VA or below AGND.
VA
I/O
To Internal Circuitry
AGND
(2)
(3)
(4)
With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
CMOS Specifications are for FCLK = 170 MHz.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
9
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
Input/Output Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Boldface limits apply
for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2)
Symbol
Parameter
Conditions
Typical
(3)
Limits
Units
(Limits)
DIGITAL INPUT CHARACTERISTICS (PD_A,PD_B,OUTSEL)
Logical “1” Input Voltage
(4)
VA = 1.9V
0.89
V (min)
VIN(0)
Logical “0” Input Voltage
(4)
VA = 1.7V
0.67
V (max)
IIN(1)
Logical “1” Input Current
VIN = 1.8V
10.6
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
-7.6
µA
CIN
Digital Input Capacitance
2
pF
330
mVP-P
VIN(1)
LVDS OUTPUT CHARACTERISTICS (D0-D9,DRDY,OR)
VOD
LVDS differential output voltage
±VOD
Output Differential Voltage
Unbalance
See
(4)
0
VOS
LVDS common-mode output voltage See
±VOS
Offset Voltage Unbalance
RL
Intended Load Resistance
(4)
50
1.25
V
50
CMOS OUTPUT CHARACTERISTICS (DA0-DA9,DB0-DB9,DRDY,OR)
mV
mV
100
Ω
1.8
V
(5)
VOH
Logical "1" Output Voltage
VDR = 1.8V (Unloaded)
VOL
Logical "0" Output Voltage
VDR = 1.8V (Unloaded)
0
V
+IOSC
Output Short Circuit Source Current
VOUT = 0V
-20
mA
-IOSC
Output Short Circuit Sink Current
VOUT = VDR
20
mA
COUT
Digital Output Capacitance
2
pF
(1)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above VA or below AGND.
VA
I/O
To Internal Circuitry
AGND
(2)
(3)
(4)
(5)
10
With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
This parameter is specified by design and/or characterization and is not tested in production.
CMOS Specifications are for FCLK = 170 MHz.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Timing measurements
are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1)
(2)
Symbol
Parameter
Conditions
Typical
(3)
Limits
Units
(Limits)
200
MHz (max)
LVDS OUTPUT MODE
Maximum Clock Frequency
Minimum Clock Frequency
DCS On
DCS Off
65
45
MHz (min)
tCH
Clock High Time
DCS On
DCS Off
1.5
2.4
ns (min)
tCL
Clock Low Time
DCS On
DCS Off
1.5
2.4
ns (min)
tCONV
Conversion Latency
5/5.5
(A/B)
Clock Cycles
tODA
Output Delay of CLK to A-Channel Data
Relative to rising edge of CLK
2.7
1.46
ns (min)
tODB
Output Delay of CLK to B-Channel Data
Relative to falling edge of CLK
2.7
1.46
ns (min)
tSU
Data Output Setup Time
Relative to DRDY
1.2
0.7
ns (min)
tH
Data Output Hold Time
Relative to DRDY
1.2
0.7
ns (min)
tAD
Aperture Delay
0.7
ns
tAJ
Aperture Jitter
0.3
ps rms
tSKEW
Data-Data Skew
20
CMOS OUTPUT MODE
470
ps
170
MHz
(4) (5)
Maximum Clock Frequency
Minimum Clock Frequency
DCS On
DCS Off
65
25
MHz
Clock High Time
DCS On
DCS Off
1.76
2.82
ns
DCS On
DCS Off
1.76
2.82
ns
Conversion Latency
5.5
Clock Cycles
tOD
Output Delay of CLK to DATA
Relative to falling edge of CLK
4.5
3.15
5.81
ns (min)
ns (max)
tSU
Data Output Setup Time (5)
Relative to DRDY
2.5
1.79
ns (min)
tH
Data Output Hold Time (5)
Relative to DRDY
3.4
2.69
ns (min)
tAD
Aperture Delay
0.7
ns
tAJ
Aperture Jitter
0.3
ps rms
tCH
tCL
tCONV
(1)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes
above VA or below AGND.
VA
I/O
To Internal Circuitry
AGND
(2)
(3)
(4)
(5)
With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
CMOS Specifications are for FCLK = 170 MHz.
This parameter is specified by design and/or characterization and is not tested in production.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
11
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
Specification Definitions
APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output. The amount of SNR reduction can be calculated as
SNR Reduction = 20 x log10[½ x π x ƒA x tj]
(1)
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the
total time of one period. The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both input terminals of the ADC.
CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is
presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay
plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the
conversion by the pipeline delay.
CROSSTALK is coupling of energy from one channel into the other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Negative Full Scale Error
(2)
It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as:
PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error
(3)
INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight
line. The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in
the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n,
where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC is ensured not to
have any missing codes.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of
½ LSB above negative full scale.
OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition
from code 511 to 512.
OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the
output pins.
PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.
POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of
1½ LSB below positive full scale.
12
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply
limit to the Full-Scale output of the ADC with the supply at the maximum DC supply limit, expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or DC.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum
that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
(4)
where f1 is the RMS power of the fundamental (output) frequency and f2 through f7 are the RMS power of the first
six harmonic frequencies in the output spectrum.
SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in
the input frequency at the output and the power in its 2nd harmonic level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in
the input frequency at the output and the power in its 3rd harmonic level at the output.
Timing Diagrams
VINA
tAD
VINB
CLK N+5
CLK N
1/fCLK
CLK
tCH
Latency = 5
CLK Cycles
tCL
DRDY
(DDR)
tSU
tODB
tODA
D9-D0
AN-1
tH
BN-1
AN
BN
AN+1
BN+1
AN+2
BN+2
AN+3
Figure 1. LVDS Output Timing
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
13
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
VINA
tAD
VINB
CLK N+5
CLK N
1/fCLK
CLK
tCH
Latency=5.5
tCL
CLK Cycles
DRDYA
(DDR)
tOD
Data N-1
DA9-DA0
tSU
tH
Data N+1
Data N
Data N+2
DRDYB
(DDR)
Data N-1
DB9-DB0
Data N+1
Data N
Figure 2. CMOS Output Timing
Transfer Characteristic
Output Code
1023
1022
MID-SCALE
POINT
POSITIVE
FULL-SCALE
TRANSITION
(VFS+)
512
NEGATIVE
FULL-SCALE
TRANSITION
OFFSET
ERROR
(VFS-)
2
1
0
-1 * VREF
(VIN +) > (VIN -)
(VIN +) < (VIN -)
0.0V
1 * VREF
Analog Input Voltage (VIN +) - (VIN -)
Figure 3. Transfer Characteristic
14
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Typical Performance Characteristics DNL, INL
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, 50% Duty Cycle, DCS Enabled, LVDS Output, VCM = VRM, TA = 25°C.
DNL
INL
Figure 4.
Figure 5.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
15
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, 50% Duty Cycle, DCS disabled, LVDS Output, VCM = VRM, fIN = 70 MHz, TA = 25°C.
16
SNR, SINAD, SFDR
vs.
VA
Distortion
vs.
VA
Figure 6.
Figure 7.
SNR, SINAD, SFDR
vs.
Temperature
Distortion
vs.
Temperature
Figure 8.
Figure 9.
SNR, SINAD, SFDR
vs.
Clock Duty Cycle, fIN = 10MHz
Distortion
vs.
Clock Duty Cycle, fIN = 10MHz
Figure 10.
Figure 11.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, 50% Duty Cycle, DCS disabled, LVDS Output, VCM = VRM, fIN = 70 MHz, TA = 25°C.
SNR, SINAD, SFDR
vs.
Ext. Reference Voltage
Distortion
vs.
Ext. Reference Voltage
Figure 12.
Figure 13.
SNR, SINAD, SFDR
vs.
Clock Frequency
Distortion
vs.
Clock Frequency
Figure 14.
Figure 15.
SNR, SINAD, SFDR
vs.
Ext. VCM
Distortion
vs.
Ext. VCM
Figure 16.
Figure 17.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
17
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200
MHz, 50% Duty Cycle, DCS disabled, LVDS Output, VCM = VRM, fIN = 70 MHz, TA = 25°C.
Spectral Response @ 10 MHz Input
Spectral Response @ 70 MHz Input
Figure 18.
Figure 19.
Spectral Response @ 170 MHz Input
IMD, fIN1 = 69 MHz, fIN2 = 70 MHz
Figure 20.
Figure 21.
Total Power
vs.
Clock Frequency, fIN = 10 MHz
Figure 22.
18
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
Operating on a single +1.8V supply, the ADC10DV200 digitizes two differential analog input signals to 10 bits,
using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to
ensure maximum performance. The user has the choice of using an internal 0.75V stable reference, or using an
external 0.75V reference. Any external reference is buffered on-chip to ease the task of driving that pin. Duty
cycle stabilization and output data format are selectable using the quad state function DF/DCS pin (pin 20). The
output data can be set for offset binary or two's complement.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
19
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
APPLICATIONS INFORMATION
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC10DV200:
1.7V ≤ VA ≤ 1.9V
1.7V ≤ VDR ≤ VA
45 MHz ≤ fCLK ≤ 200 MHz, with DCS off
65 MHz ≤ fCLK ≤ 200 MHz, with DCS on
0.75V internal reference
VREF = 0.75V (for an external reference)
VCM = 0.9V (from VRM)
ANALOG INPUTS
Signal Inputs
Differential Analog Input Pins
The ADC10DV200 has a pair of analog signal input pins for each of two channels. VIN+ and VIN− form a
differential input pair. The input signal, VIN, is defined as
VIN = (VIN+) – (VIN−)
(5)
Figure 23shows the expected input signal range. Note that the common mode input voltage, VCM, should be
0.9V. Using VRM (pins 5,11) for VCM will ensure the proper input common mode level for the analog input signal.
The positive peaks of the individual input signals should each never exceed 2.2V. Each analog input pin of the
differential pair should have a maximum peak-to-peak voltage of 1.5V, be 180° out of phase with each other and
be centered around VCM.The peak-to-peak voltage swing at each analog input pin should not exceed the 1V or
the output data will be clipped.
Figure 23. Expected Input Signal Range
For single frequency sine waves the full scale error in LSB can be described as approximately
EFS = 1024 ( 1 - sin (90° + dev))
(6)
Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship
to each other (see Figure 24). For single frequency inputs, angular errors result in a reduction of the effective full
scale input. For complex waveforms, however, angular errors will result in distortion.
20
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
Figure 24. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause
Distortion
It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source
impedance for the differential inputs will improve even ordered harmonic performance (particularly second
harmonic).
Table 2 indicates the input to output relationship of the ADC10DV200.
Table 2. Input to Output Relationship
VIN
VIN
Binary Output
2’s Complement Output
VCM − VREF/2
VCM + VREF/2
00 0000 0000
10 0000 0000
VCM − VREF/4
VCM + VREF/4
01 0000 0000
11 0000 0000
−
+
VCM
VCM
10 0000 0000
00 0000 0000
VCM + VREF/4
VCM − VREF/4
11 0000 0000
01 0000 0000
VCM + VREF/2
VCM − VREF/2
11 1111 1111
01 1111 1111
Negative Full-Scale
Mid-Scale
Positive Full-Scale
Driving the Analog Inputs
The VIN+ and the VIN− inputs of the ADC10DV200 have an internal sample-and-hold circuit which consists of an
analog switch followed by a switched-capacitor amplifier.
Figure 25 and Figure 26 show examples of single-ended to differential conversion circuits. The circuit in
Figure 25 works well for input frequencies up to approximately 70MHz, while the circuit in Figure 26 works well
above 70MHz.
VIN
0.1 PF
20:
ADT1-1WT
18 pF
50:
ADC
Input
0.1 PF
0.1 PF
20:
VRM
Figure 25. Low Input Frequency Transformer Drive Circuit
VIN
ETC1-1-13
25:
0.1 PF
30:
27 pF
25:
0.1 PF
ADC
Input
30:
ETC1-1-13
VRM
0.1 PF
Figure 26. High Input Frequency Transformer Drive Circuit
One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF
transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs
for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the
analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed
to the ADC core.
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
21
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
Input Common Mode Voltage
The input common mode voltage, VCM, should be in the range of 0.8V to 1.0V and be a value such that the peak
excursions of the analog signal do not go more negative than ground or more positive than the VA supply. It is
recommended to use VRM (pins 5,11) as the input common mode voltage.
If the ADC10DV200 is operated with VA=1.8V, a resistor of approximately 1KΩ should be used from the VRM pin
to AGND. This will help maintain stability over the entire temperature range when using a high supply voltage.
Reference Pins
The ADC10DV200 is designed to operate with an internal or external voltage reference. The voltage on the VREF
pin selects the source and level of the reference voltage. An internal 0.75 Volt reference is used when a voltage
between 1.4 V to VA is applied to the VREF pin. An internal 0.5 Volt reference is used when a voltage between
0.2V and AGND is applied to the VREF pin. If a voltage between 0.2V and 1.4V is applied to the VREF pin, then
that voltage is used for the reference. SNR will improve without a significant degradation in SFDR for VREF=1.0V.
SNR will decrease if VREF=0.5V, yet linearity will be maintained. If using an external reference the VREF pin
should be bypassed to ground with a 0.1 µF capacitor close to the reference input pin.
It is important that all grounds associated with the reference voltage and the analog input signal make connection
to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.
The Reference Bypass Pins (VRP, VRM, and VRN) for channels A and B are made available for bypass purposes.
These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor
placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and
VRN as close to the pins as possible. This configuration is shown in Figure 27. It is necessary to avoid reference
oscillation, which could result in reduced SFDR and/or SNR. VRM may be loaded to 1mA for use as a
temperature stable 0.9V reference. The remaining pins should not be loaded.
Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may
result in degraded noise performance. Loading any of these pins, other than VRM may result in performance
degradation.
The nominal voltages for the reference bypass pins are as follows:
VRM = 0.9 V
VRP = 1.33 V
VRN = 0.55 V
DF/DCS Pin
Duty cycle stabilization and output data format are selectable using this quad state function pin. When enabled,
duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate
a stable internal clock, improving the performance of the part. See Table 1 for DF/DCS voltage vs output format
description. DCS mode of operation is limited to 65 MHz ≤ fCLK ≤ 200 MHz.
DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK, PD_A, PD_B, and OUTSEL.
Clock Input
The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input
should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input
signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock
source through a high speed buffer gate. The trace carrying the clock signal should be as short as possible and
should not cross any other signal line, analog or digital, not even at 90°.
If the clock is interrupted, or its frequency is too low, the charge on the internal capacitors can dissipate to the
point where the accuracy of the output data will degrade. This is what limits the minimum sample rate.
22
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
The clock line should be terminated at its source in the characteristic impedance of that line. Take care to
maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905
(SNLA035) for information on setting characteristic impedance. It is highly desirable that the the source driving
the ADC clock pins only drive that pin.
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC10DV200 has a Duty Cycle Stabilizer.
DIGITAL OUTPUTS
Digital outputs consist of the LVDS signals D0-D9, OR, and DRDY.
The ADC10DV200 has 12 LVDS compatible data output pins: 10 data output pins corresponding to the
converted input value, a data ready (DRDY) signal that should be used to capture the output data and an overrange indicator (OR) which is set high when the sample amplitude exceeds the 10-Bit conversion range. Valid
data is present at these outputs while the PD pin is low. A-Channel data should be captured and latched with the
rising edge of the DRDY signal and B-Channel data should be captured and latched with the falling edge of
DRDY.
To minimize noise due to output switching, the load currents at the digital outputs should be minimized. This can
be achieved by keeping the PCB traces less than 2 inches long; longer traces are more susceptible to noise. The
characteristic impedance of the LVDS traces should be 100Ω, and the effective capacitance < 10pF. Try to place
the 100Ω termination resistor as close to the receiving circuit as possible. (See Figure 27)
+1.8V
+1.8V
+1.8V
2x 0.1 PF
2x 0.1 PF
5x 0.1 PF
+
17
11
0.1 PF
0.1 PF
0.1 PF
6
0.1 PF
7
0.1 PF
20
31
45
21
54
DRDYDRDY+
0.1 PF
VRPB
VRNB
ADC10DV200
18 pF
2
13
14
20
VINA+
VINA-
ADT1-1WT
50
VIN_B
1
20
0.1 PF
0.1 PF
18 pF
2
0.1 PF
20
3
2
VINB+
VINB-
ADT1-1WT
DF/DCS
PD_A
PD_B
36
53
23
CLK+
CLK-
-
+
-
50
D949
D9+
48
D847
D8+
44
D743
D7+
42
D641
D6+
40
D539
D5+
35
D434
D4+
33
D332
D3+
29
D228
D2+
27
D126
D1+
25
D024
D0+
100
100
100
100
100
100
100
100
100
100
+
+
+
+
-
Receiver
+
+
+
+
+
+
-
DF/DCS
PD_A
PD_B
OUTSEL
1
4
12
15
22
55
58
AGND
AGND
AGND
AGND
AGND
AGND
AGND
OUTSEL
20
100
+
DR GND
DR GND
56
100
38
37
30
46
57
Crystal
Oscillator
52
51
VRMB
0.1 PF
1
0.1 PF
OROR+
10 V A
RP
9
VRNA
5
0.1 PF
0.1 PF
VREF
VRMA
0.1 PF
50
VIN_A
VDR
VDR
0.1 PF
VD
VD
VA
VA
VA
VA
VA
8
16
18
59
60
10 PF
Figure 27. Application Circuit
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
23
ADC10DV200
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
www.ti.com
POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 0.1 µF capacitor and with a 100 pF ceramic chip capacitor
close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC10DV200 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100 mVP-P.
No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be
especially careful of this during power turn on and turn off.
24
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
ADC10DV200
www.ti.com
SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013
REVISION HISTORY
Changes from Original (April 2013) to Revision A
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: ADC10DV200
25
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
工商网监
湘ICP备2023018690号
